arch/mips/netlogic/xlp/nlm_hal.c

   1 /*
   2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3  * reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the NetLogic
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/types.h>
  36 #include <linux/kernel.h>
  37 #include <linux/mm.h>
  38 #include <linux/delay.h>
  39
  40 #include <asm/mipsregs.h>
  41 #include <asm/time.h>
  42
  43 #include <asm/netlogic/common.h>
  44 #include <asm/netlogic/haldefs.h>
  45 #include <asm/netlogic/xlp-hal/iomap.h>
  46 #include <asm/netlogic/xlp-hal/xlp.h>
  47 #include <asm/netlogic/xlp-hal/bridge.h>
  48 #include <asm/netlogic/xlp-hal/pic.h>
  49 #include <asm/netlogic/xlp-hal/sys.h>
  50
  51 /* Main initialization */
  52 void nlm_node_init(int node)
  53 {
  54         struct nlm_soc_info *nodep;
  55
  56         nodep = nlm_get_node(node);
  57         nodep->sysbase = nlm_get_sys_regbase(node);
  58         nodep->picbase = nlm_get_pic_regbase(node);
  59         nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
  60         spin_lock_init(&nodep->piclock);
  61 }
  62
  63 int nlm_irq_to_irt(int irq)
  64 {
  65         uint64_t pcibase;
  66         int devoff, irt;
  67
  68         switch (irq) {
  69         case PIC_UART_0_IRQ:
  70                 devoff = XLP_IO_UART0_OFFSET(0);
  71                 break;
  72         case PIC_UART_1_IRQ:
  73                 devoff = XLP_IO_UART1_OFFSET(0);
  74                 break;
  75         case PIC_EHCI_0_IRQ:
  76                 devoff = XLP_IO_USB_EHCI0_OFFSET(0);
  77                 break;
  78         case PIC_EHCI_1_IRQ:
  79                 devoff = XLP_IO_USB_EHCI1_OFFSET(0);
  80                 break;
  81         case PIC_OHCI_0_IRQ:
  82                 devoff = XLP_IO_USB_OHCI0_OFFSET(0);
  83                 break;
  84         case PIC_OHCI_1_IRQ:
  85                 devoff = XLP_IO_USB_OHCI1_OFFSET(0);
  86                 break;
  87         case PIC_OHCI_2_IRQ:
  88                 devoff = XLP_IO_USB_OHCI2_OFFSET(0);
  89                 break;
  90         case PIC_OHCI_3_IRQ:
  91                 devoff = XLP_IO_USB_OHCI3_OFFSET(0);
  92                 break;
  93         case PIC_MMC_IRQ:
  94                 devoff = XLP_IO_SD_OFFSET(0);
  95                 break;
  96         case PIC_I2C_0_IRQ:
  97                 devoff = XLP_IO_I2C0_OFFSET(0);
  98                 break;
  99         case PIC_I2C_1_IRQ:
 100                 devoff = XLP_IO_I2C1_OFFSET(0);
 101                 break;
 102         default:
 103                 devoff = 0;
 104                 break;
 105         }
 106
 107         if (devoff != 0) {
 108                 pcibase = nlm_pcicfg_base(devoff);
 109                 irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
 110                 /* HW bug, I2C 1 irt entry is off by one */
 111                 if (irq == PIC_I2C_1_IRQ)
 112                         irt = irt + 1;
 113         } else if (irq >= PIC_PCIE_LINK_0_IRQ && irq <= PIC_PCIE_LINK_3_IRQ) {
 114                 /* HW bug, PCI IRT entries are bad on early silicon, fix */
 115                 irt = PIC_IRT_PCIE_LINK_INDEX(irq - PIC_PCIE_LINK_0_IRQ);
 116         } else {
 117                 irt = -1;
 118         }
 119         return irt;
 120 }
 121
 122 unsigned int nlm_get_core_frequency(int node, int core)
 123 {
 124         unsigned int pll_divf, pll_divr, dfs_div, ext_div;
 125         unsigned int rstval, dfsval, denom;
 126         uint64_t num, sysbase;
 127
 128         sysbase = nlm_get_node(node)->sysbase;
 129         rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
 130         dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
 131         pll_divf = ((rstval >> 10) & 0x7f) + 1;
 132         pll_divr = ((rstval >> 8)  & 0x3) + 1;
 133         ext_div  = ((rstval >> 30) & 0x3) + 1;
 134         dfs_div  = ((dfsval >> (core * 4)) & 0xf) + 1;
 135
 136         num = 800000000ULL * pll_divf;
 137         denom = 3 * pll_divr * ext_div * dfs_div;
 138         do_div(num, denom);
 139         return (unsigned int)num;
 140 }
 141
 142 unsigned int nlm_get_cpu_frequency(void)
 143 {
 144         return nlm_get_core_frequency(0, 0);
 145 }
 146
 147 /*
 148  * Fills upto 8 pairs of entries containing the DRAM map of a node
 149  * if n < 0, get dram map for all nodes
 150  */
 151 int xlp_get_dram_map(int n, uint64_t *dram_map)
 152 {
 153         uint64_t bridgebase, base, lim;
 154         uint32_t val;
 155         int i, node, rv;
 156
 157         /* Look only at mapping on Node 0, we don't handle crazy configs */
 158         bridgebase = nlm_get_bridge_regbase(0);
 159         rv = 0;
 160         for (i = 0; i < 8; i++) {
 161                 val = nlm_read_bridge_reg(bridgebase,
 162                                         BRIDGE_DRAM_NODE_TRANSLN(i));
 163                 node = (val >> 1) & 0x3;
 164                 if (n >= 0 && n != node)
 165                         continue;
 166                 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
 167                 val = (val >>  12) & 0xfffff;
 168                 base = (uint64_t) val << 20;
 169                 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
 170                 val = (val >>  12) & 0xfffff;
 171                 if (val == 0)   /* BAR not used */
 172                         continue;
 173                 lim = ((uint64_t)val + 1) << 20;
 174                 dram_map[rv] = base;
 175                 dram_map[rv + 1] = lim;
 176                 rv += 2;
 177         }
 178         return rv;
 179 }