arch/mips/netlogic/xlp/nlm_hal.c

   1 /*
   2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3  * reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the NetLogic
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/types.h>
  36 #include <linux/kernel.h>
  37 #include <linux/mm.h>
  38 #include <linux/delay.h>
  39
  40 #include <asm/mipsregs.h>
  41 #include <asm/time.h>
  42
  43 #include <asm/netlogic/common.h>
  44 #include <asm/netlogic/haldefs.h>
  45 #include <asm/netlogic/xlp-hal/iomap.h>
  46 #include <asm/netlogic/xlp-hal/xlp.h>
  47 #include <asm/netlogic/xlp-hal/bridge.h>
  48 #include <asm/netlogic/xlp-hal/pic.h>
  49 #include <asm/netlogic/xlp-hal/sys.h>
  50
  51 /* Main initialization */
  52 void nlm_node_init(int node)
  53 {
  54         struct nlm_soc_info *nodep;
  55
  56         nodep = nlm_get_node(node);
  57         if (node == 0)
  58                 nodep->coremask = 1;    /* node 0, boot cpu */
  59         nodep->sysbase = nlm_get_sys_regbase(node);
  60         nodep->picbase = nlm_get_pic_regbase(node);
  61         nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
  62         if (cpu_is_xlp9xx())
  63                 nodep->socbus = xlp9xx_get_socbus(node);
  64         else
  65                 nodep->socbus = 0;
  66         spin_lock_init(&nodep->piclock);
  67 }
  68
  69 static int xlp9xx_irq_to_irt(int irq)
  70 {
  71         switch (irq) {
  72         case PIC_GPIO_IRQ:
  73                 return 12;
  74         case PIC_9XX_XHCI_0_IRQ:
  75                 return 114;
  76         case PIC_9XX_XHCI_1_IRQ:
  77                 return 115;
  78         case PIC_UART_0_IRQ:
  79                 return 133;
  80         case PIC_UART_1_IRQ:
  81                 return 134;
  82         case PIC_SATA_IRQ:
  83                 return 143;
  84         case PIC_SPI_IRQ:
  85                 return 152;
  86         case PIC_MMC_IRQ:
  87                 return 153;
  88         case PIC_PCIE_LINK_LEGACY_IRQ(0):
  89         case PIC_PCIE_LINK_LEGACY_IRQ(1):
  90         case PIC_PCIE_LINK_LEGACY_IRQ(2):
  91         case PIC_PCIE_LINK_LEGACY_IRQ(3):
  92                 return 191 + irq - PIC_PCIE_LINK_LEGACY_IRQ_BASE;
  93         }
  94         return -1;
  95 }
  96
  97 static int xlp_irq_to_irt(int irq)
  98 {
  99         uint64_t pcibase;
 100         int devoff, irt;
 101
 102         devoff = 0;
 103         switch (irq) {
 104         case PIC_UART_0_IRQ:
 105                 devoff = XLP_IO_UART0_OFFSET(0);
 106                 break;
 107         case PIC_UART_1_IRQ:
 108                 devoff = XLP_IO_UART1_OFFSET(0);
 109                 break;
 110         case PIC_MMC_IRQ:
 111                 devoff = XLP_IO_MMC_OFFSET(0);
 112                 break;
 113         case PIC_I2C_0_IRQ:     /* I2C will be fixed up */
 114         case PIC_I2C_1_IRQ:
 115         case PIC_I2C_2_IRQ:
 116         case PIC_I2C_3_IRQ:
 117                 if (cpu_is_xlpii())
 118                         devoff = XLP2XX_IO_I2C_OFFSET(0);
 119                 else
 120                         devoff = XLP_IO_I2C0_OFFSET(0);
 121                 break;
 122         case PIC_SATA_IRQ:
 123                 devoff = XLP_IO_SATA_OFFSET(0);
 124                 break;
 125         case PIC_GPIO_IRQ:
 126                 devoff = XLP_IO_GPIO_OFFSET(0);
 127                 break;
 128         case PIC_NAND_IRQ:
 129                 devoff = XLP_IO_NAND_OFFSET(0);
 130                 break;
 131         case PIC_SPI_IRQ:
 132                 devoff = XLP_IO_SPI_OFFSET(0);
 133                 break;
 134         default:
 135                 if (cpu_is_xlpii()) {
 136                         switch (irq) {
 137                                 /* XLP2XX has three XHCI USB controller */
 138                         case PIC_2XX_XHCI_0_IRQ:
 139                                 devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0);
 140                                 break;
 141                         case PIC_2XX_XHCI_1_IRQ:
 142                                 devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0);
 143                                 break;
 144                         case PIC_2XX_XHCI_2_IRQ:
 145                                 devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0);
 146                                 break;
 147                         }
 148                 } else {
 149                         switch (irq) {
 150                         case PIC_EHCI_0_IRQ:
 151                                 devoff = XLP_IO_USB_EHCI0_OFFSET(0);
 152                                 break;
 153                         case PIC_EHCI_1_IRQ:
 154                                 devoff = XLP_IO_USB_EHCI1_OFFSET(0);
 155                                 break;
 156                         case PIC_OHCI_0_IRQ:
 157                                 devoff = XLP_IO_USB_OHCI0_OFFSET(0);
 158                                 break;
 159                         case PIC_OHCI_1_IRQ:
 160                                 devoff = XLP_IO_USB_OHCI1_OFFSET(0);
 161                                 break;
 162                         case PIC_OHCI_2_IRQ:
 163                                 devoff = XLP_IO_USB_OHCI2_OFFSET(0);
 164                                 break;
 165                         case PIC_OHCI_3_IRQ:
 166                                 devoff = XLP_IO_USB_OHCI3_OFFSET(0);
 167                                 break;
 168                         }
 169                 }
 170         }
 171
 172         if (devoff != 0) {
 173                 pcibase = nlm_pcicfg_base(devoff);
 174                 irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
 175                 /* HW weirdness, I2C IRT entry has to be fixed up */
 176                 switch (irq) {
 177                 case PIC_I2C_1_IRQ:
 178                         irt = irt + 1; break;
 179                 case PIC_I2C_2_IRQ:
 180                         irt = irt + 2; break;
 181                 case PIC_I2C_3_IRQ:
 182                         irt = irt + 3; break;
 183                 }
 184         } else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
 185                         irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
 186                 /* HW bug, PCI IRT entries are bad on early silicon, fix */
 187                 irt = PIC_IRT_PCIE_LINK_INDEX(irq -
 188                                         PIC_PCIE_LINK_LEGACY_IRQ_BASE);
 189         } else {
 190                 irt = -1;
 191         }
 192         return irt;
 193 }
 194
 195 int nlm_irq_to_irt(int irq)
 196 {
 197         /* return -2 for irqs without 1-1 mapping */
 198         if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) && irq <= PIC_PCIE_LINK_MSI_IRQ(3))
 199                 return -2;
 200         if (irq >= PIC_PCIE_MSIX_IRQ(0) && irq <= PIC_PCIE_MSIX_IRQ(3))
 201                 return -2;
 202
 203         if (cpu_is_xlp9xx())
 204                 return xlp9xx_irq_to_irt(irq);
 205         else
 206                 return xlp_irq_to_irt(irq);
 207 }
 208
 209 static unsigned int nlm_xlp2_get_core_frequency(int node, int core)
 210 {
 211         unsigned int pll_post_div, ctrl_val0, ctrl_val1, denom;
 212         uint64_t num, sysbase, clockbase;
 213
 214         if (cpu_is_xlp9xx()) {
 215                 clockbase = nlm_get_clock_regbase(node);
 216                 ctrl_val0 = nlm_read_sys_reg(clockbase,
 217                                         SYS_9XX_CPU_PLL_CTRL0(core));
 218                 ctrl_val1 = nlm_read_sys_reg(clockbase,
 219                                         SYS_9XX_CPU_PLL_CTRL1(core));
 220         } else {
 221                 sysbase = nlm_get_node(node)->sysbase;
 222                 ctrl_val0 = nlm_read_sys_reg(sysbase,
 223                                                 SYS_CPU_PLL_CTRL0(core));
 224                 ctrl_val1 = nlm_read_sys_reg(sysbase,
 225                                                 SYS_CPU_PLL_CTRL1(core));
 226         }
 227
 228         /* Find PLL post divider value */
 229         switch ((ctrl_val0 >> 24) & 0x7) {
 230         case 1:
 231                 pll_post_div = 2;
 232                 break;
 233         case 3:
 234                 pll_post_div = 4;
 235                 break;
 236         case 7:
 237                 pll_post_div = 8;
 238                 break;
 239         case 6:
 240                 pll_post_div = 16;
 241                 break;
 242         case 0:
 243         default:
 244                 pll_post_div = 1;
 245                 break;
 246         }
 247
 248         num = 1000000ULL * (400 * 3 + 100 * (ctrl_val1 & 0x3f));
 249         denom = 3 * pll_post_div;
 250         do_div(num, denom);
 251
 252         return (unsigned int)num;
 253 }
 254
 255 static unsigned int nlm_xlp_get_core_frequency(int node, int core)
 256 {
 257         unsigned int pll_divf, pll_divr, dfs_div, ext_div;
 258         unsigned int rstval, dfsval, denom;
 259         uint64_t num, sysbase;
 260
 261         sysbase = nlm_get_node(node)->sysbase;
 262         rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
 263         dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
 264         pll_divf = ((rstval >> 10) & 0x7f) + 1;
 265         pll_divr = ((rstval >> 8)  & 0x3) + 1;
 266         ext_div  = ((rstval >> 30) & 0x3) + 1;
 267         dfs_div  = ((dfsval >> (core * 4)) & 0xf) + 1;
 268
 269         num = 800000000ULL * pll_divf;
 270         denom = 3 * pll_divr * ext_div * dfs_div;
 271         do_div(num, denom);
 272
 273         return (unsigned int)num;
 274 }
 275
 276 unsigned int nlm_get_core_frequency(int node, int core)
 277 {
 278         if (cpu_is_xlpii())
 279                 return nlm_xlp2_get_core_frequency(node, core);
 280         else
 281                 return nlm_xlp_get_core_frequency(node, core);
 282 }
 283
 284 /*
 285  * Calculate PIC frequency from PLL registers.
 286  * freq_out = (ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13) /
 287  *              ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
 288  */
 289 static unsigned int nlm_xlp2_get_pic_frequency(int node)
 290 {
 291         u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div, cpu_xlp9xx;
 292         u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
 293         u64 sysbase, pll_out_freq_num, ref_clk_select, clockbase, ref_clk;
 294
 295         sysbase = nlm_get_node(node)->sysbase;
 296         clockbase = nlm_get_clock_regbase(node);
 297         cpu_xlp9xx = cpu_is_xlp9xx();
 298
 299         /* Find ref_clk_base */
 300         if (cpu_xlp9xx)
 301                 ref_clk_select = (nlm_read_sys_reg(sysbase,
 302                                 SYS_9XX_POWER_ON_RESET_CFG) >> 18) & 0x3;
 303         else
 304                 ref_clk_select = (nlm_read_sys_reg(sysbase,
 305                                         SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
 306         switch (ref_clk_select) {
 307         case 0:
 308                 ref_clk = 200000000ULL;
 309                 ref_div = 3;
 310                 break;
 311         case 1:
 312                 ref_clk = 100000000ULL;
 313                 ref_div = 1;
 314                 break;
 315         case 2:
 316                 ref_clk = 125000000ULL;
 317                 ref_div = 1;
 318                 break;
 319         case 3:
 320                 ref_clk = 400000000ULL;
 321                 ref_div = 3;
 322                 break;
 323         }
 324
 325         /* Find the clock source PLL device for PIC */
 326         if (cpu_xlp9xx) {
 327                 reg_select = nlm_read_sys_reg(clockbase,
 328                                 SYS_9XX_CLK_DEV_SEL) & 0x3;
 329                 switch (reg_select) {
 330                 case 0:
 331                         ctrl_val0 = nlm_read_sys_reg(clockbase,
 332                                         SYS_9XX_PLL_CTRL0);
 333                         ctrl_val2 = nlm_read_sys_reg(clockbase,
 334                                         SYS_9XX_PLL_CTRL2);
 335                         break;
 336                 case 1:
 337                         ctrl_val0 = nlm_read_sys_reg(clockbase,
 338                                         SYS_9XX_PLL_CTRL0_DEVX(0));
 339                         ctrl_val2 = nlm_read_sys_reg(clockbase,
 340                                         SYS_9XX_PLL_CTRL2_DEVX(0));
 341                         break;
 342                 case 2:
 343                         ctrl_val0 = nlm_read_sys_reg(clockbase,
 344                                         SYS_9XX_PLL_CTRL0_DEVX(1));
 345                         ctrl_val2 = nlm_read_sys_reg(clockbase,
 346                                         SYS_9XX_PLL_CTRL2_DEVX(1));
 347                         break;
 348                 case 3:
 349                         ctrl_val0 = nlm_read_sys_reg(clockbase,
 350                                         SYS_9XX_PLL_CTRL0_DEVX(2));
 351                         ctrl_val2 = nlm_read_sys_reg(clockbase,
 352                                         SYS_9XX_PLL_CTRL2_DEVX(2));
 353                         break;
 354                 }
 355         } else {
 356                 reg_select = (nlm_read_sys_reg(sysbase,
 357                                         SYS_CLK_DEV_SEL) >> 22) & 0x3;
 358                 switch (reg_select) {
 359                 case 0:
 360                         ctrl_val0 = nlm_read_sys_reg(sysbase,
 361                                         SYS_PLL_CTRL0);
 362                         ctrl_val2 = nlm_read_sys_reg(sysbase,
 363                                         SYS_PLL_CTRL2);
 364                         break;
 365                 case 1:
 366                         ctrl_val0 = nlm_read_sys_reg(sysbase,
 367                                         SYS_PLL_CTRL0_DEVX(0));
 368                         ctrl_val2 = nlm_read_sys_reg(sysbase,
 369                                         SYS_PLL_CTRL2_DEVX(0));
 370                         break;
 371                 case 2:
 372                         ctrl_val0 = nlm_read_sys_reg(sysbase,
 373                                         SYS_PLL_CTRL0_DEVX(1));
 374                         ctrl_val2 = nlm_read_sys_reg(sysbase,
 375                                         SYS_PLL_CTRL2_DEVX(1));
 376                         break;
 377                 case 3:
 378                         ctrl_val0 = nlm_read_sys_reg(sysbase,
 379                                         SYS_PLL_CTRL0_DEVX(2));
 380                         ctrl_val2 = nlm_read_sys_reg(sysbase,
 381                                         SYS_PLL_CTRL2_DEVX(2));
 382                         break;
 383                 }
 384         }
 385
 386         vco_post_div = (ctrl_val0 >> 5) & 0x7;
 387         pll_post_div = (ctrl_val0 >> 24) & 0x7;
 388         mdiv = ctrl_val2 & 0xff;
 389         fdiv = (ctrl_val2 >> 8) & 0x1fff;
 390
 391         /* Find PLL post divider value */
 392         switch (pll_post_div) {
 393         case 1:
 394                 pll_post_div = 2;
 395                 break;
 396         case 3:
 397                 pll_post_div = 4;
 398                 break;
 399         case 7:
 400                 pll_post_div = 8;
 401                 break;
 402         case 6:
 403                 pll_post_div = 16;
 404                 break;
 405         case 0:
 406         default:
 407                 pll_post_div = 1;
 408                 break;
 409         }
 410
 411         fdiv = fdiv/(1 << 13);
 412         pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
 413         pll_out_freq_den = (1 << vco_post_div) * pll_post_div * ref_div;
 414
 415         if (pll_out_freq_den > 0)
 416                 do_div(pll_out_freq_num, pll_out_freq_den);
 417
 418         /* PIC post divider, which happens after PLL */
 419         if (cpu_xlp9xx)
 420                 pic_div = nlm_read_sys_reg(clockbase,
 421                                 SYS_9XX_CLK_DEV_DIV) & 0x3;
 422         else
 423                 pic_div = (nlm_read_sys_reg(sysbase,
 424                                         SYS_CLK_DEV_DIV) >> 22) & 0x3;
 425         do_div(pll_out_freq_num, 1 << pic_div);
 426
 427         return pll_out_freq_num;
 428 }
 429
 430 unsigned int nlm_get_pic_frequency(int node)
 431 {
 432         if (cpu_is_xlpii())
 433                 return nlm_xlp2_get_pic_frequency(node);
 434         else
 435                 return 133333333;
 436 }
 437
 438 unsigned int nlm_get_cpu_frequency(void)
 439 {
 440         return nlm_get_core_frequency(0, 0);
 441 }
 442
 443 /*
 444  * Fills upto 8 pairs of entries containing the DRAM map of a node
 445  * if n < 0, get dram map for all nodes
 446  */
 447 int xlp_get_dram_map(int n, uint64_t *dram_map)
 448 {
 449         uint64_t bridgebase, base, lim;
 450         uint32_t val;
 451         unsigned int barreg, limreg, xlatreg;
 452         int i, node, rv;
 453
 454         /* Look only at mapping on Node 0, we don't handle crazy configs */
 455         bridgebase = nlm_get_bridge_regbase(0);
 456         rv = 0;
 457         for (i = 0; i < 8; i++) {
 458                 if (cpu_is_xlp9xx()) {
 459                         barreg = BRIDGE_9XX_DRAM_BAR(i);
 460                         limreg = BRIDGE_9XX_DRAM_LIMIT(i);
 461                         xlatreg = BRIDGE_9XX_DRAM_NODE_TRANSLN(i);
 462                 } else {
 463                         barreg = BRIDGE_DRAM_BAR(i);
 464                         limreg = BRIDGE_DRAM_LIMIT(i);
 465                         xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i);
 466                 }
 467                 if (n >= 0) {
 468                         /* node specified, get node mapping of BAR */
 469                         val = nlm_read_bridge_reg(bridgebase, xlatreg);
 470                         node = (val >> 1) & 0x3;
 471                         if (n != node)
 472                                 continue;
 473                 }
 474                 val = nlm_read_bridge_reg(bridgebase, barreg);
 475                 val = (val >>  12) & 0xfffff;
 476                 base = (uint64_t) val << 20;
 477                 val = nlm_read_bridge_reg(bridgebase, limreg);
 478                 val = (val >>  12) & 0xfffff;
 479                 if (val == 0)   /* BAR not used */
 480                         continue;
 481                 lim = ((uint64_t)val + 1) << 20;
 482                 dram_map[rv] = base;
 483                 dram_map[rv + 1] = lim;
 484                 rv += 2;
 485         }
 486         return rv;
 487 }