arch/mips/netlogic/xlp/wakeup.c

   1 /*
   2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3  * reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the NetLogic
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/init.h>
  36 #include <linux/kernel.h>
  37 #include <linux/threads.h>
  38
  39 #include <asm/asm.h>
  40 #include <asm/asm-offsets.h>
  41 #include <asm/mipsregs.h>
  42 #include <asm/addrspace.h>
  43 #include <asm/string.h>
  44
  45 #include <asm/netlogic/haldefs.h>
  46 #include <asm/netlogic/common.h>
  47 #include <asm/netlogic/mips-extns.h>
  48
  49 #include <asm/netlogic/xlp-hal/iomap.h>
  50 #include <asm/netlogic/xlp-hal/pic.h>
  51 #include <asm/netlogic/xlp-hal/xlp.h>
  52 #include <asm/netlogic/xlp-hal/sys.h>
  53
  54 static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
  55 {
  56         uint32_t coremask, value;
  57         int count;
  58
  59         coremask = (1 << core);
  60
  61         /* Enable CPU clock */
  62         value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
  63         value &= ~coremask;
  64         nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
  65
  66         /* Remove CPU Reset */
  67         value = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
  68         value &= ~coremask;
  69         nlm_write_sys_reg(sysbase, SYS_CPU_RESET, value);
  70
  71         /* Poll for CPU to mark itself coherent */
  72         count = 100000;
  73         do {
  74                 value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
  75         } while ((value & coremask) != 0 && --count > 0);
  76
  77         return count != 0;
  78 }
  79
  80 static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
  81 {
  82         struct nlm_soc_info *nodep;
  83         uint64_t syspcibase;
  84         uint32_t syscoremask;
  85         int core, n, cpu, count, val;
  86
  87         for (n = 0; n < NLM_NR_NODES; n++) {
  88                 syspcibase = nlm_get_sys_pcibase(n);
  89                 if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
  90                         break;
  91
  92                 /* read cores in reset from SYS */
  93                 if (n != 0)
  94                         nlm_node_init(n);
  95                 nodep = nlm_get_node(n);
  96                 syscoremask = nlm_read_sys_reg(nodep->sysbase, SYS_CPU_RESET);
  97                 /* The boot cpu */
  98                 if (n == 0) {
  99                         syscoremask |= 1;
 100                         nodep->coremask = 1;
 101                 }
 102
 103                 for (core = 0; core < NLM_CORES_PER_NODE; core++) {
 104                         /* we will be on node 0 core 0 */
 105                         if (n == 0 && core == 0)
 106                                 continue;
 107
 108                         /* see if the core exists */
 109                         if ((syscoremask & (1 << core)) == 0)
 110                                 continue;
 111
 112                         /* see if at least the first hw thread is enabled */
 113                         cpu = (n * NLM_CORES_PER_NODE + core)
 114                                                 * NLM_THREADS_PER_CORE;
 115                         if (!cpumask_test_cpu(cpu, wakeup_mask))
 116                                 continue;
 117
 118                         /* wake up the core */
 119                         if (!xlp_wakeup_core(nodep->sysbase, n, core))
 120                                 continue;
 121
 122                         /* core is up */
 123                         nodep->coremask |= 1u << core;
 124
 125                         /* spin until the first hw thread sets its ready */
 126                         count = 0x20000000;
 127                         do {
 128                                 val = *(volatile int *)&nlm_cpu_ready[cpu];
 129                         } while (val == 0 && --count > 0);
 130                 }
 131         }
 132 }
 133
 134 void xlp_wakeup_secondary_cpus()
 135 {
 136         /*
 137          * In case of u-boot, the secondaries are in reset
 138          * first wakeup core 0 threads
 139          */
 140         xlp_boot_core0_siblings();
 141
 142         /* now get other cores out of reset */
 143         xlp_enable_secondary_cores(&nlm_cpumask);
 144 }