arch/mips/pci/ops-au1000.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  *      Alchemy/AMD Au1x00 pci support.
   4  *
   5  * Copyright 2001,2002,2003 MontaVista Software Inc.
   6  * Author: MontaVista Software, Inc.
   7  *              ppopov@mvista.com or source@mvista.com
   8  *
   9  *  Support for all devices (greater than 16) added by David Gathright.
  10  *
  11  *  This program is free software; you can redistribute  it and/or modify it
  12  *  under  the terms of  the GNU General  Public License as published by the
  13  *  Free Software Foundation;  either version 2 of the  License, or (at your
  14  *  option) any later version.
  15  *
  16  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  17  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  18  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  19  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  20  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  22  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  23  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  24  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  *  You should have received a copy of the  GNU General Public License along
  28  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  29  *  675 Mass Ave, Cambridge, MA 02139, USA.
  30  */
  31 #include <linux/config.h>
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/kernel.h>
  35 #include <linux/init.h>
  36 #include <linux/vmalloc.h>
  37
  38 #include <asm/mach-au1x00/au1000.h>
  39
  40 #undef DEBUG
  41 #ifdef DEBUG
  42 #define DBG(x...) printk(x)
  43 #else
  44 #define DBG(x...)
  45 #endif
  46
  47 #define PCI_ACCESS_READ  0
  48 #define PCI_ACCESS_WRITE 1
  49
  50
  51 int (*board_pci_idsel)(unsigned int devsel, int assert);
  52
  53 void mod_wired_entry(int entry, unsigned long entrylo0,
  54                 unsigned long entrylo1, unsigned long entryhi,
  55                 unsigned long pagemask)
  56 {
  57         unsigned long old_pagemask;
  58         unsigned long old_ctx;
  59
  60         /* Save old context and create impossible VPN2 value */
  61         old_ctx = read_c0_entryhi() & 0xff;
  62         old_pagemask = read_c0_pagemask();
  63         write_c0_index(entry);
  64         write_c0_pagemask(pagemask);
  65         write_c0_entryhi(entryhi);
  66         write_c0_entrylo0(entrylo0);
  67         write_c0_entrylo1(entrylo1);
  68         tlb_write_indexed();
  69         write_c0_entryhi(old_ctx);
  70         write_c0_pagemask(old_pagemask);
  71 }
  72
  73 struct vm_struct *pci_cfg_vm;
  74 static int pci_cfg_wired_entry;
  75 static int first_cfg = 1;
  76 unsigned long last_entryLo0, last_entryLo1;
  77
  78 static int config_access(unsigned char access_type, struct pci_bus *bus,
  79                          unsigned int dev_fn, unsigned char where,
  80                          u32 * data)
  81 {
  82 #if defined( CONFIG_SOC_AU1500 ) || defined( CONFIG_SOC_AU1550 )
  83         unsigned int device = PCI_SLOT(dev_fn);
  84         unsigned int function = PCI_FUNC(dev_fn);
  85         unsigned long offset, status;
  86         unsigned long cfg_base;
  87         unsigned long flags;
  88         int error = PCIBIOS_SUCCESSFUL;
  89         unsigned long entryLo0, entryLo1;
  90
  91         if (device > 19) {
  92                 *data = 0xffffffff;
  93                 return -1;
  94         }
  95
  96         local_irq_save(flags);
  97         au_writel(((0x2000 << 16) | (au_readl(Au1500_PCI_STATCMD) & 0xffff)),
  98                         Au1500_PCI_STATCMD);
  99         au_sync_udelay(1);
 100
 101         /*
 102          * We can't ioremap the entire pci config space because it's
 103          * too large. Nor can we call ioremap dynamically because some
 104          * device drivers use the pci config routines from within
 105          * interrupt handlers and that becomes a problem in get_vm_area().
 106          * We use one wired tlb to handle all config accesses for all
 107          * busses. To improve performance, if the current device
 108          * is the same as the last device accessed, we don't touch the
 109          * tlb.
 110          */
 111         if (first_cfg) {
 112                 /* reserve a wired entry for pci config accesses */
 113                 first_cfg = 0;
 114                 pci_cfg_vm = get_vm_area(0x2000, 0);
 115                 if (!pci_cfg_vm)
 116                         panic (KERN_ERR "PCI unable to get vm area\n");
 117                 pci_cfg_wired_entry = read_c0_wired();
 118                 add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K);
 119                 last_entryLo0  = last_entryLo1 = 0xffffffff;
 120         }
 121
 122         /* Allow board vendors to implement their own off-chip idsel.
 123          * If it doesn't succeed, may as well bail out at this point.
 124          */
 125         if (board_pci_idsel) {
 126                 if (board_pci_idsel(device, 1) == 0) {
 127                         *data = 0xffffffff;
 128                         local_irq_restore(flags);
 129                         return -1;
 130                 }
 131         }
 132
 133         /* setup the config window */
 134         if (bus->number == 0) {
 135                 cfg_base = ((1<<device)<<11);
 136         } else {
 137                 cfg_base = 0x80000000 | (bus->number<<16) | (device<<11);
 138         }
 139
 140         /* setup the lower bits of the 36 bit address */
 141         offset = (function << 8) | (where & ~0x3);
 142         /* pick up any address that falls below the page mask */
 143         offset |= cfg_base & ~PAGE_MASK;
 144
 145         /* page boundary */
 146         cfg_base = cfg_base & PAGE_MASK;
 147
 148         entryLo0 = (6 << 26)  | (cfg_base >> 6) | (2 << 3) | 7;
 149         entryLo1 = (6 << 26)  | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
 150
 151         if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) {
 152                 mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1,
 153                                 (unsigned long)pci_cfg_vm->addr, PM_4K);
 154                 last_entryLo0 = entryLo0;
 155                 last_entryLo1 = entryLo1;
 156         }
 157
 158         if (access_type == PCI_ACCESS_WRITE) {
 159                 au_writel(*data, (int)(pci_cfg_vm->addr + offset));
 160         } else {
 161                 *data = au_readl((int)(pci_cfg_vm->addr + offset));
 162         }
 163         au_sync_udelay(2);
 164
 165         DBG("cfg_access %d bus->number %d dev %d at %x *data %x conf %x\n",
 166                         access_type, bus->number, device, where, *data, offset);
 167
 168         /* check master abort */
 169         status = au_readl(Au1500_PCI_STATCMD);
 170
 171         if (status & (1<<29)) {
 172                 *data = 0xffffffff;
 173                 error = -1;
 174                 DBG("Au1x Master Abort\n");
 175         } else if ((status >> 28) & 0xf) {
 176                 DBG("PCI ERR detected: status %x\n", status);
 177                 *data = 0xffffffff;
 178                 error = -1;
 179         }
 180
 181         /* Take away the idsel.
 182         */
 183         if (board_pci_idsel) {
 184                 (void)board_pci_idsel(device, 0);
 185         }
 186
 187         local_irq_restore(flags);
 188         return error;
 189 #endif
 190 }
 191
 192 static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
 193                             int where, u8 * val)
 194 {
 195         u32 data;
 196         int ret;
 197
 198         ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 199         if (where & 1)
 200                 data >>= 8;
 201         if (where & 2)
 202                 data >>= 16;
 203         *val = data & 0xff;
 204         return ret;
 205 }
 206
 207
 208 static int read_config_word(struct pci_bus *bus, unsigned int devfn,
 209                             int where, u16 * val)
 210 {
 211         u32 data;
 212         int ret;
 213
 214         ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 215         if (where & 2)
 216                 data >>= 16;
 217         *val = data & 0xffff;
 218         return ret;
 219 }
 220
 221 static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
 222                              int where, u32 * val)
 223 {
 224         int ret;
 225
 226         ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
 227         return ret;
 228 }
 229
 230 static int
 231 write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
 232                   u8 val)
 233 {
 234         u32 data = 0;
 235
 236         if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 237                 return -1;
 238
 239         data = (data & ~(0xff << ((where & 3) << 3))) |
 240             (val << ((where & 3) << 3));
 241
 242         if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 243                 return -1;
 244
 245         return PCIBIOS_SUCCESSFUL;
 246 }
 247
 248 static int
 249 write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
 250                   u16 val)
 251 {
 252         u32 data = 0;
 253
 254         if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 255                 return -1;
 256
 257         data = (data & ~(0xffff << ((where & 3) << 3))) |
 258             (val << ((where & 3) << 3));
 259
 260         if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 261                 return -1;
 262
 263
 264         return PCIBIOS_SUCCESSFUL;
 265 }
 266
 267 static int
 268 write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
 269                    u32 val)
 270 {
 271         if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
 272                 return -1;
 273
 274         return PCIBIOS_SUCCESSFUL;
 275 }
 276
 277 static int config_read(struct pci_bus *bus, unsigned int devfn,
 278                        int where, int size, u32 * val)
 279 {
 280         switch (size) {
 281         case 1: {
 282                         u8 _val;
 283                         int rc = read_config_byte(bus, devfn, where, &_val);
 284                         *val = _val;
 285                         return rc;
 286                 }
 287        case 2: {
 288                         u16 _val;
 289                         int rc = read_config_word(bus, devfn, where, &_val);
 290                         *val = _val;
 291                         return rc;
 292                 }
 293         default:
 294                 return read_config_dword(bus, devfn, where, val);
 295         }
 296 }
 297
 298 static int config_write(struct pci_bus *bus, unsigned int devfn,
 299                         int where, int size, u32 val)
 300 {
 301         switch (size) {
 302         case 1:
 303                 return write_config_byte(bus, devfn, where, (u8) val);
 304         case 2:
 305                 return write_config_word(bus, devfn, where, (u16) val);
 306         default:
 307                 return write_config_dword(bus, devfn, where, val);
 308         }
 309 }
 310
 311
 312 struct pci_ops au1x_pci_ops = {
 313         config_read,
 314         config_write
 315 };