arch/mips/pci/pci-mt7620.c

   1 /*
   2  *  Ralink MT7620A SoC PCI support
   3  *
   4  *  Copyright (C) 2007-2013 Bruce Chang (Mediatek)
   5  *  Copyright (C) 2013-2016 John Crispin <john@phrozen.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License version 2 as published
   9  *  by the Free Software Foundation.
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/pci.h>
  14 #include <linux/io.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/of.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_pci.h>
  21 #include <linux/reset.h>
  22 #include <linux/platform_device.h>
  23
  24 #include <asm/mach-ralink/ralink_regs.h>
  25 #include <asm/mach-ralink/mt7620.h>
  26
  27 #define RALINK_PCI_IO_MAP_BASE          0x10160000
  28 #define RALINK_PCI_MEMORY_BASE          0x0
  29
  30 #define RALINK_INT_PCIE0                4
  31
  32 #define RALINK_CLKCFG1                  0x30
  33 #define RALINK_GPIOMODE                 0x60
  34
  35 #define PPLL_CFG1                       0x9c
  36
  37 #define PPLL_DRV                        0xa0
  38 #define PDRV_SW_SET                     BIT(31)
  39 #define LC_CKDRVPD                      BIT(19)
  40 #define LC_CKDRVOHZ                     BIT(18)
  41 #define LC_CKDRVHZ                      BIT(17)
  42 #define LC_CKTEST                       BIT(16)
  43
  44 /* PCI Bridge registers */
  45 #define RALINK_PCI_PCICFG_ADDR          0x00
  46 #define PCIRST                          BIT(1)
  47
  48 #define RALINK_PCI_PCIENA               0x0C
  49 #define PCIINT2                         BIT(20)
  50
  51 #define RALINK_PCI_CONFIG_ADDR          0x20
  52 #define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
  53 #define RALINK_PCI_MEMBASE              0x28
  54 #define RALINK_PCI_IOBASE               0x2C
  55
  56 /* PCI RC registers */
  57 #define RALINK_PCI0_BAR0SETUP_ADDR      0x10
  58 #define RALINK_PCI0_IMBASEBAR0_ADDR     0x18
  59 #define RALINK_PCI0_ID                  0x30
  60 #define RALINK_PCI0_CLASS               0x34
  61 #define RALINK_PCI0_SUBID               0x38
  62 #define RALINK_PCI0_STATUS              0x50
  63 #define PCIE_LINK_UP_ST                 BIT(0)
  64
  65 #define PCIEPHY0_CFG                    0x90
  66
  67 #define RALINK_PCIEPHY_P0_CTL_OFFSET    0x7498
  68 #define RALINK_PCIE0_CLK_EN             BIT(26)
  69
  70 #define BUSY                            0x80000000
  71 #define WAITRETRY_MAX                   10
  72 #define WRITE_MODE                      (1UL << 23)
  73 #define DATA_SHIFT                      0
  74 #define ADDR_SHIFT                      8
  75
  76
  77 static void __iomem *bridge_base;
  78 static void __iomem *pcie_base;
  79
  80 static struct reset_control *rstpcie0;
  81
  82 static inline void bridge_w32(u32 val, unsigned reg)
  83 {
  84         iowrite32(val, bridge_base + reg);
  85 }
  86
  87 static inline u32 bridge_r32(unsigned reg)
  88 {
  89         return ioread32(bridge_base + reg);
  90 }
  91
  92 static inline void pcie_w32(u32 val, unsigned reg)
  93 {
  94         iowrite32(val, pcie_base + reg);
  95 }
  96
  97 static inline u32 pcie_r32(unsigned reg)
  98 {
  99         return ioread32(pcie_base + reg);
 100 }
 101
 102 static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
 103 {
 104         u32 val = pcie_r32(reg);
 105
 106         val &= ~clr;
 107         val |= set;
 108         pcie_w32(val, reg);
 109 }
 110
 111 static int wait_pciephy_busy(void)
 112 {
 113         unsigned long reg_value = 0x0, retry = 0;
 114
 115         while (1) {
 116                 reg_value = pcie_r32(PCIEPHY0_CFG);
 117
 118                 if (reg_value & BUSY)
 119                         mdelay(100);
 120                 else
 121                         break;
 122                 if (retry++ > WAITRETRY_MAX) {
 123                         pr_warn("PCIE-PHY retry failed.\n");
 124                         return -1;
 125                 }
 126         }
 127         return 0;
 128 }
 129
 130 static void pcie_phy(unsigned long addr, unsigned long val)
 131 {
 132         wait_pciephy_busy();
 133         pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT),
 134                  PCIEPHY0_CFG);
 135         mdelay(1);
 136         wait_pciephy_busy();
 137 }
 138
 139 static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
 140                            int size, u32 *val)
 141 {
 142         unsigned int slot = PCI_SLOT(devfn);
 143         u8 func = PCI_FUNC(devfn);
 144         u32 address;
 145         u32 data;
 146         u32 num = 0;
 147
 148         if (bus)
 149                 num = bus->number;
 150
 151         address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
 152                   (func << 8) | (where & 0xfc) | 0x80000000;
 153         bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
 154         data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
 155
 156         switch (size) {
 157         case 1:
 158                 *val = (data >> ((where & 3) << 3)) & 0xff;
 159                 break;
 160         case 2:
 161                 *val = (data >> ((where & 3) << 3)) & 0xffff;
 162                 break;
 163         case 4:
 164                 *val = data;
 165                 break;
 166         }
 167
 168         return PCIBIOS_SUCCESSFUL;
 169 }
 170
 171 static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
 172                             int size, u32 val)
 173 {
 174         unsigned int slot = PCI_SLOT(devfn);
 175         u8 func = PCI_FUNC(devfn);
 176         u32 address;
 177         u32 data;
 178         u32 num = 0;
 179
 180         if (bus)
 181                 num = bus->number;
 182
 183         address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
 184                   (func << 8) | (where & 0xfc) | 0x80000000;
 185         bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
 186         data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
 187
 188         switch (size) {
 189         case 1:
 190                 data = (data & ~(0xff << ((where & 3) << 3))) |
 191                         (val << ((where & 3) << 3));
 192                 break;
 193         case 2:
 194                 data = (data & ~(0xffff << ((where & 3) << 3))) |
 195                         (val << ((where & 3) << 3));
 196                 break;
 197         case 4:
 198                 data = val;
 199                 break;
 200         }
 201
 202         bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
 203
 204         return PCIBIOS_SUCCESSFUL;
 205 }
 206
 207 struct pci_ops mt7620_pci_ops = {
 208         .read   = pci_config_read,
 209         .write  = pci_config_write,
 210 };
 211
 212 static struct resource mt7620_res_pci_mem1;
 213 static struct resource mt7620_res_pci_io1;
 214 struct pci_controller mt7620_controller = {
 215         .pci_ops        = &mt7620_pci_ops,
 216         .mem_resource   = &mt7620_res_pci_mem1,
 217         .mem_offset     = 0x00000000UL,
 218         .io_resource    = &mt7620_res_pci_io1,
 219         .io_offset      = 0x00000000UL,
 220         .io_map_base    = 0xa0000000,
 221 };
 222
 223 static int mt7620_pci_hw_init(struct platform_device *pdev)
 224 {
 225         /* bypass PCIe DLL */
 226         pcie_phy(0x0, 0x80);
 227         pcie_phy(0x1, 0x04);
 228
 229         /* Elastic buffer control */
 230         pcie_phy(0x68, 0xB4);
 231
 232         /* put core into reset */
 233         pcie_m32(0, PCIRST, RALINK_PCI_PCICFG_ADDR);
 234         reset_control_assert(rstpcie0);
 235
 236         /* disable power and all clocks */
 237         rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 238         rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
 239
 240         /* bring core out of reset */
 241         reset_control_deassert(rstpcie0);
 242         rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
 243         mdelay(100);
 244
 245         if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
 246                 dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
 247                 reset_control_assert(rstpcie0);
 248                 rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 249                 return -1;
 250         }
 251
 252         /* power up the bus */
 253         rt_sysc_m32(LC_CKDRVHZ | LC_CKDRVOHZ, LC_CKDRVPD | PDRV_SW_SET,
 254                     PPLL_DRV);
 255
 256         return 0;
 257 }
 258
 259 static int mt7628_pci_hw_init(struct platform_device *pdev)
 260 {
 261         u32 val = 0;
 262
 263         /* bring the core out of reset */
 264         rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
 265         reset_control_deassert(rstpcie0);
 266
 267         /* enable the pci clk */
 268         rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
 269         mdelay(100);
 270
 271         /* voodoo from the SDK driver */
 272         pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
 273
 274         pci_config_read(NULL, 0, 0x70c, 4, &val);
 275         val &= ~(0xff) << 8;
 276         val |= 0x50 << 8;
 277         pci_config_write(NULL, 0, 0x70c, 4, val);
 278
 279         pci_config_read(NULL, 0, 0x70c, 4, &val);
 280         dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
 281
 282         return 0;
 283 }
 284
 285 static int mt7620_pci_probe(struct platform_device *pdev)
 286 {
 287         struct resource *bridge_res = platform_get_resource(pdev,
 288                                                             IORESOURCE_MEM, 0);
 289         struct resource *pcie_res = platform_get_resource(pdev,
 290                                                           IORESOURCE_MEM, 1);
 291         u32 val = 0;
 292
 293         rstpcie0 = devm_reset_control_get_exclusive(&pdev->dev, "pcie0");
 294         if (IS_ERR(rstpcie0))
 295                 return PTR_ERR(rstpcie0);
 296
 297         bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
 298         if (IS_ERR(bridge_base))
 299                 return PTR_ERR(bridge_base);
 300
 301         pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
 302         if (IS_ERR(pcie_base))
 303                 return PTR_ERR(pcie_base);
 304
 305         iomem_resource.start = 0;
 306         iomem_resource.end = ~0;
 307         ioport_resource.start = 0;
 308         ioport_resource.end = ~0;
 309
 310         /* bring up the pci core */
 311         switch (ralink_soc) {
 312         case MT762X_SOC_MT7620A:
 313                 if (mt7620_pci_hw_init(pdev))
 314                         return -1;
 315                 break;
 316
 317         case MT762X_SOC_MT7628AN:
 318         case MT762X_SOC_MT7688:
 319                 if (mt7628_pci_hw_init(pdev))
 320                         return -1;
 321                 break;
 322
 323         default:
 324                 dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
 325                 return -1;
 326         }
 327         mdelay(50);
 328
 329         /* enable write access */
 330         pcie_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
 331         mdelay(100);
 332
 333         /* check if there is a card present */
 334         if ((pcie_r32(RALINK_PCI0_STATUS) & PCIE_LINK_UP_ST) == 0) {
 335                 reset_control_assert(rstpcie0);
 336                 rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 337                 if (ralink_soc == MT762X_SOC_MT7620A)
 338                         rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
 339                 dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
 340                 return -1;
 341         }
 342
 343         /* setup ranges */
 344         bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
 345         bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
 346
 347         pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
 348         pcie_w32(RALINK_PCI_MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
 349         pcie_w32(0x06040001, RALINK_PCI0_CLASS);
 350
 351         /* enable interrupts */
 352         pcie_m32(0, PCIINT2, RALINK_PCI_PCIENA);
 353
 354         /* voodoo from the SDK driver */
 355         pci_config_read(NULL, 0, 4, 4, &val);
 356         pci_config_write(NULL, 0, 4, 4, val | 0x7);
 357
 358         pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
 359         register_pci_controller(&mt7620_controller);
 360
 361         return 0;
 362 }
 363
 364 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 365 {
 366         u16 cmd;
 367         u32 val;
 368         int irq = 0;
 369
 370         if ((dev->bus->number == 0) && (slot == 0)) {
 371                 pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
 372                 pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,
 373                                  RALINK_PCI_MEMORY_BASE);
 374                 pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
 375         } else if ((dev->bus->number == 1) && (slot == 0x0)) {
 376                 irq = RALINK_INT_PCIE0;
 377         } else {
 378                 dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n",
 379                         dev->bus->number, slot);
 380                 return 0;
 381         }
 382         dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
 383                 dev->bus->number, slot, irq);
 384
 385         /* configure the cache line size to 0x14 */
 386         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
 387
 388         /* configure latency timer to 0xff */
 389         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xff);
 390         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 391
 392         /* setup the slot */
 393         cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 394         pci_write_config_word(dev, PCI_COMMAND, cmd);
 395         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 396
 397         return irq;
 398 }
 399
 400 int pcibios_plat_dev_init(struct pci_dev *dev)
 401 {
 402         return 0;
 403 }
 404
 405 static const struct of_device_id mt7620_pci_ids[] = {
 406         { .compatible = "mediatek,mt7620-pci" },
 407         {},
 408 };
 409
 410 static struct platform_driver mt7620_pci_driver = {
 411         .probe = mt7620_pci_probe,
 412         .driver = {
 413                 .name = "mt7620-pci",
 414                 .of_match_table = of_match_ptr(mt7620_pci_ids),
 415         },
 416 };
 417
 418 static int __init mt7620_pci_init(void)
 419 {
 420         return platform_driver_register(&mt7620_pci_driver);
 421 }
 422
 423 arch_initcall(mt7620_pci_init);