arch/mips/pci/pci-xlp.c

   1 /*
   2  * Copyright (c) 2003-2012 Broadcom Corporation
   3  * All Rights Reserved
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the Broadcom
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/types.h>
  36 #include <linux/pci.h>
  37 #include <linux/kernel.h>
  38 #include <linux/init.h>
  39 #include <linux/msi.h>
  40 #include <linux/mm.h>
  41 #include <linux/irq.h>
  42 #include <linux/irqdesc.h>
  43 #include <linux/console.h>
  44
  45 #include <asm/io.h>
  46
  47 #include <asm/netlogic/interrupt.h>
  48 #include <asm/netlogic/haldefs.h>
  49 #include <asm/netlogic/common.h>
  50 #include <asm/netlogic/mips-extns.h>
  51
  52 #include <asm/netlogic/xlp-hal/iomap.h>
  53 #include <asm/netlogic/xlp-hal/xlp.h>
  54 #include <asm/netlogic/xlp-hal/pic.h>
  55 #include <asm/netlogic/xlp-hal/pcibus.h>
  56 #include <asm/netlogic/xlp-hal/bridge.h>
  57
  58 static void *pci_config_base;
  59
  60 #define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
  61
  62 /* PCI ops */
  63 static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
  64         int where)
  65 {
  66         u32 data;
  67         u32 *cfgaddr;
  68
  69         where &= ~3;
  70         if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954)
  71                 return 0xffffffff;
  72
  73         cfgaddr = (u32 *)(pci_config_base +
  74                         pci_cfg_addr(bus->number, devfn, where));
  75         data = *cfgaddr;
  76         return data;
  77 }
  78
  79 static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
  80         int where, u32 data)
  81 {
  82         u32 *cfgaddr;
  83
  84         cfgaddr = (u32 *)(pci_config_base +
  85                         pci_cfg_addr(bus->number, devfn, where & ~3));
  86         *cfgaddr = data;
  87 }
  88
  89 static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
  90         int where, int size, u32 *val)
  91 {
  92         u32 data;
  93
  94         if ((size == 2) && (where & 1))
  95                 return PCIBIOS_BAD_REGISTER_NUMBER;
  96         else if ((size == 4) && (where & 3))
  97                 return PCIBIOS_BAD_REGISTER_NUMBER;
  98
  99         data = pci_cfg_read_32bit(bus, devfn, where);
 100
 101         if (size == 1)
 102                 *val = (data >> ((where & 3) << 3)) & 0xff;
 103         else if (size == 2)
 104                 *val = (data >> ((where & 3) << 3)) & 0xffff;
 105         else
 106                 *val = data;
 107
 108         return PCIBIOS_SUCCESSFUL;
 109 }
 110
 111
 112 static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
 113                 int where, int size, u32 val)
 114 {
 115         u32 data;
 116
 117         if ((size == 2) && (where & 1))
 118                 return PCIBIOS_BAD_REGISTER_NUMBER;
 119         else if ((size == 4) && (where & 3))
 120                 return PCIBIOS_BAD_REGISTER_NUMBER;
 121
 122         data = pci_cfg_read_32bit(bus, devfn, where);
 123
 124         if (size == 1)
 125                 data = (data & ~(0xff << ((where & 3) << 3))) |
 126                         (val << ((where & 3) << 3));
 127         else if (size == 2)
 128                 data = (data & ~(0xffff << ((where & 3) << 3))) |
 129                         (val << ((where & 3) << 3));
 130         else
 131                 data = val;
 132
 133         pci_cfg_write_32bit(bus, devfn, where, data);
 134
 135         return PCIBIOS_SUCCESSFUL;
 136 }
 137
 138 struct pci_ops nlm_pci_ops = {
 139         .read  = nlm_pcibios_read,
 140         .write = nlm_pcibios_write
 141 };
 142
 143 static struct resource nlm_pci_mem_resource = {
 144         .name           = "XLP PCI MEM",
 145         .start          = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
 146         .end            = 0xdfffffffUL,
 147         .flags          = IORESOURCE_MEM,
 148 };
 149
 150 static struct resource nlm_pci_io_resource = {
 151         .name           = "XLP IO MEM",
 152         .start          = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
 153         .end            = 0x17ffffffUL,
 154         .flags          = IORESOURCE_IO,
 155 };
 156
 157 struct pci_controller nlm_pci_controller = {
 158         .index          = 0,
 159         .pci_ops        = &nlm_pci_ops,
 160         .mem_resource   = &nlm_pci_mem_resource,
 161         .mem_offset     = 0x00000000UL,
 162         .io_resource    = &nlm_pci_io_resource,
 163         .io_offset      = 0x00000000UL,
 164 };
 165
 166 struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev)
 167 {
 168         struct pci_bus *bus, *p;
 169
 170         /* Find the bridge on bus 0 */
 171         bus = dev->bus;
 172         for (p = bus->parent; p && p->number != 0; p = p->parent)
 173                 bus = p;
 174
 175         return p ? bus->self : NULL;
 176 }
 177
 178 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 179 {
 180         struct pci_dev *lnkdev;
 181         int lnkslot, lnkfunc;
 182
 183         /*
 184          * For XLP PCIe, there is an IRQ per Link, find out which
 185          * link the device is on to assign interrupts
 186         */
 187         lnkdev = xlp_get_pcie_link(dev);
 188         if (lnkdev == NULL)
 189                 return 0;
 190         lnkfunc = PCI_FUNC(lnkdev->devfn);
 191         lnkslot = PCI_SLOT(lnkdev->devfn);
 192         return nlm_irq_to_xirq(lnkslot / 8, PIC_PCIE_LINK_LEGACY_IRQ(lnkfunc));
 193 }
 194
 195 /* Do platform specific device initialization at pci_enable_device() time */
 196 int pcibios_plat_dev_init(struct pci_dev *dev)
 197 {
 198         return 0;
 199 }
 200
 201 /*
 202  * If big-endian, enable hardware byteswap on the PCIe bridges.
 203  * This will make both the SoC and PCIe devices behave consistently with
 204  * readl/writel.
 205  */
 206 #ifdef __BIG_ENDIAN
 207 static void xlp_config_pci_bswap(int node, int link)
 208 {
 209         uint64_t nbubase, lnkbase;
 210         u32 reg;
 211
 212         nbubase = nlm_get_bridge_regbase(node);
 213         lnkbase = nlm_get_pcie_base(node, link);
 214
 215         /*
 216          *  Enable byte swap in hardware. Program each link's PCIe SWAP regions
 217          * from the link's address ranges.
 218          */
 219         reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link);
 220         nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg);
 221
 222         reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_LIMIT0 + link);
 223         nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff);
 224
 225         reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link);
 226         nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg);
 227
 228         reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link);
 229         nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
 230 }
 231 #else
 232 /* Swap configuration not needed in little-endian mode */
 233 static inline void xlp_config_pci_bswap(int node, int link) {}
 234 #endif /* __BIG_ENDIAN */
 235
 236 static int __init pcibios_init(void)
 237 {
 238         uint64_t pciebase;
 239         int link, n;
 240         u32 reg;
 241
 242         /* Firmware assigns PCI resources */
 243         pci_set_flags(PCI_PROBE_ONLY);
 244         pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
 245
 246         /* Extend IO port for memory mapped io */
 247         ioport_resource.start =  0;
 248         ioport_resource.end   = ~0;
 249
 250         for (n = 0; n < NLM_NR_NODES; n++) {
 251                 if (!nlm_node_present(n))
 252                         continue;
 253
 254                 for (link = 0; link < PCIE_NLINKS; link++) {
 255                         pciebase = nlm_get_pcie_base(n, link);
 256                         if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
 257                                 continue;
 258                         xlp_config_pci_bswap(n, link);
 259                         xlp_init_node_msi_irqs(n, link);
 260
 261                         /* put in intpin and irq - u-boot does not */
 262                         reg = nlm_read_pci_reg(pciebase, 0xf);
 263                         reg &= ~0x1fu;
 264                         reg |= (1 << 8) | PIC_PCIE_LINK_LEGACY_IRQ(link);
 265                         nlm_write_pci_reg(pciebase, 0xf, reg);
 266                         pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link);
 267                 }
 268         }
 269
 270         set_io_port_base(CKSEG1);
 271         nlm_pci_controller.io_map_base = CKSEG1;
 272
 273         register_pci_controller(&nlm_pci_controller);
 274         pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource,
 275                 &nlm_pci_mem_resource);
 276
 277         return 0;
 278 }
 279 arch_initcall(pcibios_init);