arch/mips/philips/pnx8550/common/time.c

   1 /*
   2  * Copyright 2001, 2002, 2003 MontaVista Software Inc.
   3  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
   4  *
   5  * Common time service routines for MIPS machines. See
   6  * Documents/MIPS/README.txt.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13 #include <linux/types.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/sched.h>
  17 #include <linux/param.h>
  18 #include <linux/time.h>
  19 #include <linux/timer.h>
  20 #include <linux/smp.h>
  21 #include <linux/kernel_stat.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25
  26 #include <asm/bootinfo.h>
  27 #include <asm/cpu.h>
  28 #include <asm/time.h>
  29 #include <asm/hardirq.h>
  30 #include <asm/div64.h>
  31 #include <asm/debug.h>
  32
  33 #include <int.h>
  34 #include <cm.h>
  35
  36 extern unsigned int mips_hpt_frequency;
  37
  38 /*
  39  * pnx8550_time_init() - it does the following things:
  40  *
  41  * 1) board_time_init() -
  42  *      a) (optional) set up RTC routines,
  43  *      b) (optional) calibrate and set the mips_hpt_frequency
  44  *          (only needed if you intended to use fixed_rate_gettimeoffset
  45  *           or use cpu counter as timer interrupt source)
  46  */
  47
  48 void pnx8550_time_init(void)
  49 {
  50         unsigned int             n;
  51         unsigned int             m;
  52         unsigned int             p;
  53         unsigned int             pow2p;
  54
  55         /* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */
  56         /* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1:  FIXME) */
  57
  58         n = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_N_MASK) >> 16;
  59         m = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_M_MASK) >> 8;
  60         p = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_P_MASK) >> 2;
  61         pow2p = (1 << p);
  62
  63         db_assert(m != 0 && pow2p != 0);
  64
  65         /*
  66          * Compute the frequency as in the PNX8550 User Manual 1.0, p.186
  67          * (a.k.a. 8-10).  Divide by HZ for a timer offset that results in
  68          * HZ timer interrupts per second.
  69          */
  70         mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p));
  71 }
  72
  73 void __init plat_timer_setup(struct irqaction *irq)
  74 {
  75         int configPR;
  76
  77         setup_irq(PNX8550_INT_TIMER1, irq);
  78
  79         /* Start timer1 */
  80         configPR = read_c0_config7();
  81         configPR &= ~0x00000008;
  82         write_c0_config7(configPR);
  83
  84         /* Timer 2 stop */
  85         configPR = read_c0_config7();
  86         configPR |= 0x00000010;
  87         write_c0_config7(configPR);
  88
  89         write_c0_count2(0);
  90         write_c0_compare2(0xffffffff);
  91
  92         /* Timer 3 stop */
  93         configPR = read_c0_config7();
  94         configPR |= 0x00000020;
  95         write_c0_config7(configPR);
  96 }