arch/mips/ralink/mt7620.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify it
   3  * under the terms of the GNU General Public License version 2 as published
   4  * by the Free Software Foundation.
   5  *
   6  * Parts of this file are based on Ralink's 2.6.21 BSP
   7  *
   8  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   9  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  10  * Copyright (C) 2013 John Crispin <john@phrozen.org>
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/bug.h>
  16
  17 #include <asm/mipsregs.h>
  18 #include <asm/mach-ralink/ralink_regs.h>
  19 #include <asm/mach-ralink/mt7620.h>
  20 #include <asm/mach-ralink/pinmux.h>
  21
  22 #include "common.h"
  23
  24 /* analog */
  25 #define PMU0_CFG                0x88
  26 #define PMU_SW_SET              BIT(28)
  27 #define A_DCDC_EN               BIT(24)
  28 #define A_SSC_PERI              BIT(19)
  29 #define A_SSC_GEN               BIT(18)
  30 #define A_SSC_M                 0x3
  31 #define A_SSC_S                 16
  32 #define A_DLY_M                 0x7
  33 #define A_DLY_S                 8
  34 #define A_VTUNE_M               0xff
  35
  36 /* digital */
  37 #define PMU1_CFG                0x8C
  38 #define DIG_SW_SEL              BIT(25)
  39
  40 /* clock scaling */
  41 #define CLKCFG_FDIV_MASK        0x1f00
  42 #define CLKCFG_FDIV_USB_VAL     0x0300
  43 #define CLKCFG_FFRAC_MASK       0x001f
  44 #define CLKCFG_FFRAC_USB_VAL    0x0003
  45
  46 /* EFUSE bits */
  47 #define EFUSE_MT7688            0x100000
  48
  49 /* DRAM type bit */
  50 #define DRAM_TYPE_MT7628_MASK   0x1
  51
  52 /* does the board have sdram or ddram */
  53 static int dram_type;
  54
  55 static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 1, 2) };
  56 static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
  57 static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
  58 static struct rt2880_pmx_func mdio_grp[] = {
  59         FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
  60         FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
  61 };
  62 static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
  63 static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
  64 static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
  65 static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
  66 static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
  67 static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
  68 static struct rt2880_pmx_func uartf_grp[] = {
  69         FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
  70         FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
  71         FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
  72         FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
  73         FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
  74         FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
  75         FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
  76 };
  77 static struct rt2880_pmx_func wdt_grp[] = {
  78         FUNC("wdt rst", 0, 17, 1),
  79         FUNC("wdt refclk", 0, 17, 1),
  80         };
  81 static struct rt2880_pmx_func pcie_rst_grp[] = {
  82         FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
  83         FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
  84 };
  85 static struct rt2880_pmx_func nd_sd_grp[] = {
  86         FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
  87         FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
  88 };
  89
  90 static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
  91         GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
  92         GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
  93                 MT7620_GPIO_MODE_UART0_SHIFT),
  94         GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
  95         GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
  96         GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
  97                 MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
  98         GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
  99                 MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT),
 100         GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
 101         GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
 102         GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
 103                 MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
 104         GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
 105                 MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
 106         GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
 107         GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
 108         GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
 109         GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
 110         { 0 }
 111 };
 112
 113 static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
 114         FUNC("sdxc d6", 3, 19, 1),
 115         FUNC("utif", 2, 19, 1),
 116         FUNC("gpio", 1, 19, 1),
 117         FUNC("pwm1", 0, 19, 1),
 118 };
 119
 120 static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
 121         FUNC("sdxc d7", 3, 18, 1),
 122         FUNC("utif", 2, 18, 1),
 123         FUNC("gpio", 1, 18, 1),
 124         FUNC("pwm0", 0, 18, 1),
 125 };
 126
 127 static struct rt2880_pmx_func uart2_grp_mt7628[] = {
 128         FUNC("sdxc d5 d4", 3, 20, 2),
 129         FUNC("pwm", 2, 20, 2),
 130         FUNC("gpio", 1, 20, 2),
 131         FUNC("uart2", 0, 20, 2),
 132 };
 133
 134 static struct rt2880_pmx_func uart1_grp_mt7628[] = {
 135         FUNC("sw_r", 3, 45, 2),
 136         FUNC("pwm", 2, 45, 2),
 137         FUNC("gpio", 1, 45, 2),
 138         FUNC("uart1", 0, 45, 2),
 139 };
 140
 141 static struct rt2880_pmx_func i2c_grp_mt7628[] = {
 142         FUNC("-", 3, 4, 2),
 143         FUNC("debug", 2, 4, 2),
 144         FUNC("gpio", 1, 4, 2),
 145         FUNC("i2c", 0, 4, 2),
 146 };
 147
 148 static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) };
 149 static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) };
 150 static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) };
 151 static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
 152
 153 static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
 154         FUNC("jtag", 3, 22, 8),
 155         FUNC("utif", 2, 22, 8),
 156         FUNC("gpio", 1, 22, 8),
 157         FUNC("sdxc", 0, 22, 8),
 158 };
 159
 160 static struct rt2880_pmx_func uart0_grp_mt7628[] = {
 161         FUNC("-", 3, 12, 2),
 162         FUNC("-", 2, 12, 2),
 163         FUNC("gpio", 1, 12, 2),
 164         FUNC("uart0", 0, 12, 2),
 165 };
 166
 167 static struct rt2880_pmx_func i2s_grp_mt7628[] = {
 168         FUNC("antenna", 3, 0, 4),
 169         FUNC("pcm", 2, 0, 4),
 170         FUNC("gpio", 1, 0, 4),
 171         FUNC("i2s", 0, 0, 4),
 172 };
 173
 174 static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = {
 175         FUNC("-", 3, 6, 1),
 176         FUNC("refclk", 2, 6, 1),
 177         FUNC("gpio", 1, 6, 1),
 178         FUNC("spi cs1", 0, 6, 1),
 179 };
 180
 181 static struct rt2880_pmx_func spis_grp_mt7628[] = {
 182         FUNC("pwm_uart2", 3, 14, 4),
 183         FUNC("utif", 2, 14, 4),
 184         FUNC("gpio", 1, 14, 4),
 185         FUNC("spis", 0, 14, 4),
 186 };
 187
 188 static struct rt2880_pmx_func gpio_grp_mt7628[] = {
 189         FUNC("pcie", 3, 11, 1),
 190         FUNC("refclk", 2, 11, 1),
 191         FUNC("gpio", 1, 11, 1),
 192         FUNC("gpio", 0, 11, 1),
 193 };
 194
 195 static struct rt2880_pmx_func p4led_kn_grp_mt7628[] = {
 196         FUNC("jtag", 3, 30, 1),
 197         FUNC("utif", 2, 30, 1),
 198         FUNC("gpio", 1, 30, 1),
 199         FUNC("p4led_kn", 0, 30, 1),
 200 };
 201
 202 static struct rt2880_pmx_func p3led_kn_grp_mt7628[] = {
 203         FUNC("jtag", 3, 31, 1),
 204         FUNC("utif", 2, 31, 1),
 205         FUNC("gpio", 1, 31, 1),
 206         FUNC("p3led_kn", 0, 31, 1),
 207 };
 208
 209 static struct rt2880_pmx_func p2led_kn_grp_mt7628[] = {
 210         FUNC("jtag", 3, 32, 1),
 211         FUNC("utif", 2, 32, 1),
 212         FUNC("gpio", 1, 32, 1),
 213         FUNC("p2led_kn", 0, 32, 1),
 214 };
 215
 216 static struct rt2880_pmx_func p1led_kn_grp_mt7628[] = {
 217         FUNC("jtag", 3, 33, 1),
 218         FUNC("utif", 2, 33, 1),
 219         FUNC("gpio", 1, 33, 1),
 220         FUNC("p1led_kn", 0, 33, 1),
 221 };
 222
 223 static struct rt2880_pmx_func p0led_kn_grp_mt7628[] = {
 224         FUNC("jtag", 3, 34, 1),
 225         FUNC("rsvd", 2, 34, 1),
 226         FUNC("gpio", 1, 34, 1),
 227         FUNC("p0led_kn", 0, 34, 1),
 228 };
 229
 230 static struct rt2880_pmx_func wled_kn_grp_mt7628[] = {
 231         FUNC("rsvd", 3, 35, 1),
 232         FUNC("rsvd", 2, 35, 1),
 233         FUNC("gpio", 1, 35, 1),
 234         FUNC("wled_kn", 0, 35, 1),
 235 };
 236
 237 static struct rt2880_pmx_func p4led_an_grp_mt7628[] = {
 238         FUNC("jtag", 3, 39, 1),
 239         FUNC("utif", 2, 39, 1),
 240         FUNC("gpio", 1, 39, 1),
 241         FUNC("p4led_an", 0, 39, 1),
 242 };
 243
 244 static struct rt2880_pmx_func p3led_an_grp_mt7628[] = {
 245         FUNC("jtag", 3, 40, 1),
 246         FUNC("utif", 2, 40, 1),
 247         FUNC("gpio", 1, 40, 1),
 248         FUNC("p3led_an", 0, 40, 1),
 249 };
 250
 251 static struct rt2880_pmx_func p2led_an_grp_mt7628[] = {
 252         FUNC("jtag", 3, 41, 1),
 253         FUNC("utif", 2, 41, 1),
 254         FUNC("gpio", 1, 41, 1),
 255         FUNC("p2led_an", 0, 41, 1),
 256 };
 257
 258 static struct rt2880_pmx_func p1led_an_grp_mt7628[] = {
 259         FUNC("jtag", 3, 42, 1),
 260         FUNC("utif", 2, 42, 1),
 261         FUNC("gpio", 1, 42, 1),
 262         FUNC("p1led_an", 0, 42, 1),
 263 };
 264
 265 static struct rt2880_pmx_func p0led_an_grp_mt7628[] = {
 266         FUNC("jtag", 3, 43, 1),
 267         FUNC("rsvd", 2, 43, 1),
 268         FUNC("gpio", 1, 43, 1),
 269         FUNC("p0led_an", 0, 43, 1),
 270 };
 271
 272 static struct rt2880_pmx_func wled_an_grp_mt7628[] = {
 273         FUNC("rsvd", 3, 44, 1),
 274         FUNC("rsvd", 2, 44, 1),
 275         FUNC("gpio", 1, 44, 1),
 276         FUNC("wled_an", 0, 44, 1),
 277 };
 278
 279 #define MT7628_GPIO_MODE_MASK           0x3
 280
 281 #define MT7628_GPIO_MODE_P4LED_KN       58
 282 #define MT7628_GPIO_MODE_P3LED_KN       56
 283 #define MT7628_GPIO_MODE_P2LED_KN       54
 284 #define MT7628_GPIO_MODE_P1LED_KN       52
 285 #define MT7628_GPIO_MODE_P0LED_KN       50
 286 #define MT7628_GPIO_MODE_WLED_KN        48
 287 #define MT7628_GPIO_MODE_P4LED_AN       42
 288 #define MT7628_GPIO_MODE_P3LED_AN       40
 289 #define MT7628_GPIO_MODE_P2LED_AN       38
 290 #define MT7628_GPIO_MODE_P1LED_AN       36
 291 #define MT7628_GPIO_MODE_P0LED_AN       34
 292 #define MT7628_GPIO_MODE_WLED_AN        32
 293 #define MT7628_GPIO_MODE_PWM1           30
 294 #define MT7628_GPIO_MODE_PWM0           28
 295 #define MT7628_GPIO_MODE_UART2          26
 296 #define MT7628_GPIO_MODE_UART1          24
 297 #define MT7628_GPIO_MODE_I2C            20
 298 #define MT7628_GPIO_MODE_REFCLK         18
 299 #define MT7628_GPIO_MODE_PERST          16
 300 #define MT7628_GPIO_MODE_WDT            14
 301 #define MT7628_GPIO_MODE_SPI            12
 302 #define MT7628_GPIO_MODE_SDMODE         10
 303 #define MT7628_GPIO_MODE_UART0          8
 304 #define MT7628_GPIO_MODE_I2S            6
 305 #define MT7628_GPIO_MODE_CS1            4
 306 #define MT7628_GPIO_MODE_SPIS           2
 307 #define MT7628_GPIO_MODE_GPIO           0
 308
 309 static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
 310         GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
 311                                 1, MT7628_GPIO_MODE_PWM1),
 312         GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
 313                                 1, MT7628_GPIO_MODE_PWM0),
 314         GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK,
 315                                 1, MT7628_GPIO_MODE_UART2),
 316         GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK,
 317                                 1, MT7628_GPIO_MODE_UART1),
 318         GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK,
 319                                 1, MT7628_GPIO_MODE_I2C),
 320         GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK),
 321         GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST),
 322         GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT),
 323         GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI),
 324         GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK,
 325                                 1, MT7628_GPIO_MODE_SDMODE),
 326         GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK,
 327                                 1, MT7628_GPIO_MODE_UART0),
 328         GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK,
 329                                 1, MT7628_GPIO_MODE_I2S),
 330         GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK,
 331                                 1, MT7628_GPIO_MODE_CS1),
 332         GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK,
 333                                 1, MT7628_GPIO_MODE_SPIS),
 334         GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK,
 335                                 1, MT7628_GPIO_MODE_GPIO),
 336         GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
 337                                 1, MT7628_GPIO_MODE_WLED_AN),
 338         GRP_G("p0led_an", p0led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
 339                                 1, MT7628_GPIO_MODE_P0LED_AN),
 340         GRP_G("p1led_an", p1led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
 341                                 1, MT7628_GPIO_MODE_P1LED_AN),
 342         GRP_G("p2led_an", p2led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
 343                                 1, MT7628_GPIO_MODE_P2LED_AN),
 344         GRP_G("p3led_an", p3led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
 345                                 1, MT7628_GPIO_MODE_P3LED_AN),
 346         GRP_G("p4led_an", p4led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
 347                                 1, MT7628_GPIO_MODE_P4LED_AN),
 348         GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
 349                                 1, MT7628_GPIO_MODE_WLED_KN),
 350         GRP_G("p0led_kn", p0led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
 351                                 1, MT7628_GPIO_MODE_P0LED_KN),
 352         GRP_G("p1led_kn", p1led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
 353                                 1, MT7628_GPIO_MODE_P1LED_KN),
 354         GRP_G("p2led_kn", p2led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
 355                                 1, MT7628_GPIO_MODE_P2LED_KN),
 356         GRP_G("p3led_kn", p3led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
 357                                 1, MT7628_GPIO_MODE_P3LED_KN),
 358         GRP_G("p4led_kn", p4led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
 359                                 1, MT7628_GPIO_MODE_P4LED_KN),
 360         { 0 }
 361 };
 362
 363 static inline int is_mt76x8(void)
 364 {
 365         return ralink_soc == MT762X_SOC_MT7628AN ||
 366                ralink_soc == MT762X_SOC_MT7688;
 367 }
 368
 369 static __init u32
 370 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
 371 {
 372         u64 t;
 373
 374         t = ref_rate;
 375         t *= mul;
 376         do_div(t, div);
 377
 378         return t;
 379 }
 380
 381 #define MHZ(x)          ((x) * 1000 * 1000)
 382
 383 static __init unsigned long
 384 mt7620_get_xtal_rate(void)
 385 {
 386         u32 reg;
 387
 388         reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
 389         if (reg & SYSCFG0_XTAL_FREQ_SEL)
 390                 return MHZ(40);
 391
 392         return MHZ(20);
 393 }
 394
 395 static __init unsigned long
 396 mt7620_get_periph_rate(unsigned long xtal_rate)
 397 {
 398         u32 reg;
 399
 400         reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
 401         if (reg & CLKCFG0_PERI_CLK_SEL)
 402                 return xtal_rate;
 403
 404         return MHZ(40);
 405 }
 406
 407 static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
 408
 409 static __init unsigned long
 410 mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
 411 {
 412         u32 reg;
 413         u32 mul;
 414         u32 div;
 415
 416         reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
 417         if (reg & CPLL_CFG0_BYPASS_REF_CLK)
 418                 return xtal_rate;
 419
 420         if ((reg & CPLL_CFG0_SW_CFG) == 0)
 421                 return MHZ(600);
 422
 423         mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
 424               CPLL_CFG0_PLL_MULT_RATIO_MASK;
 425         mul += 24;
 426         if (reg & CPLL_CFG0_LC_CURFCK)
 427                 mul *= 2;
 428
 429         div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
 430               CPLL_CFG0_PLL_DIV_RATIO_MASK;
 431
 432         WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
 433
 434         return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
 435 }
 436
 437 static __init unsigned long
 438 mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
 439 {
 440         u32 reg;
 441
 442         reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
 443         if (reg & CPLL_CFG1_CPU_AUX1)
 444                 return xtal_rate;
 445
 446         if (reg & CPLL_CFG1_CPU_AUX0)
 447                 return MHZ(480);
 448
 449         return cpu_pll_rate;
 450 }
 451
 452 static __init unsigned long
 453 mt7620_get_cpu_rate(unsigned long pll_rate)
 454 {
 455         u32 reg;
 456         u32 mul;
 457         u32 div;
 458
 459         reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
 460
 461         mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
 462         div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
 463               CPU_SYS_CLKCFG_CPU_FDIV_MASK;
 464
 465         return mt7620_calc_rate(pll_rate, mul, div);
 466 }
 467
 468 static const u32 mt7620_ocp_dividers[16] __initconst = {
 469         [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
 470         [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
 471         [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
 472         [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
 473         [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
 474 };
 475
 476 static __init unsigned long
 477 mt7620_get_dram_rate(unsigned long pll_rate)
 478 {
 479         if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
 480                 return pll_rate / 4;
 481
 482         return pll_rate / 3;
 483 }
 484
 485 static __init unsigned long
 486 mt7620_get_sys_rate(unsigned long cpu_rate)
 487 {
 488         u32 reg;
 489         u32 ocp_ratio;
 490         u32 div;
 491
 492         reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
 493
 494         ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
 495                     CPU_SYS_CLKCFG_OCP_RATIO_MASK;
 496
 497         if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
 498                 return cpu_rate;
 499
 500         div = mt7620_ocp_dividers[ocp_ratio];
 501         if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
 502                 return cpu_rate;
 503
 504         return cpu_rate / div;
 505 }
 506
 507 void __init ralink_clk_init(void)
 508 {
 509         unsigned long xtal_rate;
 510         unsigned long cpu_pll_rate;
 511         unsigned long pll_rate;
 512         unsigned long cpu_rate;
 513         unsigned long sys_rate;
 514         unsigned long dram_rate;
 515         unsigned long periph_rate;
 516         unsigned long pcmi2s_rate;
 517
 518         xtal_rate = mt7620_get_xtal_rate();
 519
 520 #define RFMT(label)     label ":%lu.%03luMHz "
 521 #define RINT(x)         ((x) / 1000000)
 522 #define RFRAC(x)        (((x) / 1000) % 1000)
 523
 524         if (is_mt76x8()) {
 525                 if (xtal_rate == MHZ(40))
 526                         cpu_rate = MHZ(580);
 527                 else
 528                         cpu_rate = MHZ(575);
 529                 dram_rate = sys_rate = cpu_rate / 3;
 530                 periph_rate = MHZ(40);
 531                 pcmi2s_rate = MHZ(480);
 532
 533                 ralink_clk_add("10000d00.uartlite", periph_rate);
 534                 ralink_clk_add("10000e00.uartlite", periph_rate);
 535         } else {
 536                 cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
 537                 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
 538
 539                 cpu_rate = mt7620_get_cpu_rate(pll_rate);
 540                 dram_rate = mt7620_get_dram_rate(pll_rate);
 541                 sys_rate = mt7620_get_sys_rate(cpu_rate);
 542                 periph_rate = mt7620_get_periph_rate(xtal_rate);
 543                 pcmi2s_rate = periph_rate;
 544
 545                 pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
 546                          RINT(xtal_rate), RFRAC(xtal_rate),
 547                          RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
 548                          RINT(pll_rate), RFRAC(pll_rate));
 549
 550                 ralink_clk_add("10000500.uart", periph_rate);
 551         }
 552
 553         pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
 554                  RINT(cpu_rate), RFRAC(cpu_rate),
 555                  RINT(dram_rate), RFRAC(dram_rate),
 556                  RINT(sys_rate), RFRAC(sys_rate),
 557                  RINT(periph_rate), RFRAC(periph_rate));
 558 #undef RFRAC
 559 #undef RINT
 560 #undef RFMT
 561
 562         ralink_clk_add("cpu", cpu_rate);
 563         ralink_clk_add("10000100.timer", periph_rate);
 564         ralink_clk_add("10000120.watchdog", periph_rate);
 565         ralink_clk_add("10000900.i2c", periph_rate);
 566         ralink_clk_add("10000a00.i2s", pcmi2s_rate);
 567         ralink_clk_add("10000b00.spi", sys_rate);
 568         ralink_clk_add("10000b40.spi", sys_rate);
 569         ralink_clk_add("10000c00.uartlite", periph_rate);
 570         ralink_clk_add("10000d00.uart1", periph_rate);
 571         ralink_clk_add("10000e00.uart2", periph_rate);
 572         ralink_clk_add("10180000.wmac", xtal_rate);
 573
 574         if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
 575                 /*
 576                  * When the CPU goes into sleep mode, the BUS clock will be
 577                  * too low for USB to function properly. Adjust the busses
 578                  * fractional divider to fix this
 579                  */
 580                 u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
 581
 582                 val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
 583                 val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
 584
 585                 rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
 586         }
 587 }
 588
 589 void __init ralink_of_remap(void)
 590 {
 591         rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
 592         rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
 593
 594         if (!rt_sysc_membase || !rt_memc_membase)
 595                 panic("Failed to remap core resources");
 596 }
 597
 598 static __init void
 599 mt7620_dram_init(struct ralink_soc_info *soc_info)
 600 {
 601         switch (dram_type) {
 602         case SYSCFG0_DRAM_TYPE_SDRAM:
 603                 pr_info("Board has SDRAM\n");
 604                 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
 605                 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
 606                 break;
 607
 608         case SYSCFG0_DRAM_TYPE_DDR1:
 609                 pr_info("Board has DDR1\n");
 610                 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
 611                 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
 612                 break;
 613
 614         case SYSCFG0_DRAM_TYPE_DDR2:
 615                 pr_info("Board has DDR2\n");
 616                 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
 617                 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
 618                 break;
 619         default:
 620                 BUG();
 621         }
 622 }
 623
 624 static __init void
 625 mt7628_dram_init(struct ralink_soc_info *soc_info)
 626 {
 627         switch (dram_type) {
 628         case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
 629                 pr_info("Board has DDR1\n");
 630                 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
 631                 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
 632                 break;
 633
 634         case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
 635                 pr_info("Board has DDR2\n");
 636                 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
 637                 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
 638                 break;
 639         default:
 640                 BUG();
 641         }
 642 }
 643
 644 void prom_soc_init(struct ralink_soc_info *soc_info)
 645 {
 646         void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
 647         unsigned char *name = NULL;
 648         u32 n0;
 649         u32 n1;
 650         u32 rev;
 651         u32 cfg0;
 652         u32 pmu0;
 653         u32 pmu1;
 654         u32 bga;
 655
 656         n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 657         n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 658         rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
 659         bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
 660
 661         if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
 662                 if (bga) {
 663                         ralink_soc = MT762X_SOC_MT7620A;
 664                         name = "MT7620A";
 665                         soc_info->compatible = "ralink,mt7620a-soc";
 666                 } else {
 667                         ralink_soc = MT762X_SOC_MT7620N;
 668                         name = "MT7620N";
 669                         soc_info->compatible = "ralink,mt7620n-soc";
 670                 }
 671         } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
 672                 u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
 673
 674                 if (efuse & EFUSE_MT7688) {
 675                         ralink_soc = MT762X_SOC_MT7688;
 676                         name = "MT7688";
 677                 } else {
 678                         ralink_soc = MT762X_SOC_MT7628AN;
 679                         name = "MT7628AN";
 680                 }
 681                 soc_info->compatible = "ralink,mt7628an-soc";
 682         } else {
 683                 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
 684         }
 685
 686         snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 687                 "MediaTek %s ver:%u eco:%u",
 688                 name,
 689                 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
 690                 (rev & CHIP_REV_ECO_MASK));
 691
 692         cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
 693         if (is_mt76x8()) {
 694                 dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;
 695         } else {
 696                 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) &
 697                             SYSCFG0_DRAM_TYPE_MASK;
 698                 if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN)
 699                         dram_type = SYSCFG0_DRAM_TYPE_SDRAM;
 700         }
 701
 702         soc_info->mem_base = MT7620_DRAM_BASE;
 703         if (is_mt76x8())
 704                 mt7628_dram_init(soc_info);
 705         else
 706                 mt7620_dram_init(soc_info);
 707
 708         pmu0 = __raw_readl(sysc + PMU0_CFG);
 709         pmu1 = __raw_readl(sysc + PMU1_CFG);
 710
 711         pr_info("Analog PMU set to %s control\n",
 712                 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
 713         pr_info("Digital PMU set to %s control\n",
 714                 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
 715
 716         if (is_mt76x8())
 717                 rt2880_pinmux_data = mt7628an_pinmux_data;
 718         else
 719                 rt2880_pinmux_data = mt7620a_pinmux_data;
 720 }