arch/mips/ralink/mt7620.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify it
   3  * under the terms of the GNU General Public License version 2 as published
   4  * by the Free Software Foundation.
   5  *
   6  * Parts of this file are based on Ralink's 2.6.21 BSP
   7  *
   8  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   9  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  10  * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16
  17 #include <asm/mipsregs.h>
  18 #include <asm/mach-ralink/ralink_regs.h>
  19 #include <asm/mach-ralink/mt7620.h>
  20 #include <asm/mach-ralink/pinmux.h>
  21
  22 #include "common.h"
  23
  24 /* analog */
  25 #define PMU0_CFG                0x88
  26 #define PMU_SW_SET              BIT(28)
  27 #define A_DCDC_EN               BIT(24)
  28 #define A_SSC_PERI              BIT(19)
  29 #define A_SSC_GEN               BIT(18)
  30 #define A_SSC_M                 0x3
  31 #define A_SSC_S                 16
  32 #define A_DLY_M                 0x7
  33 #define A_DLY_S                 8
  34 #define A_VTUNE_M               0xff
  35
  36 /* digital */
  37 #define PMU1_CFG                0x8C
  38 #define DIG_SW_SEL              BIT(25)
  39
  40 /* clock scaling */
  41 #define CLKCFG_FDIV_MASK        0x1f00
  42 #define CLKCFG_FDIV_USB_VAL     0x0300
  43 #define CLKCFG_FFRAC_MASK       0x001f
  44 #define CLKCFG_FFRAC_USB_VAL    0x0003
  45
  46 /* EFUSE bits */
  47 #define EFUSE_MT7688            0x100000
  48
  49 /* DRAM type bit */
  50 #define DRAM_TYPE_MT7628_MASK   0x1
  51
  52 /* does the board have sdram or ddram */
  53 static int dram_type;
  54
  55 static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 1, 2) };
  56 static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
  57 static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
  58 static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
  59 static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
  60 static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
  61 static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
  62 static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
  63 static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
  64 static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
  65 static struct rt2880_pmx_func uartf_grp[] = {
  66         FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
  67         FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
  68         FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
  69         FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
  70         FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
  71         FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
  72         FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
  73 };
  74 static struct rt2880_pmx_func wdt_grp[] = {
  75         FUNC("wdt rst", 0, 17, 1),
  76         FUNC("wdt refclk", 0, 17, 1),
  77         };
  78 static struct rt2880_pmx_func pcie_rst_grp[] = {
  79         FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
  80         FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
  81 };
  82 static struct rt2880_pmx_func nd_sd_grp[] = {
  83         FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
  84         FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
  85 };
  86
  87 static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
  88         GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
  89         GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
  90                 MT7620_GPIO_MODE_UART0_SHIFT),
  91         GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
  92         GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
  93         GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
  94                 MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
  95         GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
  96         GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
  97         GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
  98         GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
  99                 MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
 100         GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
 101                 MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
 102         GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
 103         GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
 104         GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
 105         GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
 106         { 0 }
 107 };
 108
 109 static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
 110         FUNC("sdcx", 3, 19, 1),
 111         FUNC("utif", 2, 19, 1),
 112         FUNC("gpio", 1, 19, 1),
 113         FUNC("pwm", 0, 19, 1),
 114 };
 115
 116 static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
 117         FUNC("sdcx", 3, 18, 1),
 118         FUNC("utif", 2, 18, 1),
 119         FUNC("gpio", 1, 18, 1),
 120         FUNC("pwm", 0, 18, 1),
 121 };
 122
 123 static struct rt2880_pmx_func uart2_grp_mt7628[] = {
 124         FUNC("sdcx", 3, 20, 2),
 125         FUNC("pwm", 2, 20, 2),
 126         FUNC("gpio", 1, 20, 2),
 127         FUNC("uart", 0, 20, 2),
 128 };
 129
 130 static struct rt2880_pmx_func uart1_grp_mt7628[] = {
 131         FUNC("sdcx", 3, 45, 2),
 132         FUNC("pwm", 2, 45, 2),
 133         FUNC("gpio", 1, 45, 2),
 134         FUNC("uart", 0, 45, 2),
 135 };
 136
 137 static struct rt2880_pmx_func i2c_grp_mt7628[] = {
 138         FUNC("-", 3, 4, 2),
 139         FUNC("debug", 2, 4, 2),
 140         FUNC("gpio", 1, 4, 2),
 141         FUNC("i2c", 0, 4, 2),
 142 };
 143
 144 static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) };
 145 static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) };
 146 static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 15, 38) };
 147 static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
 148
 149 static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
 150         FUNC("jtag", 3, 22, 8),
 151         FUNC("utif", 2, 22, 8),
 152         FUNC("gpio", 1, 22, 8),
 153         FUNC("sdcx", 0, 22, 8),
 154 };
 155
 156 static struct rt2880_pmx_func uart0_grp_mt7628[] = {
 157         FUNC("-", 3, 12, 2),
 158         FUNC("-", 2, 12, 2),
 159         FUNC("gpio", 1, 12, 2),
 160         FUNC("uart", 0, 12, 2),
 161 };
 162
 163 static struct rt2880_pmx_func i2s_grp_mt7628[] = {
 164         FUNC("antenna", 3, 0, 4),
 165         FUNC("pcm", 2, 0, 4),
 166         FUNC("gpio", 1, 0, 4),
 167         FUNC("i2s", 0, 0, 4),
 168 };
 169
 170 static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = {
 171         FUNC("-", 3, 6, 1),
 172         FUNC("refclk", 2, 6, 1),
 173         FUNC("gpio", 1, 6, 1),
 174         FUNC("spi", 0, 6, 1),
 175 };
 176
 177 static struct rt2880_pmx_func spis_grp_mt7628[] = {
 178         FUNC("pwm", 3, 14, 4),
 179         FUNC("util", 2, 14, 4),
 180         FUNC("gpio", 1, 14, 4),
 181         FUNC("spis", 0, 14, 4),
 182 };
 183
 184 static struct rt2880_pmx_func gpio_grp_mt7628[] = {
 185         FUNC("pcie", 3, 11, 1),
 186         FUNC("refclk", 2, 11, 1),
 187         FUNC("gpio", 1, 11, 1),
 188         FUNC("gpio", 0, 11, 1),
 189 };
 190
 191 #define MT7628_GPIO_MODE_MASK   0x3
 192
 193 #define MT7628_GPIO_MODE_PWM1   30
 194 #define MT7628_GPIO_MODE_PWM0   28
 195 #define MT7628_GPIO_MODE_UART2  26
 196 #define MT7628_GPIO_MODE_UART1  24
 197 #define MT7628_GPIO_MODE_I2C    20
 198 #define MT7628_GPIO_MODE_REFCLK 18
 199 #define MT7628_GPIO_MODE_PERST  16
 200 #define MT7628_GPIO_MODE_WDT    14
 201 #define MT7628_GPIO_MODE_SPI    12
 202 #define MT7628_GPIO_MODE_SDMODE 10
 203 #define MT7628_GPIO_MODE_UART0  8
 204 #define MT7628_GPIO_MODE_I2S    6
 205 #define MT7628_GPIO_MODE_CS1    4
 206 #define MT7628_GPIO_MODE_SPIS   2
 207 #define MT7628_GPIO_MODE_GPIO   0
 208
 209 static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
 210         GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
 211                                 1, MT7628_GPIO_MODE_PWM1),
 212         GRP_G("pmw1", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
 213                                 1, MT7628_GPIO_MODE_PWM0),
 214         GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK,
 215                                 1, MT7628_GPIO_MODE_UART2),
 216         GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK,
 217                                 1, MT7628_GPIO_MODE_UART1),
 218         GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK,
 219                                 1, MT7628_GPIO_MODE_I2C),
 220         GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK),
 221         GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST),
 222         GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT),
 223         GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI),
 224         GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK,
 225                                 1, MT7628_GPIO_MODE_SDMODE),
 226         GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK,
 227                                 1, MT7628_GPIO_MODE_UART0),
 228         GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK,
 229                                 1, MT7628_GPIO_MODE_I2S),
 230         GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK,
 231                                 1, MT7628_GPIO_MODE_CS1),
 232         GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK,
 233                                 1, MT7628_GPIO_MODE_SPIS),
 234         GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK,
 235                                 1, MT7628_GPIO_MODE_GPIO),
 236         { 0 }
 237 };
 238
 239 static inline int is_mt76x8(void)
 240 {
 241         return ralink_soc == MT762X_SOC_MT7628AN ||
 242                ralink_soc == MT762X_SOC_MT7688;
 243 }
 244
 245 static __init u32
 246 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
 247 {
 248         u64 t;
 249
 250         t = ref_rate;
 251         t *= mul;
 252         do_div(t, div);
 253
 254         return t;
 255 }
 256
 257 #define MHZ(x)          ((x) * 1000 * 1000)
 258
 259 static __init unsigned long
 260 mt7620_get_xtal_rate(void)
 261 {
 262         u32 reg;
 263
 264         reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
 265         if (reg & SYSCFG0_XTAL_FREQ_SEL)
 266                 return MHZ(40);
 267
 268         return MHZ(20);
 269 }
 270
 271 static __init unsigned long
 272 mt7620_get_periph_rate(unsigned long xtal_rate)
 273 {
 274         u32 reg;
 275
 276         reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
 277         if (reg & CLKCFG0_PERI_CLK_SEL)
 278                 return xtal_rate;
 279
 280         return MHZ(40);
 281 }
 282
 283 static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
 284
 285 static __init unsigned long
 286 mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
 287 {
 288         u32 reg;
 289         u32 mul;
 290         u32 div;
 291
 292         reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
 293         if (reg & CPLL_CFG0_BYPASS_REF_CLK)
 294                 return xtal_rate;
 295
 296         if ((reg & CPLL_CFG0_SW_CFG) == 0)
 297                 return MHZ(600);
 298
 299         mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
 300               CPLL_CFG0_PLL_MULT_RATIO_MASK;
 301         mul += 24;
 302         if (reg & CPLL_CFG0_LC_CURFCK)
 303                 mul *= 2;
 304
 305         div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
 306               CPLL_CFG0_PLL_DIV_RATIO_MASK;
 307
 308         WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
 309
 310         return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
 311 }
 312
 313 static __init unsigned long
 314 mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
 315 {
 316         u32 reg;
 317
 318         reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
 319         if (reg & CPLL_CFG1_CPU_AUX1)
 320                 return xtal_rate;
 321
 322         if (reg & CPLL_CFG1_CPU_AUX0)
 323                 return MHZ(480);
 324
 325         return cpu_pll_rate;
 326 }
 327
 328 static __init unsigned long
 329 mt7620_get_cpu_rate(unsigned long pll_rate)
 330 {
 331         u32 reg;
 332         u32 mul;
 333         u32 div;
 334
 335         reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
 336
 337         mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
 338         div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
 339               CPU_SYS_CLKCFG_CPU_FDIV_MASK;
 340
 341         return mt7620_calc_rate(pll_rate, mul, div);
 342 }
 343
 344 static const u32 mt7620_ocp_dividers[16] __initconst = {
 345         [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
 346         [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
 347         [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
 348         [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
 349         [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
 350 };
 351
 352 static __init unsigned long
 353 mt7620_get_dram_rate(unsigned long pll_rate)
 354 {
 355         if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
 356                 return pll_rate / 4;
 357
 358         return pll_rate / 3;
 359 }
 360
 361 static __init unsigned long
 362 mt7620_get_sys_rate(unsigned long cpu_rate)
 363 {
 364         u32 reg;
 365         u32 ocp_ratio;
 366         u32 div;
 367
 368         reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
 369
 370         ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
 371                     CPU_SYS_CLKCFG_OCP_RATIO_MASK;
 372
 373         if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
 374                 return cpu_rate;
 375
 376         div = mt7620_ocp_dividers[ocp_ratio];
 377         if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
 378                 return cpu_rate;
 379
 380         return cpu_rate / div;
 381 }
 382
 383 void __init ralink_clk_init(void)
 384 {
 385         unsigned long xtal_rate;
 386         unsigned long cpu_pll_rate;
 387         unsigned long pll_rate;
 388         unsigned long cpu_rate;
 389         unsigned long sys_rate;
 390         unsigned long dram_rate;
 391         unsigned long periph_rate;
 392
 393         xtal_rate = mt7620_get_xtal_rate();
 394
 395 #define RFMT(label)     label ":%lu.%03luMHz "
 396 #define RINT(x)         ((x) / 1000000)
 397 #define RFRAC(x)        (((x) / 1000) % 1000)
 398
 399         if (is_mt76x8()) {
 400                 if (xtal_rate == MHZ(40))
 401                         cpu_rate = MHZ(580);
 402                 else
 403                         cpu_rate = MHZ(575);
 404                 dram_rate = sys_rate = cpu_rate / 3;
 405                 periph_rate = MHZ(40);
 406
 407                 ralink_clk_add("10000d00.uartlite", periph_rate);
 408                 ralink_clk_add("10000e00.uartlite", periph_rate);
 409         } else {
 410                 cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
 411                 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
 412
 413                 cpu_rate = mt7620_get_cpu_rate(pll_rate);
 414                 dram_rate = mt7620_get_dram_rate(pll_rate);
 415                 sys_rate = mt7620_get_sys_rate(cpu_rate);
 416                 periph_rate = mt7620_get_periph_rate(xtal_rate);
 417
 418                 pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
 419                          RINT(xtal_rate), RFRAC(xtal_rate),
 420                          RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
 421                          RINT(pll_rate), RFRAC(pll_rate));
 422
 423                 ralink_clk_add("10000500.uart", periph_rate);
 424         }
 425
 426         pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
 427                  RINT(cpu_rate), RFRAC(cpu_rate),
 428                  RINT(dram_rate), RFRAC(dram_rate),
 429                  RINT(sys_rate), RFRAC(sys_rate),
 430                  RINT(periph_rate), RFRAC(periph_rate));
 431 #undef RFRAC
 432 #undef RINT
 433 #undef RFMT
 434
 435         ralink_clk_add("cpu", cpu_rate);
 436         ralink_clk_add("10000100.timer", periph_rate);
 437         ralink_clk_add("10000120.watchdog", periph_rate);
 438         ralink_clk_add("10000b00.spi", sys_rate);
 439         ralink_clk_add("10000c00.uartlite", periph_rate);
 440         ralink_clk_add("10180000.wmac", xtal_rate);
 441
 442         if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {
 443                 /*
 444                  * When the CPU goes into sleep mode, the BUS clock will be
 445                  * too low for USB to function properly. Adjust the busses
 446                  * fractional divider to fix this
 447                  */
 448                 u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
 449
 450                 val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
 451                 val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
 452
 453                 rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
 454         }
 455 }
 456
 457 void __init ralink_of_remap(void)
 458 {
 459         rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
 460         rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
 461
 462         if (!rt_sysc_membase || !rt_memc_membase)
 463                 panic("Failed to remap core resources");
 464 }
 465
 466 static __init void
 467 mt7620_dram_init(struct ralink_soc_info *soc_info)
 468 {
 469         switch (dram_type) {
 470         case SYSCFG0_DRAM_TYPE_SDRAM:
 471                 pr_info("Board has SDRAM\n");
 472                 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
 473                 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
 474                 break;
 475
 476         case SYSCFG0_DRAM_TYPE_DDR1:
 477                 pr_info("Board has DDR1\n");
 478                 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
 479                 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
 480                 break;
 481
 482         case SYSCFG0_DRAM_TYPE_DDR2:
 483                 pr_info("Board has DDR2\n");
 484                 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
 485                 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
 486                 break;
 487         default:
 488                 BUG();
 489         }
 490 }
 491
 492 static __init void
 493 mt7628_dram_init(struct ralink_soc_info *soc_info)
 494 {
 495         switch (dram_type) {
 496         case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
 497                 pr_info("Board has DDR1\n");
 498                 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
 499                 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
 500                 break;
 501
 502         case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
 503                 pr_info("Board has DDR2\n");
 504                 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
 505                 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
 506                 break;
 507         default:
 508                 BUG();
 509         }
 510 }
 511
 512 void prom_soc_init(struct ralink_soc_info *soc_info)
 513 {
 514         void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
 515         unsigned char *name = NULL;
 516         u32 n0;
 517         u32 n1;
 518         u32 rev;
 519         u32 cfg0;
 520         u32 pmu0;
 521         u32 pmu1;
 522         u32 bga;
 523
 524         n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 525         n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 526         rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
 527         bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
 528
 529         if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
 530                 if (bga) {
 531                         ralink_soc = MT762X_SOC_MT7620A;
 532                         name = "MT7620A";
 533                         soc_info->compatible = "ralink,mt7620a-soc";
 534                 } else {
 535                         ralink_soc = MT762X_SOC_MT7620N;
 536                         name = "MT7620N";
 537                         soc_info->compatible = "ralink,mt7620n-soc";
 538                 }
 539         } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
 540                 u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
 541
 542                 if (efuse & EFUSE_MT7688) {
 543                         ralink_soc = MT762X_SOC_MT7688;
 544                         name = "MT7688";
 545                 } else {
 546                         ralink_soc = MT762X_SOC_MT7628AN;
 547                         name = "MT7628AN";
 548                 }
 549                 soc_info->compatible = "ralink,mt7628an-soc";
 550         } else {
 551                 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
 552         }
 553
 554         snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 555                 "Ralink %s ver:%u eco:%u",
 556                 name,
 557                 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
 558                 (rev & CHIP_REV_ECO_MASK));
 559
 560         cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
 561         if (is_mt76x8())
 562                 dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;
 563         else
 564                 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) &
 565                             SYSCFG0_DRAM_TYPE_MASK;
 566
 567         soc_info->mem_base = MT7620_DRAM_BASE;
 568         if (is_mt76x8())
 569                 mt7628_dram_init(soc_info);
 570         else
 571                 mt7620_dram_init(soc_info);
 572
 573         pmu0 = __raw_readl(sysc + PMU0_CFG);
 574         pmu1 = __raw_readl(sysc + PMU1_CFG);
 575
 576         pr_info("Analog PMU set to %s control\n",
 577                 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
 578         pr_info("Digital PMU set to %s control\n",
 579                 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
 580
 581         if (is_mt76x8())
 582                 rt2880_pinmux_data = mt7628an_pinmux_data;
 583         else
 584                 rt2880_pinmux_data = mt7620a_pinmux_data;
 585 }