arch/mips/ralink/mt7620.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify it
   3  * under the terms of the GNU General Public License version 2 as published
   4  * by the Free Software Foundation.
   5  *
   6  * Parts of this file are based on Ralink's 2.6.21 BSP
   7  *
   8  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   9  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  10  * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16
  17 #include <asm/mipsregs.h>
  18 #include <asm/mach-ralink/ralink_regs.h>
  19 #include <asm/mach-ralink/mt7620.h>
  20
  21 #include "common.h"
  22
  23 /* does the board have sdram or ddram */
  24 static int dram_type;
  25
  26 /* the pll dividers */
  27 static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
  28
  29 static struct ralink_pinmux_grp mode_mux[] = {
  30         {
  31                 .name = "i2c",
  32                 .mask = MT7620_GPIO_MODE_I2C,
  33                 .gpio_first = 1,
  34                 .gpio_last = 2,
  35         }, {
  36                 .name = "spi",
  37                 .mask = MT7620_GPIO_MODE_SPI,
  38                 .gpio_first = 3,
  39                 .gpio_last = 6,
  40         }, {
  41                 .name = "uartlite",
  42                 .mask = MT7620_GPIO_MODE_UART1,
  43                 .gpio_first = 15,
  44                 .gpio_last = 16,
  45         }, {
  46                 .name = "wdt",
  47                 .mask = MT7620_GPIO_MODE_WDT,
  48                 .gpio_first = 17,
  49                 .gpio_last = 17,
  50         }, {
  51                 .name = "mdio",
  52                 .mask = MT7620_GPIO_MODE_MDIO,
  53                 .gpio_first = 22,
  54                 .gpio_last = 23,
  55         }, {
  56                 .name = "rgmii1",
  57                 .mask = MT7620_GPIO_MODE_RGMII1,
  58                 .gpio_first = 24,
  59                 .gpio_last = 35,
  60         }, {
  61                 .name = "spi refclk",
  62                 .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
  63                 .gpio_first = 37,
  64                 .gpio_last = 39,
  65         }, {
  66                 .name = "jtag",
  67                 .mask = MT7620_GPIO_MODE_JTAG,
  68                 .gpio_first = 40,
  69                 .gpio_last = 44,
  70         }, {
  71                 /* shared lines with jtag */
  72                 .name = "ephy",
  73                 .mask = MT7620_GPIO_MODE_EPHY,
  74                 .gpio_first = 40,
  75                 .gpio_last = 44,
  76         }, {
  77                 .name = "nand",
  78                 .mask = MT7620_GPIO_MODE_JTAG,
  79                 .gpio_first = 45,
  80                 .gpio_last = 59,
  81         }, {
  82                 .name = "rgmii2",
  83                 .mask = MT7620_GPIO_MODE_RGMII2,
  84                 .gpio_first = 60,
  85                 .gpio_last = 71,
  86         }, {
  87                 .name = "wled",
  88                 .mask = MT7620_GPIO_MODE_WLED,
  89                 .gpio_first = 72,
  90                 .gpio_last = 72,
  91         }, {0}
  92 };
  93
  94 static struct ralink_pinmux_grp uart_mux[] = {
  95         {
  96                 .name = "uartf",
  97                 .mask = MT7620_GPIO_MODE_UARTF,
  98                 .gpio_first = 7,
  99                 .gpio_last = 14,
 100         }, {
 101                 .name = "pcm uartf",
 102                 .mask = MT7620_GPIO_MODE_PCM_UARTF,
 103                 .gpio_first = 7,
 104                 .gpio_last = 14,
 105         }, {
 106                 .name = "pcm i2s",
 107                 .mask = MT7620_GPIO_MODE_PCM_I2S,
 108                 .gpio_first = 7,
 109                 .gpio_last = 14,
 110         }, {
 111                 .name = "i2s uartf",
 112                 .mask = MT7620_GPIO_MODE_I2S_UARTF,
 113                 .gpio_first = 7,
 114                 .gpio_last = 14,
 115         }, {
 116                 .name = "pcm gpio",
 117                 .mask = MT7620_GPIO_MODE_PCM_GPIO,
 118                 .gpio_first = 11,
 119                 .gpio_last = 14,
 120         }, {
 121                 .name = "gpio uartf",
 122                 .mask = MT7620_GPIO_MODE_GPIO_UARTF,
 123                 .gpio_first = 7,
 124                 .gpio_last = 10,
 125         }, {
 126                 .name = "gpio i2s",
 127                 .mask = MT7620_GPIO_MODE_GPIO_I2S,
 128                 .gpio_first = 7,
 129                 .gpio_last = 10,
 130         }, {
 131                 .name = "gpio",
 132                 .mask = MT7620_GPIO_MODE_GPIO,
 133         }, {0}
 134 };
 135
 136 struct ralink_pinmux rt_gpio_pinmux = {
 137         .mode = mode_mux,
 138         .uart = uart_mux,
 139         .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
 140         .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
 141 };
 142
 143 void __init ralink_clk_init(void)
 144 {
 145         unsigned long cpu_rate, sys_rate;
 146         u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
 147         u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
 148         u32 swconfig = (c0 >> CPLL_SW_CONFIG_SHIFT) & CPLL_SW_CONFIG_MASK;
 149         u32 cpu_clk = (c1 >> CPLL_CPU_CLK_SHIFT) & CPLL_CPU_CLK_MASK;
 150
 151         if (cpu_clk) {
 152                 cpu_rate = 480000000;
 153         } else if (!swconfig) {
 154                 cpu_rate = 600000000;
 155         } else {
 156                 u32 m = (c0 >> CPLL_MULT_RATIO_SHIFT) & CPLL_MULT_RATIO;
 157                 u32 d = (c0 >> CPLL_DIV_RATIO_SHIFT) & CPLL_DIV_RATIO;
 158
 159                 cpu_rate = ((40 * (m + 24)) / mt7620_clk_divider[d]) * 1000000;
 160         }
 161
 162         if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
 163                 sys_rate = cpu_rate / 4;
 164         else
 165                 sys_rate = cpu_rate / 3;
 166
 167         ralink_clk_add("cpu", cpu_rate);
 168         ralink_clk_add("10000100.timer", 40000000);
 169         ralink_clk_add("10000500.uart", 40000000);
 170         ralink_clk_add("10000c00.uartlite", 40000000);
 171 }
 172
 173 void __init ralink_of_remap(void)
 174 {
 175         rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
 176         rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
 177
 178         if (!rt_sysc_membase || !rt_memc_membase)
 179                 panic("Failed to remap core resources");
 180 }
 181
 182 void prom_soc_init(struct ralink_soc_info *soc_info)
 183 {
 184         void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
 185         unsigned char *name = NULL;
 186         u32 n0;
 187         u32 n1;
 188         u32 rev;
 189         u32 cfg0;
 190
 191         n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 192         n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 193
 194         if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
 195                 name = "MT7620N";
 196                 soc_info->compatible = "ralink,mt7620n-soc";
 197         } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
 198                 name = "MT7620A";
 199                 soc_info->compatible = "ralink,mt7620a-soc";
 200         } else {
 201                 panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
 202         }
 203
 204         rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
 205
 206         snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 207                 "Ralink %s ver:%u eco:%u",
 208                 name,
 209                 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
 210                 (rev & CHIP_REV_ECO_MASK));
 211
 212         cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
 213         dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
 214
 215         switch (dram_type) {
 216         case SYSCFG0_DRAM_TYPE_SDRAM:
 217                 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
 218                 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
 219                 break;
 220
 221         case SYSCFG0_DRAM_TYPE_DDR1:
 222                 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
 223                 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
 224                 break;
 225
 226         case SYSCFG0_DRAM_TYPE_DDR2:
 227                 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
 228                 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
 229                 break;
 230         default:
 231                 BUG();
 232         }
 233         soc_info->mem_base = MT7620_DRAM_BASE;
 234 }