arch/mips/sgi-ip22/ip22-mc.c

   1 /*
   2  * ip22-mc.c: Routines for manipulating SGI Memory Controller.
   3  *
   4  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
   5  * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes
   6  * Copyright (C) 2003 Ladislav Michl  (ladis@linux-mips.org)
   7  * Copyright (C) 2004 Peter Fuerst    (pf@net.alphadv.de) - IP28
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13
  14 #include <asm/io.h>
  15 #include <asm/bootinfo.h>
  16 #include <asm/sgialib.h>
  17 #include <asm/sgi/mc.h>
  18 #include <asm/sgi/hpc3.h>
  19 #include <asm/sgi/ip22.h>
  20
  21 struct sgimc_regs *sgimc;
  22
  23 EXPORT_SYMBOL(sgimc);
  24
  25 static inline unsigned long get_bank_addr(unsigned int memconfig)
  26 {
  27         return (memconfig & SGIMC_MCONFIG_BASEADDR) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 24 : 22);
  28 }
  29
  30 static inline unsigned long get_bank_size(unsigned int memconfig)
  31 {
  32         return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 16 : 14);
  33 }
  34
  35 static inline unsigned int get_bank_config(int bank)
  36 {
  37         unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0;
  38         return bank % 2 ? res & 0xffff : res >> 16;
  39 }
  40
  41 struct mem {
  42         unsigned long addr;
  43         unsigned long size;
  44 };
  45
  46 /*
  47  * Detect installed memory, do some sanity checks and notify kernel about it
  48  */
  49 static void __init probe_memory(void)
  50 {
  51         int i, j, found, cnt = 0;
  52         struct mem bank[4];
  53         struct mem space[2] = {{SGIMC_SEG0_BADDR, 0}, {SGIMC_SEG1_BADDR, 0}};
  54
  55         printk(KERN_INFO "MC: Probing memory configuration:\n");
  56         for (i = 0; i < ARRAY_SIZE(bank); i++) {
  57                 unsigned int tmp = get_bank_config(i);
  58                 if (!(tmp & SGIMC_MCONFIG_BVALID))
  59                         continue;
  60
  61                 bank[cnt].size = get_bank_size(tmp);
  62                 bank[cnt].addr = get_bank_addr(tmp);
  63                 printk(KERN_INFO " bank%d: %3ldM @ %08lx\n",
  64                         i, bank[cnt].size / 1024 / 1024, bank[cnt].addr);
  65                 cnt++;
  66         }
  67
  68         /* And you thought bubble sort is dead algorithm... */
  69         do {
  70                 unsigned long addr, size;
  71
  72                 found = 0;
  73                 for (i = 1; i < cnt; i++)
  74                         if (bank[i-1].addr > bank[i].addr) {
  75                                 addr = bank[i].addr;
  76                                 size = bank[i].size;
  77                                 bank[i].addr = bank[i-1].addr;
  78                                 bank[i].size = bank[i-1].size;
  79                                 bank[i-1].addr = addr;
  80                                 bank[i-1].size = size;
  81                                 found = 1;
  82                         }
  83         } while (found);
  84
  85         /* Figure out how are memory banks mapped into spaces */
  86         for (i = 0; i < cnt; i++) {
  87                 found = 0;
  88                 for (j = 0; j < ARRAY_SIZE(space) && !found; j++)
  89                         if (space[j].addr + space[j].size == bank[i].addr) {
  90                                 space[j].size += bank[i].size;
  91                                 found = 1;
  92                         }
  93                 /* There is either hole or overlapping memory */
  94                 if (!found)
  95                         printk(KERN_CRIT "MC: Memory configuration mismatch "
  96                                          "(%08lx), expect Bus Error soon\n",
  97                                          bank[i].addr);
  98         }
  99
 100         for (i = 0; i < ARRAY_SIZE(space); i++)
 101                 if (space[i].size)
 102                         add_memory_region(space[i].addr, space[i].size,
 103                                           BOOT_MEM_RAM);
 104 }
 105
 106 void __init sgimc_init(void)
 107 {
 108         u32 tmp;
 109
 110         /* ioremap can't fail */
 111         sgimc = (struct sgimc_regs *)
 112                 ioremap(SGIMC_BASE, sizeof(struct sgimc_regs));
 113
 114         printk(KERN_INFO "MC: SGI memory controller Revision %d\n",
 115                (int) sgimc->systemid & SGIMC_SYSID_MASKREV);
 116
 117         /* Place the MC into a known state.  This must be done before
 118          * interrupts are first enabled etc.
 119          */
 120
 121         /* Step 0: Make sure we turn off the watchdog in case it's
 122          *         still running (which might be the case after a
 123          *         soft reboot).
 124          */
 125         tmp = sgimc->cpuctrl0;
 126         tmp &= ~SGIMC_CCTRL0_WDOG;
 127         sgimc->cpuctrl0 = tmp;
 128
 129         /* Step 1: The CPU/GIO error status registers will not latch
 130          *         up a new error status until the register has been
 131          *         cleared by the cpu.  These status registers are
 132          *         cleared by writing any value to them.
 133          */
 134         sgimc->cstat = sgimc->gstat = 0;
 135
 136         /* Step 2: Enable all parity checking in cpu control register
 137          *         zero.
 138          */
 139         /* don't touch parity settings for IP28 */
 140         tmp = sgimc->cpuctrl0;
 141 #ifndef CONFIG_SGI_IP28
 142         tmp |= SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM;
 143 #endif
 144         tmp |= SGIMC_CCTRL0_R4KNOCHKPARR;
 145         sgimc->cpuctrl0 = tmp;
 146
 147         /* Step 3: Setup the MC write buffer depth, this is controlled
 148          *         in cpu control register 1 in the lower 4 bits.
 149          */
 150         tmp = sgimc->cpuctrl1;
 151         tmp &= ~0xf;
 152         tmp |= 0xd;
 153         sgimc->cpuctrl1 = tmp;
 154
 155         /* Step 4: Initialize the RPSS divider register to run as fast
 156          *         as it can correctly operate.  The register is laid
 157          *         out as follows:
 158          *
 159          *         ----------------------------------------
 160          *         |  RESERVED  |   INCREMENT   | DIVIDER |
 161          *         ----------------------------------------
 162          *          31        16 15            8 7       0
 163          *
 164          *         DIVIDER determines how often a 'tick' happens,
 165          *         INCREMENT determines by how the RPSS increment
 166          *         registers value increases at each 'tick'. Thus,
 167          *         for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
 168          */
 169         sgimc->divider = 0x101;
 170
 171         /* Step 5: Initialize GIO64 arbitrator configuration register.
 172          *
 173          * NOTE: HPC init code in sgihpc_init() must run before us because
 174          *       we need to know Guiness vs. FullHouse and the board
 175          *       revision on this machine. You have been warned.
 176          */
 177
 178         /* First the basic invariants across all GIO64 implementations. */
 179         tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */
 180         tmp |= SGIMC_GIOPAR_HPC64;      /* All 1st HPC's interface at 64bits */
 181         tmp |= SGIMC_GIOPAR_ONEBUS;     /* Only one physical GIO bus exists */
 182
 183         if (ip22_is_fullhouse()) {
 184                 /* Fullhouse specific settings. */
 185                 if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) {
 186                         tmp |= SGIMC_GIOPAR_HPC264;     /* 2nd HPC at 64bits */
 187                         tmp |= SGIMC_GIOPAR_PLINEEXP0;  /* exp0 pipelines */
 188                         tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
 189                         tmp |= SGIMC_GIOPAR_RTIMEEXP0;  /* exp0 is realtime */
 190                 } else {
 191                         tmp |= SGIMC_GIOPAR_HPC264;     /* 2nd HPC 64bits */
 192                         tmp |= SGIMC_GIOPAR_PLINEEXP0;  /* exp[01] pipelined */
 193                         tmp |= SGIMC_GIOPAR_PLINEEXP1;
 194                         tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
 195                 }
 196         } else {
 197                 /* Guiness specific settings. */
 198                 tmp |= SGIMC_GIOPAR_EISA64;     /* MC talks to EISA at 64bits */
 199                 tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
 200         }
 201         sgimc->giopar = tmp;    /* poof */
 202
 203         probe_memory();
 204 }
 205
 206 void __init prom_meminit(void) {}
 207 void __init prom_free_prom_memory(void)
 208 {
 209 #ifdef CONFIG_SGI_IP28
 210         u32 mconfig1;
 211         unsigned long flags;
 212         spinlock_t lock;
 213
 214         /*
 215          * because ARCS accesses memory uncached we wait until ARCS
 216          * isn't needed any longer, before we switch from slow to
 217          * normal mode
 218          */
 219         spin_lock_irqsave(&lock, flags);
 220         mconfig1 = sgimc->mconfig1;
 221         /* map ECC register */
 222         sgimc->mconfig1 = (mconfig1 & 0xffff0000) | 0x2060;
 223         iob();
 224         /* switch to normal mode */
 225         *(unsigned long *)PHYS_TO_XKSEG_UNCACHED(0x60000000) = 0;
 226         iob();
 227         /* reduce WR_COL */
 228         sgimc->cmacc = (sgimc->cmacc & ~0xf) | 4;
 229         iob();
 230         /* restore old config */
 231         sgimc->mconfig1 = mconfig1;
 232         iob();
 233         spin_unlock_irqrestore(&lock, flags);
 234 #endif
 235 }