arch/mips/sgi-ip22/ip28-berr.c

   1 /*
   2  * ip28-berr.c: Bus error handling.
   3  *
   4  * Copyright (C) 2002, 2003 Ladislav Michl (ladis@linux-mips.org)
   5  * Copyright (C) 2005 Peter Fuerst (pf@net.alphadv.de) - IP28
   6  */
   7
   8 #include <linux/init.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/sched/debug.h>
  12 #include <linux/sched/signal.h>
  13 #include <linux/seq_file.h>
  14
  15 #include <asm/addrspace.h>
  16 #include <asm/traps.h>
  17 #include <asm/branch.h>
  18 #include <asm/irq_regs.h>
  19 #include <asm/sgi/mc.h>
  20 #include <asm/sgi/hpc3.h>
  21 #include <asm/sgi/ioc.h>
  22 #include <asm/sgi/ip22.h>
  23 #include <asm/r4kcache.h>
  24 #include <linux/uaccess.h>
  25 #include <asm/bootinfo.h>
  26
  27 static unsigned int count_be_is_fixup;
  28 static unsigned int count_be_handler;
  29 static unsigned int count_be_interrupt;
  30 static int debug_be_interrupt;
  31
  32 static unsigned int cpu_err_stat;       /* Status reg for CPU */
  33 static unsigned int gio_err_stat;       /* Status reg for GIO */
  34 static unsigned int cpu_err_addr;       /* Error address reg for CPU */
  35 static unsigned int gio_err_addr;       /* Error address reg for GIO */
  36 static unsigned int extio_stat;
  37 static unsigned int hpc3_berr_stat;     /* Bus error interrupt status */
  38
  39 struct hpc3_stat {
  40         unsigned long addr;
  41         unsigned int ctrl;
  42         unsigned int cbp;
  43         unsigned int ndptr;
  44 };
  45
  46 static struct {
  47         struct hpc3_stat pbdma[8];
  48         struct hpc3_stat scsi[2];
  49         struct hpc3_stat ethrx, ethtx;
  50 } hpc3;
  51
  52 static struct {
  53         unsigned long err_addr;
  54         struct {
  55                 u32 lo;
  56                 u32 hi;
  57         } tags[1][2], tagd[4][2], tagi[4][2]; /* Way 0/1 */
  58 } cache_tags;
  59
  60 static inline void save_cache_tags(unsigned busaddr)
  61 {
  62         unsigned long addr = CAC_BASE | busaddr;
  63         int i;
  64         cache_tags.err_addr = addr;
  65
  66         /*
  67          * Starting with a bus-address, save secondary cache (indexed by
  68          * PA[23..18:7..6]) tags first.
  69          */
  70         addr &= ~1L;
  71 #define tag cache_tags.tags[0]
  72         cache_op(Index_Load_Tag_S, addr);
  73         tag[0].lo = read_c0_taglo();    /* PA[35:18], VA[13:12] */
  74         tag[0].hi = read_c0_taghi();    /* PA[39:36] */
  75         cache_op(Index_Load_Tag_S, addr | 1L);
  76         tag[1].lo = read_c0_taglo();    /* PA[35:18], VA[13:12] */
  77         tag[1].hi = read_c0_taghi();    /* PA[39:36] */
  78 #undef tag
  79
  80         /*
  81          * Save all primary data cache (indexed by VA[13:5]) tags which
  82          * might fit to this bus-address, knowing that VA[11:0] == PA[11:0].
  83          * Saving all tags and evaluating them later is easier and safer
  84          * than relying on VA[13:12] from the secondary cache tags to pick
  85          * matching primary tags here already.
  86          */
  87         addr &= (0xffL << 56) | ((1 << 12) - 1);
  88 #define tag cache_tags.tagd[i]
  89         for (i = 0; i < 4; ++i, addr += (1 << 12)) {
  90                 cache_op(Index_Load_Tag_D, addr);
  91                 tag[0].lo = read_c0_taglo();    /* PA[35:12] */
  92                 tag[0].hi = read_c0_taghi();    /* PA[39:36] */
  93                 cache_op(Index_Load_Tag_D, addr | 1L);
  94                 tag[1].lo = read_c0_taglo();    /* PA[35:12] */
  95                 tag[1].hi = read_c0_taghi();    /* PA[39:36] */
  96         }
  97 #undef tag
  98
  99         /*
 100          * Save primary instruction cache (indexed by VA[13:6]) tags
 101          * the same way.
 102          */
 103         addr &= (0xffL << 56) | ((1 << 12) - 1);
 104 #define tag cache_tags.tagi[i]
 105         for (i = 0; i < 4; ++i, addr += (1 << 12)) {
 106                 cache_op(Index_Load_Tag_I, addr);
 107                 tag[0].lo = read_c0_taglo();    /* PA[35:12] */
 108                 tag[0].hi = read_c0_taghi();    /* PA[39:36] */
 109                 cache_op(Index_Load_Tag_I, addr | 1L);
 110                 tag[1].lo = read_c0_taglo();    /* PA[35:12] */
 111                 tag[1].hi = read_c0_taghi();    /* PA[39:36] */
 112         }
 113 #undef tag
 114 }
 115
 116 #define GIO_ERRMASK     0xff00
 117 #define CPU_ERRMASK     0x3f00
 118
 119 static void save_and_clear_buserr(void)
 120 {
 121         int i;
 122
 123         /* save status registers */
 124         cpu_err_addr = sgimc->cerr;
 125         cpu_err_stat = sgimc->cstat;
 126         gio_err_addr = sgimc->gerr;
 127         gio_err_stat = sgimc->gstat;
 128         extio_stat = sgioc->extio;
 129         hpc3_berr_stat = hpc3c0->bestat;
 130
 131         hpc3.scsi[0].addr  = (unsigned long)&hpc3c0->scsi_chan0;
 132         hpc3.scsi[0].ctrl  = hpc3c0->scsi_chan0.ctrl; /* HPC3_SCTRL_ACTIVE ? */
 133         hpc3.scsi[0].cbp   = hpc3c0->scsi_chan0.cbptr;
 134         hpc3.scsi[0].ndptr = hpc3c0->scsi_chan0.ndptr;
 135
 136         hpc3.scsi[1].addr  = (unsigned long)&hpc3c0->scsi_chan1;
 137         hpc3.scsi[1].ctrl  = hpc3c0->scsi_chan1.ctrl; /* HPC3_SCTRL_ACTIVE ? */
 138         hpc3.scsi[1].cbp   = hpc3c0->scsi_chan1.cbptr;
 139         hpc3.scsi[1].ndptr = hpc3c0->scsi_chan1.ndptr;
 140
 141         hpc3.ethrx.addr  = (unsigned long)&hpc3c0->ethregs.rx_cbptr;
 142         hpc3.ethrx.ctrl  = hpc3c0->ethregs.rx_ctrl; /* HPC3_ERXCTRL_ACTIVE ? */
 143         hpc3.ethrx.cbp   = hpc3c0->ethregs.rx_cbptr;
 144         hpc3.ethrx.ndptr = hpc3c0->ethregs.rx_ndptr;
 145
 146         hpc3.ethtx.addr  = (unsigned long)&hpc3c0->ethregs.tx_cbptr;
 147         hpc3.ethtx.ctrl  = hpc3c0->ethregs.tx_ctrl; /* HPC3_ETXCTRL_ACTIVE ? */
 148         hpc3.ethtx.cbp   = hpc3c0->ethregs.tx_cbptr;
 149         hpc3.ethtx.ndptr = hpc3c0->ethregs.tx_ndptr;
 150
 151         for (i = 0; i < 8; ++i) {
 152                 /* HPC3_PDMACTRL_ISACT ? */
 153                 hpc3.pbdma[i].addr  = (unsigned long)&hpc3c0->pbdma[i];
 154                 hpc3.pbdma[i].ctrl  = hpc3c0->pbdma[i].pbdma_ctrl;
 155                 hpc3.pbdma[i].cbp   = hpc3c0->pbdma[i].pbdma_bptr;
 156                 hpc3.pbdma[i].ndptr = hpc3c0->pbdma[i].pbdma_dptr;
 157         }
 158         i = 0;
 159         if (gio_err_stat & CPU_ERRMASK)
 160                 i = gio_err_addr;
 161         if (cpu_err_stat & CPU_ERRMASK)
 162                 i = cpu_err_addr;
 163         save_cache_tags(i);
 164
 165         sgimc->cstat = sgimc->gstat = 0;
 166 }
 167
 168 static void print_cache_tags(void)
 169 {
 170         u32 scb, scw;
 171         int i;
 172
 173         printk(KERN_ERR "Cache tags @ %08x:\n", (unsigned)cache_tags.err_addr);
 174
 175         /* PA[31:12] shifted to PTag0 (PA[35:12]) format */
 176         scw = (cache_tags.err_addr >> 4) & 0x0fffff00;
 177
 178         scb = cache_tags.err_addr & ((1 << 12) - 1) & ~((1 << 5) - 1);
 179         for (i = 0; i < 4; ++i) { /* for each possible VA[13:12] value */
 180                 if ((cache_tags.tagd[i][0].lo & 0x0fffff00) != scw &&
 181                     (cache_tags.tagd[i][1].lo & 0x0fffff00) != scw)
 182                     continue;
 183                 printk(KERN_ERR
 184                        "D: 0: %08x %08x, 1: %08x %08x  (VA[13:5]  %04x)\n",
 185                         cache_tags.tagd[i][0].hi, cache_tags.tagd[i][0].lo,
 186                         cache_tags.tagd[i][1].hi, cache_tags.tagd[i][1].lo,
 187                         scb | (1 << 12)*i);
 188         }
 189         scb = cache_tags.err_addr & ((1 << 12) - 1) & ~((1 << 6) - 1);
 190         for (i = 0; i < 4; ++i) { /* for each possible VA[13:12] value */
 191                 if ((cache_tags.tagi[i][0].lo & 0x0fffff00) != scw &&
 192                     (cache_tags.tagi[i][1].lo & 0x0fffff00) != scw)
 193                     continue;
 194                 printk(KERN_ERR
 195                        "I: 0: %08x %08x, 1: %08x %08x  (VA[13:6]  %04x)\n",
 196                         cache_tags.tagi[i][0].hi, cache_tags.tagi[i][0].lo,
 197                         cache_tags.tagi[i][1].hi, cache_tags.tagi[i][1].lo,
 198                         scb | (1 << 12)*i);
 199         }
 200         i = read_c0_config();
 201         scb = i & (1 << 13) ? 7:6;      /* scblksize = 2^[7..6] */
 202         scw = ((i >> 16) & 7) + 19 - 1; /* scwaysize = 2^[24..19] / 2 */
 203
 204         i = ((1 << scw) - 1) & ~((1 << scb) - 1);
 205         printk(KERN_ERR "S: 0: %08x %08x, 1: %08x %08x  (PA[%u:%u] %05x)\n",
 206                 cache_tags.tags[0][0].hi, cache_tags.tags[0][0].lo,
 207                 cache_tags.tags[0][1].hi, cache_tags.tags[0][1].lo,
 208                 scw-1, scb, i & (unsigned)cache_tags.err_addr);
 209 }
 210
 211 static inline const char *cause_excode_text(int cause)
 212 {
 213         static const char *txt[32] =
 214         {       "Interrupt",
 215                 "TLB modification",
 216                 "TLB (load or instruction fetch)",
 217                 "TLB (store)",
 218                 "Address error (load or instruction fetch)",
 219                 "Address error (store)",
 220                 "Bus error (instruction fetch)",
 221                 "Bus error (data: load or store)",
 222                 "Syscall",
 223                 "Breakpoint",
 224                 "Reserved instruction",
 225                 "Coprocessor unusable",
 226                 "Arithmetic Overflow",
 227                 "Trap",
 228                 "14",
 229                 "Floating-Point",
 230                 "16", "17", "18", "19", "20", "21", "22",
 231                 "Watch Hi/Lo",
 232                 "24", "25", "26", "27", "28", "29", "30", "31",
 233         };
 234         return txt[(cause & 0x7c) >> 2];
 235 }
 236
 237 static void print_buserr(const struct pt_regs *regs)
 238 {
 239         const int field = 2 * sizeof(unsigned long);
 240         int error = 0;
 241
 242         if (extio_stat & EXTIO_MC_BUSERR) {
 243                 printk(KERN_ERR "MC Bus Error\n");
 244                 error |= 1;
 245         }
 246         if (extio_stat & EXTIO_HPC3_BUSERR) {
 247                 printk(KERN_ERR "HPC3 Bus Error 0x%x:<id=0x%x,%s,lane=0x%x>\n",
 248                         hpc3_berr_stat,
 249                         (hpc3_berr_stat & HPC3_BESTAT_PIDMASK) >>
 250                                           HPC3_BESTAT_PIDSHIFT,
 251                         (hpc3_berr_stat & HPC3_BESTAT_CTYPE) ? "PIO" : "DMA",
 252                         hpc3_berr_stat & HPC3_BESTAT_BLMASK);
 253                 error |= 2;
 254         }
 255         if (extio_stat & EXTIO_EISA_BUSERR) {
 256                 printk(KERN_ERR "EISA Bus Error\n");
 257                 error |= 4;
 258         }
 259         if (cpu_err_stat & CPU_ERRMASK) {
 260                 printk(KERN_ERR "CPU error 0x%x<%s%s%s%s%s%s> @ 0x%08x\n",
 261                         cpu_err_stat,
 262                         cpu_err_stat & SGIMC_CSTAT_RD ? "RD " : "",
 263                         cpu_err_stat & SGIMC_CSTAT_PAR ? "PAR " : "",
 264                         cpu_err_stat & SGIMC_CSTAT_ADDR ? "ADDR " : "",
 265                         cpu_err_stat & SGIMC_CSTAT_SYSAD_PAR ? "SYSAD " : "",
 266                         cpu_err_stat & SGIMC_CSTAT_SYSCMD_PAR ? "SYSCMD " : "",
 267                         cpu_err_stat & SGIMC_CSTAT_BAD_DATA ? "BAD_DATA " : "",
 268                         cpu_err_addr);
 269                 error |= 8;
 270         }
 271         if (gio_err_stat & GIO_ERRMASK) {
 272                 printk(KERN_ERR "GIO error 0x%x:<%s%s%s%s%s%s%s%s> @ 0x%08x\n",
 273                         gio_err_stat,
 274                         gio_err_stat & SGIMC_GSTAT_RD ? "RD " : "",
 275                         gio_err_stat & SGIMC_GSTAT_WR ? "WR " : "",
 276                         gio_err_stat & SGIMC_GSTAT_TIME ? "TIME " : "",
 277                         gio_err_stat & SGIMC_GSTAT_PROM ? "PROM " : "",
 278                         gio_err_stat & SGIMC_GSTAT_ADDR ? "ADDR " : "",
 279                         gio_err_stat & SGIMC_GSTAT_BC ? "BC " : "",
 280                         gio_err_stat & SGIMC_GSTAT_PIO_RD ? "PIO_RD " : "",
 281                         gio_err_stat & SGIMC_GSTAT_PIO_WR ? "PIO_WR " : "",
 282                         gio_err_addr);
 283                 error |= 16;
 284         }
 285         if (!error)
 286                 printk(KERN_ERR "MC: Hmm, didn't find any error condition.\n");
 287         else {
 288                 printk(KERN_ERR "CP0: config %08x,  "
 289                         "MC: cpuctrl0/1: %08x/%05x, giopar: %04x\n"
 290                         "MC: cpu/gio_memacc: %08x/%05x, memcfg0/1: %08x/%08x\n",
 291                         read_c0_config(),
 292                         sgimc->cpuctrl0, sgimc->cpuctrl0, sgimc->giopar,
 293                         sgimc->cmacc, sgimc->gmacc,
 294                         sgimc->mconfig0, sgimc->mconfig1);
 295                 print_cache_tags();
 296         }
 297         printk(KERN_ALERT "%s, epc == %0*lx, ra == %0*lx\n",
 298                cause_excode_text(regs->cp0_cause),
 299                field, regs->cp0_epc, field, regs->regs[31]);
 300 }
 301
 302 /*
 303  * Check, whether MC's (virtual) DMA address caused the bus error.
 304  * See "Virtual DMA Specification", Draft 1.5, Feb 13 1992, SGI
 305  */
 306
 307 static int addr_is_ram(unsigned long addr, unsigned sz)
 308 {
 309         int i;
 310
 311         for (i = 0; i < boot_mem_map.nr_map; i++) {
 312                 unsigned long a = boot_mem_map.map[i].addr;
 313                 if (a <= addr && addr+sz <= a+boot_mem_map.map[i].size)
 314                         return 1;
 315         }
 316         return 0;
 317 }
 318
 319 static int check_microtlb(u32 hi, u32 lo, unsigned long vaddr)
 320 {
 321         /* This is likely rather similar to correct code ;-) */
 322
 323         vaddr &= 0x7fffffff; /* Doc. states that top bit is ignored */
 324
 325         /* If tlb-entry is valid and VPN-high (bits [30:21] ?) matches... */
 326         if ((lo & 2) && (vaddr >> 21) == ((hi<<1) >> 22)) {
 327                 u32 ctl = sgimc->dma_ctrl;
 328                 if (ctl & 1) {
 329                         unsigned int pgsz = (ctl & 2) ? 14:12; /* 16k:4k */
 330                         /* PTEIndex is VPN-low (bits [22:14]/[20:12] ?) */
 331                         unsigned long pte = (lo >> 6) << 12; /* PTEBase */
 332                         pte += 8*((vaddr >> pgsz) & 0x1ff);
 333                         if (addr_is_ram(pte, 8)) {
 334                                 /*
 335                                  * Note: Since DMA hardware does look up
 336                                  * translation on its own, this PTE *must*
 337                                  * match the TLB/EntryLo-register format !
 338                                  */
 339                                 unsigned long a = *(unsigned long *)
 340                                                 PHYS_TO_XKSEG_UNCACHED(pte);
 341                                 a = (a & 0x3f) << 6; /* PFN */
 342                                 a += vaddr & ((1 << pgsz) - 1);
 343                                 return cpu_err_addr == a;
 344                         }
 345                 }
 346         }
 347         return 0;
 348 }
 349
 350 static int check_vdma_memaddr(void)
 351 {
 352         if (cpu_err_stat & CPU_ERRMASK) {
 353                 u32 a = sgimc->maddronly;
 354
 355                 if (!(sgimc->dma_ctrl & 0x100)) /* Xlate-bit clear ? */
 356                         return cpu_err_addr == a;
 357
 358                 if (check_microtlb(sgimc->dtlb_hi0, sgimc->dtlb_lo0, a) ||
 359                     check_microtlb(sgimc->dtlb_hi1, sgimc->dtlb_lo1, a) ||
 360                     check_microtlb(sgimc->dtlb_hi2, sgimc->dtlb_lo2, a) ||
 361                     check_microtlb(sgimc->dtlb_hi3, sgimc->dtlb_lo3, a))
 362                         return 1;
 363         }
 364         return 0;
 365 }
 366
 367 static int check_vdma_gioaddr(void)
 368 {
 369         if (gio_err_stat & GIO_ERRMASK) {
 370                 u32 a = sgimc->gio_dma_trans;
 371                 a = (sgimc->gmaddronly & ~a) | (sgimc->gio_dma_sbits & a);
 372                 return gio_err_addr == a;
 373         }
 374         return 0;
 375 }
 376
 377 /*
 378  * MC sends an interrupt whenever bus or parity errors occur. In addition,
 379  * if the error happened during a CPU read, it also asserts the bus error
 380  * pin on the R4K. Code in bus error handler save the MC bus error registers
 381  * and then clear the interrupt when this happens.
 382  */
 383
 384 static int ip28_be_interrupt(const struct pt_regs *regs)
 385 {
 386         int i;
 387
 388         save_and_clear_buserr();
 389         /*
 390          * Try to find out, whether we got here by a mispredicted speculative
 391          * load/store operation.  If so, it's not fatal, we can go on.
 392          */
 393         /* Any cause other than "Interrupt" (ExcCode 0) is fatal. */
 394         if (regs->cp0_cause & CAUSEF_EXCCODE)
 395                 goto mips_be_fatal;
 396
 397         /* Any cause other than "Bus error interrupt" (IP6) is weird. */
 398         if ((regs->cp0_cause & CAUSEF_IP6) != CAUSEF_IP6)
 399                 goto mips_be_fatal;
 400
 401         if (extio_stat & (EXTIO_HPC3_BUSERR | EXTIO_EISA_BUSERR))
 402                 goto mips_be_fatal;
 403
 404         /* Any state other than "Memory bus error" is fatal. */
 405         if (cpu_err_stat & CPU_ERRMASK & ~SGIMC_CSTAT_ADDR)
 406                 goto mips_be_fatal;
 407
 408         /* GIO errors other than timeouts are fatal */
 409         if (gio_err_stat & GIO_ERRMASK & ~SGIMC_GSTAT_TIME)
 410                 goto mips_be_fatal;
 411
 412         /*
 413          * Now we have an asynchronous bus error, speculatively or DMA caused.
 414          * Need to search all DMA descriptors for the error address.
 415          */
 416         for (i = 0; i < sizeof(hpc3)/sizeof(struct hpc3_stat); ++i) {
 417                 struct hpc3_stat *hp = (struct hpc3_stat *)&hpc3 + i;
 418                 if ((cpu_err_stat & CPU_ERRMASK) &&
 419                     (cpu_err_addr == hp->ndptr || cpu_err_addr == hp->cbp))
 420                         break;
 421                 if ((gio_err_stat & GIO_ERRMASK) &&
 422                     (gio_err_addr == hp->ndptr || gio_err_addr == hp->cbp))
 423                         break;
 424         }
 425         if (i < sizeof(hpc3)/sizeof(struct hpc3_stat)) {
 426                 struct hpc3_stat *hp = (struct hpc3_stat *)&hpc3 + i;
 427                 printk(KERN_ERR "at DMA addresses: HPC3 @ %08lx:"
 428                        " ctl %08x, ndp %08x, cbp %08x\n",
 429                        CPHYSADDR(hp->addr), hp->ctrl, hp->ndptr, hp->cbp);
 430                 goto mips_be_fatal;
 431         }
 432         /* Check MC's virtual DMA stuff. */
 433         if (check_vdma_memaddr()) {
 434                 printk(KERN_ERR "at GIO DMA: mem address 0x%08x.\n",
 435                         sgimc->maddronly);
 436                 goto mips_be_fatal;
 437         }
 438         if (check_vdma_gioaddr()) {
 439                 printk(KERN_ERR "at GIO DMA: gio address 0x%08x.\n",
 440                         sgimc->gmaddronly);
 441                 goto mips_be_fatal;
 442         }
 443         /* A speculative bus error... */
 444         if (debug_be_interrupt) {
 445                 print_buserr(regs);
 446                 printk(KERN_ERR "discarded!\n");
 447         }
 448         return MIPS_BE_DISCARD;
 449
 450 mips_be_fatal:
 451         print_buserr(regs);
 452         return MIPS_BE_FATAL;
 453 }
 454
 455 void ip22_be_interrupt(int irq)
 456 {
 457         struct pt_regs *regs = get_irq_regs();
 458
 459         count_be_interrupt++;
 460
 461         if (ip28_be_interrupt(regs) != MIPS_BE_DISCARD) {
 462                 /* Assume it would be too dangerous to continue ... */
 463                 die_if_kernel("Oops", regs);
 464                 force_sig(SIGBUS, current);
 465         } else if (debug_be_interrupt)
 466                 show_regs((struct pt_regs *)regs);
 467 }
 468
 469 static int ip28_be_handler(struct pt_regs *regs, int is_fixup)
 470 {
 471         /*
 472          * We arrive here only in the unusual case of do_be() invocation,
 473          * i.e. by a bus error exception without a bus error interrupt.
 474          */
 475         if (is_fixup) {
 476                 count_be_is_fixup++;
 477                 save_and_clear_buserr();
 478                 return MIPS_BE_FIXUP;
 479         }
 480         count_be_handler++;
 481         return ip28_be_interrupt(regs);
 482 }
 483
 484 void __init ip22_be_init(void)
 485 {
 486         board_be_handler = ip28_be_handler;
 487 }
 488
 489 int ip28_show_be_info(struct seq_file *m)
 490 {
 491         seq_printf(m, "IP28 be fixups\t\t: %u\n", count_be_is_fixup);
 492         seq_printf(m, "IP28 be interrupts\t: %u\n", count_be_interrupt);
 493         seq_printf(m, "IP28 be handler\t\t: %u\n", count_be_handler);
 494
 495         return 0;
 496 }
 497
 498 static int __init debug_be_setup(char *str)
 499 {
 500         debug_be_interrupt++;
 501         return 1;
 502 }
 503 __setup("ip28_debug_be", debug_be_setup);