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Merge branch 'drm-patches' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[mirror_ubuntu-artful-kernel.git] / arch / mips / tx4927 / toshiba_rbtx4927 / toshiba_rbtx4927_setup.c
1 /*
2 * Toshiba rbtx4927 specific setup
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright 2001-2002 MontaVista Software Inc.
8 *
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * Copyright (C) 2000 RidgeRun, Inc.
11 * Author: RidgeRun, Inc.
12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
13 *
14 * Copyright 2001 MontaVista Software Inc.
15 * Author: jsun@mvista.com or jsun@junsun.net
16 *
17 * Copyright 2002 MontaVista Software Inc.
18 * Author: Michael Pruznick, michael_pruznick@mvista.com
19 *
20 * Copyright (C) 2000-2001 Toshiba Corporation
21 *
22 * Copyright (C) 2004 MontaVista Software Inc.
23 * Author: Manish Lachwani, mlachwani@mvista.com
24 *
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
29 *
30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * You should have received a copy of the GNU General Public License along
42 * with this program; if not, write to the Free Software Foundation, Inc.,
43 * 675 Mass Ave, Cambridge, MA 02139, USA.
44 */
45 #include <linux/init.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
48 #include <linux/mm.h>
49 #include <linux/swap.h>
50 #include <linux/ioport.h>
51 #include <linux/sched.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/timex.h>
55 #include <linux/pm.h>
56 #include <linux/platform_device.h>
57
58 #include <asm/bootinfo.h>
59 #include <asm/page.h>
60 #include <asm/io.h>
61 #include <asm/irq.h>
62 #include <asm/irq_regs.h>
63 #include <asm/processor.h>
64 #include <asm/reboot.h>
65 #include <asm/time.h>
66 #include <linux/bootmem.h>
67 #include <linux/blkdev.h>
68 #ifdef CONFIG_TOSHIBA_FPCIB0
69 #include <asm/tx4927/smsc_fdc37m81x.h>
70 #endif
71 #include <asm/tx4927/toshiba_rbtx4927.h>
72 #ifdef CONFIG_PCI
73 #include <asm/tx4927/tx4927_pci.h>
74 #endif
75 #ifdef CONFIG_BLK_DEV_IDEPCI
76 #include <linux/hdreg.h>
77 #include <linux/ide.h>
78 #endif
79 #ifdef CONFIG_SERIAL_TXX9
80 #include <linux/tty.h>
81 #include <linux/serial.h>
82 #include <linux/serial_core.h>
83 #endif
84
85 #undef TOSHIBA_RBTX4927_SETUP_DEBUG
86
87 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
88 #define TOSHIBA_RBTX4927_SETUP_NONE 0x00000000
89
90 #define TOSHIBA_RBTX4927_SETUP_INFO ( 1 << 0 )
91 #define TOSHIBA_RBTX4927_SETUP_WARN ( 1 << 1 )
92 #define TOSHIBA_RBTX4927_SETUP_EROR ( 1 << 2 )
93
94 #define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
95 #define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
96 #define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
97 #define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 << 6 )
98 #define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
99 #define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
100 #define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
101 #define TOSHIBA_RBTX4927_SETUP_PCI66 ( 1 << 10 )
102
103 #define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
104 #endif
105
106 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
107 static const u32 toshiba_rbtx4927_setup_debug_flag =
108 (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
109 TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
110 TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
111 TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
112 | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
113 TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
114 #endif
115
116 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
117 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
118 if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
119 { \
120 char tmp[100]; \
121 sprintf( tmp, str ); \
122 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
123 }
124 #else
125 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...)
126 #endif
127
128 /* These functions are used for rebooting or halting the machine*/
129 extern void toshiba_rbtx4927_restart(char *command);
130 extern void toshiba_rbtx4927_halt(void);
131 extern void toshiba_rbtx4927_power_off(void);
132
133 int tx4927_using_backplane = 0;
134
135 extern void gt64120_time_init(void);
136 extern void toshiba_rbtx4927_irq_setup(void);
137
138 char *prom_getcmdline(void);
139
140 #ifdef CONFIG_PCI
141 #undef TX4927_SUPPORT_COMMAND_IO
142 #undef TX4927_SUPPORT_PCI_66
143 int tx4927_cpu_clock = 100000000; /* 100MHz */
144 unsigned long mips_pci_io_base;
145 unsigned long mips_pci_io_size;
146 unsigned long mips_pci_mem_base;
147 unsigned long mips_pci_mem_size;
148 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
149 unsigned long mips_pci_io_pciaddr = 0;
150 unsigned long mips_memory_upper;
151 static int tx4927_ccfg_toeon = 1;
152 static int tx4927_pcic_trdyto = 0; /* default: disabled */
153 unsigned long tx4927_ce_base[8];
154 void tx4927_pci_setup(void);
155 void tx4927_reset_pci_pcic(void);
156 int tx4927_pci66 = 0; /* 0:auto */
157 #endif
158
159 char *toshiba_name = "";
160
161 #ifdef CONFIG_PCI
162 extern struct pci_controller tx4927_controller;
163
164 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
165 int top_bus, int busnr, int devfn)
166 {
167 static struct pci_dev dev;
168 static struct pci_bus bus;
169
170 dev.sysdata = (void *)hose;
171 dev.devfn = devfn;
172 bus.number = busnr;
173 bus.ops = hose->pci_ops;
174 bus.parent = NULL;
175 dev.bus = &bus;
176
177 return &dev;
178 }
179
180 #define EARLY_PCI_OP(rw, size, type) \
181 static int early_##rw##_config_##size(struct pci_controller *hose, \
182 int top_bus, int bus, int devfn, int offset, type value) \
183 { \
184 return pci_##rw##_config_##size( \
185 fake_pci_dev(hose, top_bus, bus, devfn), \
186 offset, value); \
187 }
188
189 EARLY_PCI_OP(read, byte, u8 *)
190 EARLY_PCI_OP(read, dword, u32 *)
191 EARLY_PCI_OP(write, byte, u8)
192 EARLY_PCI_OP(write, dword, u32)
193
194 static int __init tx4927_pcibios_init(void)
195 {
196 unsigned int id;
197 u32 pci_devfn;
198 int devfn_start = 0;
199 int devfn_stop = 0xff;
200 int busno = 0; /* One bus on the Toshiba */
201 struct pci_controller *hose = &tx4927_controller;
202
203 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
204 "-\n");
205
206 for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
207 early_read_config_dword(hose, busno, busno, pci_devfn,
208 PCI_VENDOR_ID, &id);
209
210 if (id == 0xffffffff) {
211 continue;
212 }
213
214 if (id == 0x94601055) {
215 u8 v08_64;
216 u32 v32_b0;
217 u8 v08_e1;
218 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
219 char *s = " sb/isa --";
220 #endif
221
222 TOSHIBA_RBTX4927_SETUP_DPRINTK
223 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
224 s);
225
226 early_read_config_byte(hose, busno, busno,
227 pci_devfn, 0x64, &v08_64);
228 early_read_config_dword(hose, busno, busno,
229 pci_devfn, 0xb0, &v32_b0);
230 early_read_config_byte(hose, busno, busno,
231 pci_devfn, 0xe1, &v08_e1);
232
233 TOSHIBA_RBTX4927_SETUP_DPRINTK
234 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
235 ":%s beg 0x64 = 0x%02x\n", s, v08_64);
236 TOSHIBA_RBTX4927_SETUP_DPRINTK
237 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
238 ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
239 TOSHIBA_RBTX4927_SETUP_DPRINTK
240 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
241 ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
242
243 /* serial irq control */
244 v08_64 = 0xd0;
245
246 /* serial irq pin */
247 v32_b0 |= 0x00010000;
248
249 /* ide irq on isa14 */
250 v08_e1 &= 0xf0;
251 v08_e1 |= 0x0d;
252
253 TOSHIBA_RBTX4927_SETUP_DPRINTK
254 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
255 ":%s mid 0x64 = 0x%02x\n", s, v08_64);
256 TOSHIBA_RBTX4927_SETUP_DPRINTK
257 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
258 ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
259 TOSHIBA_RBTX4927_SETUP_DPRINTK
260 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
261 ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
262
263 early_write_config_byte(hose, busno, busno,
264 pci_devfn, 0x64, v08_64);
265 early_write_config_dword(hose, busno, busno,
266 pci_devfn, 0xb0, v32_b0);
267 early_write_config_byte(hose, busno, busno,
268 pci_devfn, 0xe1, v08_e1);
269
270 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
271 {
272 early_read_config_byte(hose, busno, busno,
273 pci_devfn, 0x64,
274 &v08_64);
275 early_read_config_dword(hose, busno, busno,
276 pci_devfn, 0xb0,
277 &v32_b0);
278 early_read_config_byte(hose, busno, busno,
279 pci_devfn, 0xe1,
280 &v08_e1);
281
282 TOSHIBA_RBTX4927_SETUP_DPRINTK
283 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
284 ":%s end 0x64 = 0x%02x\n", s, v08_64);
285 TOSHIBA_RBTX4927_SETUP_DPRINTK
286 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
287 ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
288 TOSHIBA_RBTX4927_SETUP_DPRINTK
289 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
290 ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
291 }
292 #endif
293
294 TOSHIBA_RBTX4927_SETUP_DPRINTK
295 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
296 s);
297 }
298
299 if (id == 0x91301055) {
300 u8 v08_04;
301 u8 v08_09;
302 u8 v08_41;
303 u8 v08_43;
304 u8 v08_5c;
305 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
306 char *s = " sb/ide --";
307 #endif
308
309 TOSHIBA_RBTX4927_SETUP_DPRINTK
310 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
311 s);
312
313 early_read_config_byte(hose, busno, busno,
314 pci_devfn, 0x04, &v08_04);
315 early_read_config_byte(hose, busno, busno,
316 pci_devfn, 0x09, &v08_09);
317 early_read_config_byte(hose, busno, busno,
318 pci_devfn, 0x41, &v08_41);
319 early_read_config_byte(hose, busno, busno,
320 pci_devfn, 0x43, &v08_43);
321 early_read_config_byte(hose, busno, busno,
322 pci_devfn, 0x5c, &v08_5c);
323
324 TOSHIBA_RBTX4927_SETUP_DPRINTK
325 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
326 ":%s beg 0x04 = 0x%02x\n", s, v08_04);
327 TOSHIBA_RBTX4927_SETUP_DPRINTK
328 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
329 ":%s beg 0x09 = 0x%02x\n", s, v08_09);
330 TOSHIBA_RBTX4927_SETUP_DPRINTK
331 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
332 ":%s beg 0x41 = 0x%02x\n", s, v08_41);
333 TOSHIBA_RBTX4927_SETUP_DPRINTK
334 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
335 ":%s beg 0x43 = 0x%02x\n", s, v08_43);
336 TOSHIBA_RBTX4927_SETUP_DPRINTK
337 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
338 ":%s beg 0x5c = 0x%02x\n", s, v08_5c);
339
340 /* enable ide master/io */
341 v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
342
343 /* enable ide native mode */
344 v08_09 |= 0x05;
345
346 /* enable primary ide */
347 v08_41 |= 0x80;
348
349 /* enable secondary ide */
350 v08_43 |= 0x80;
351
352 /*
353 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
354 *
355 * This line of code is intended to provide the user with a work
356 * around solution to the anomalies cited in SMSC's anomaly sheet
357 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
358 *
359 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
360 */
361 v08_5c |= 0x01;
362
363 TOSHIBA_RBTX4927_SETUP_DPRINTK
364 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
365 ":%s mid 0x04 = 0x%02x\n", s, v08_04);
366 TOSHIBA_RBTX4927_SETUP_DPRINTK
367 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
368 ":%s mid 0x09 = 0x%02x\n", s, v08_09);
369 TOSHIBA_RBTX4927_SETUP_DPRINTK
370 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
371 ":%s mid 0x41 = 0x%02x\n", s, v08_41);
372 TOSHIBA_RBTX4927_SETUP_DPRINTK
373 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
374 ":%s mid 0x43 = 0x%02x\n", s, v08_43);
375 TOSHIBA_RBTX4927_SETUP_DPRINTK
376 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
377 ":%s mid 0x5c = 0x%02x\n", s, v08_5c);
378
379 early_write_config_byte(hose, busno, busno,
380 pci_devfn, 0x5c, v08_5c);
381 early_write_config_byte(hose, busno, busno,
382 pci_devfn, 0x04, v08_04);
383 early_write_config_byte(hose, busno, busno,
384 pci_devfn, 0x09, v08_09);
385 early_write_config_byte(hose, busno, busno,
386 pci_devfn, 0x41, v08_41);
387 early_write_config_byte(hose, busno, busno,
388 pci_devfn, 0x43, v08_43);
389
390 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
391 {
392 early_read_config_byte(hose, busno, busno,
393 pci_devfn, 0x04,
394 &v08_04);
395 early_read_config_byte(hose, busno, busno,
396 pci_devfn, 0x09,
397 &v08_09);
398 early_read_config_byte(hose, busno, busno,
399 pci_devfn, 0x41,
400 &v08_41);
401 early_read_config_byte(hose, busno, busno,
402 pci_devfn, 0x43,
403 &v08_43);
404 early_read_config_byte(hose, busno, busno,
405 pci_devfn, 0x5c,
406 &v08_5c);
407
408 TOSHIBA_RBTX4927_SETUP_DPRINTK
409 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
410 ":%s end 0x04 = 0x%02x\n", s, v08_04);
411 TOSHIBA_RBTX4927_SETUP_DPRINTK
412 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
413 ":%s end 0x09 = 0x%02x\n", s, v08_09);
414 TOSHIBA_RBTX4927_SETUP_DPRINTK
415 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
416 ":%s end 0x41 = 0x%02x\n", s, v08_41);
417 TOSHIBA_RBTX4927_SETUP_DPRINTK
418 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
419 ":%s end 0x43 = 0x%02x\n", s, v08_43);
420 TOSHIBA_RBTX4927_SETUP_DPRINTK
421 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
422 ":%s end 0x5c = 0x%02x\n", s, v08_5c);
423 }
424 #endif
425
426 TOSHIBA_RBTX4927_SETUP_DPRINTK
427 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
428 s);
429 }
430
431 }
432
433 register_pci_controller(&tx4927_controller);
434 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
435 "+\n");
436
437 return 0;
438 }
439
440 arch_initcall(tx4927_pcibios_init);
441
442 extern struct resource pci_io_resource;
443 extern struct resource pci_mem_resource;
444
445 void tx4927_pci_setup(void)
446 {
447 static int called = 0;
448 extern unsigned int tx4927_get_mem_size(void);
449
450 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
451
452 mips_memory_upper = tx4927_get_mem_size() << 20;
453 mips_memory_upper += KSEG0;
454 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
455 "0x%08lx=mips_memory_upper\n",
456 mips_memory_upper);
457 mips_pci_io_base = TX4927_PCIIO;
458 mips_pci_io_size = TX4927_PCIIO_SIZE;
459 mips_pci_mem_base = TX4927_PCIMEM;
460 mips_pci_mem_size = TX4927_PCIMEM_SIZE;
461
462 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
463 "0x%08lx=mips_pci_io_base\n",
464 mips_pci_io_base);
465 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
466 "0x%08lx=mips_pci_io_size\n",
467 mips_pci_io_size);
468 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
469 "0x%08lx=mips_pci_mem_base\n",
470 mips_pci_mem_base);
471 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
472 "0x%08lx=mips_pci_mem_size\n",
473 mips_pci_mem_size);
474 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
475 "0x%08lx=pci_io_resource.start\n",
476 pci_io_resource.start);
477 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
478 "0x%08lx=pci_io_resource.end\n",
479 pci_io_resource.end);
480 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
481 "0x%08lx=pci_mem_resource.start\n",
482 pci_mem_resource.start);
483 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
484 "0x%08lx=pci_mem_resource.end\n",
485 pci_mem_resource.end);
486 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
487 "0x%08lx=mips_io_port_base",
488 mips_io_port_base);
489 if (!called) {
490 printk
491 ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
492 toshiba_name,
493 (unsigned short) (tx4927_pcicptr->pciid >> 16),
494 (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
495 (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
496 (!(tx4927_ccfgptr->
497 ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
498 "Internal");
499 called = 1;
500 }
501 printk("%s PCIC --%s PCICLK:",toshiba_name,
502 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
503 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
504 int pciclk = 0;
505 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
506 switch ((unsigned long) tx4927_ccfgptr->
507 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
508 case TX4937_CCFG_PCIDIVMODE_4:
509 pciclk = tx4927_cpu_clock / 4;
510 break;
511 case TX4937_CCFG_PCIDIVMODE_4_5:
512 pciclk = tx4927_cpu_clock * 2 / 9;
513 break;
514 case TX4937_CCFG_PCIDIVMODE_5:
515 pciclk = tx4927_cpu_clock / 5;
516 break;
517 case TX4937_CCFG_PCIDIVMODE_5_5:
518 pciclk = tx4927_cpu_clock * 2 / 11;
519 break;
520 case TX4937_CCFG_PCIDIVMODE_8:
521 pciclk = tx4927_cpu_clock / 8;
522 break;
523 case TX4937_CCFG_PCIDIVMODE_9:
524 pciclk = tx4927_cpu_clock / 9;
525 break;
526 case TX4937_CCFG_PCIDIVMODE_10:
527 pciclk = tx4927_cpu_clock / 10;
528 break;
529 case TX4937_CCFG_PCIDIVMODE_11:
530 pciclk = tx4927_cpu_clock / 11;
531 break;
532 }
533
534 else
535 switch ((unsigned long) tx4927_ccfgptr->
536 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
537 case TX4927_CCFG_PCIDIVMODE_2_5:
538 pciclk = tx4927_cpu_clock * 2 / 5;
539 break;
540 case TX4927_CCFG_PCIDIVMODE_3:
541 pciclk = tx4927_cpu_clock / 3;
542 break;
543 case TX4927_CCFG_PCIDIVMODE_5:
544 pciclk = tx4927_cpu_clock / 5;
545 break;
546 case TX4927_CCFG_PCIDIVMODE_6:
547 pciclk = tx4927_cpu_clock / 6;
548 break;
549 }
550
551 printk("Internal(%dMHz)", pciclk / 1000000);
552 } else {
553 int pciclk = 0;
554 int pciclk_setting = *tx4927_pci_clk_ptr;
555 switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
556 case TX4927_PCI_CLK_33:
557 pciclk = 33333333;
558 break;
559 case TX4927_PCI_CLK_25:
560 pciclk = 25000000;
561 break;
562 case TX4927_PCI_CLK_66:
563 pciclk = 66666666;
564 break;
565 case TX4927_PCI_CLK_50:
566 pciclk = 50000000;
567 break;
568 }
569 printk("External(%dMHz)", pciclk / 1000000);
570 }
571 printk("\n");
572
573
574
575 /* GB->PCI mappings */
576 tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
577 tx4927_pcicptr->g2piogbase = mips_pci_io_base |
578 #ifdef __BIG_ENDIAN
579 TX4927_PCIC_G2PIOGBASE_ECHG
580 #else
581 TX4927_PCIC_G2PIOGBASE_BSDIS
582 #endif
583 ;
584
585 tx4927_pcicptr->g2piopbase = 0;
586
587 tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
588 tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
589 #ifdef __BIG_ENDIAN
590 TX4927_PCIC_G2PMnGBASE_ECHG
591 #else
592 TX4927_PCIC_G2PMnGBASE_BSDIS
593 #endif
594 ;
595 tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
596
597 tx4927_pcicptr->g2pmmask[1] = 0;
598 tx4927_pcicptr->g2pmgbase[1] = 0;
599 tx4927_pcicptr->g2pmpbase[1] = 0;
600 tx4927_pcicptr->g2pmmask[2] = 0;
601 tx4927_pcicptr->g2pmgbase[2] = 0;
602 tx4927_pcicptr->g2pmpbase[2] = 0;
603
604
605 /* PCI->GB mappings (I/O 256B) */
606 tx4927_pcicptr->p2giopbase = 0; /* 256B */
607
608 /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
609 tx4927_pcicptr->p2gm0plbase = 0;
610 tx4927_pcicptr->p2gm0pubase = 0;
611 tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
612 #ifdef __BIG_ENDIAN
613 TX4927_PCIC_P2GMnGBASE_TECHG
614 #else
615 TX4927_PCIC_P2GMnGBASE_TBSDIS
616 #endif
617 ;
618
619 /* PCI->GB mappings (MEM 16MB) -not used */
620 tx4927_pcicptr->p2gm1plbase = 0xffffffff;
621 tx4927_pcicptr->p2gm1pubase = 0xffffffff;
622 tx4927_pcicptr->p2gmgbase[1] = 0;
623
624 /* PCI->GB mappings (MEM 1MB) -not used */
625 tx4927_pcicptr->p2gm2pbase = 0xffffffff;
626 tx4927_pcicptr->p2gmgbase[2] = 0;
627
628
629 /* Enable Initiator Memory 0 Space, I/O Space, Config */
630 tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
631 tx4927_pcicptr->pciccfg |=
632 TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
633 TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
634
635
636 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
637 tx4927_pcicptr->pcicfg1 = 0;
638
639 if (tx4927_pcic_trdyto >= 0) {
640 tx4927_pcicptr->g2ptocnt &= ~0xff;
641 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
642 }
643
644 /* Clear All Local Bus Status */
645 tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
646 /* Enable All Local Bus Interrupts */
647 tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
648 /* Clear All Initiator Status */
649 tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
650 /* Enable All Initiator Interrupts */
651 tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
652 /* Clear All PCI Status Error */
653 tx4927_pcicptr->pcistatus =
654 (tx4927_pcicptr->pcistatus & 0x0000ffff) |
655 (TX4927_PCIC_PCISTATUS_ALL << 16);
656 /* Enable All PCI Status Error Interrupts */
657 tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
658
659 /* PCIC Int => IRC IRQ16 */
660 tx4927_pcicptr->pcicfg2 =
661 (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
662
663 if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
664 /* XXX */
665 } else {
666 /* Reset Bus Arbiter */
667 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
668 /* Enable Bus Arbiter */
669 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
670 }
671
672 tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
673 PCI_COMMAND_MEMORY |
674 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
675
676 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
677 ":pci setup complete:\n");
678 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
679 }
680
681 #endif /* CONFIG_PCI */
682
683 void toshiba_rbtx4927_restart(char *command)
684 {
685 printk(KERN_NOTICE "System Rebooting...\n");
686
687 /* enable the s/w reset register */
688 reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET);
689
690 /* wait for enable to be seen */
691 while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) &
692 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
693
694 /* do a s/w reset */
695 reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET);
696
697 /* do something passive while waiting for reset */
698 local_irq_disable();
699 while (1)
700 asm_wait();
701
702 /* no return */
703 }
704
705
706 void toshiba_rbtx4927_halt(void)
707 {
708 printk(KERN_NOTICE "System Halted\n");
709 local_irq_disable();
710 while (1) {
711 asm_wait();
712 }
713 /* no return */
714 }
715
716 void toshiba_rbtx4927_power_off(void)
717 {
718 toshiba_rbtx4927_halt();
719 /* no return */
720 }
721
722 void __init toshiba_rbtx4927_setup(void)
723 {
724 vu32 cp0_config;
725 char *argptr;
726
727 printk("CPU is %s\n", toshiba_name);
728
729 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
730 "-\n");
731
732 /* f/w leaves this on at startup */
733 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
734 ":Clearing STO_ERL.\n");
735 clear_c0_status(ST0_ERL);
736
737 /* enable caches -- HCP5 does this, pmon does not */
738 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
739 ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
740 cp0_config = read_c0_config();
741 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
742 write_c0_config(cp0_config);
743
744 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
745 {
746 extern void dump_cp0(char *);
747 dump_cp0("toshiba_rbtx4927_early_fw_fixup");
748 }
749 #endif
750
751 /* setup irq stuff */
752 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
753 ":Setting up tx4927 pic.\n");
754 TX4927_WR(0xff1ff604, 0x00000400); /* irq trigger */
755 TX4927_WR(0xff1ff608, 0x00000000); /* irq trigger */
756
757 /* setup serial stuff */
758 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
759 ":Setting up tx4927 sio.\n");
760 TX4927_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
761 TX4927_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
762
763 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
764 "+\n");
765
766 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
767 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
768 ":mips_io_port_base=0x%08lx\n",
769 mips_io_port_base);
770
771 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
772 ":Resource\n");
773 ioport_resource.end = 0xffffffff;
774 iomem_resource.end = 0xffffffff;
775
776 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
777 ":ResetRoutines\n");
778 _machine_restart = toshiba_rbtx4927_restart;
779 _machine_halt = toshiba_rbtx4927_halt;
780 pm_power_off = toshiba_rbtx4927_power_off;
781
782 #ifdef CONFIG_PCI
783
784 /* PCIC */
785 /*
786 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
787 *
788 * For TX4927:
789 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
790 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
791 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
792 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
793 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
794 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
795 *
796 * For TX4937:
797 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
798 * PCIDIVMODE[10] is 0.
799 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
800 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
801 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
802 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
803 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
804 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
805 *
806 */
807 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
808 "ccfg is %lx, PCIDIVMODE is %x\n",
809 (unsigned long) tx4927_ccfgptr->ccfg,
810 (unsigned long) tx4927_ccfgptr->ccfg &
811 (mips_machtype == MACH_TOSHIBA_RBTX4937 ?
812 TX4937_CCFG_PCIDIVMODE_MASK :
813 TX4927_CCFG_PCIDIVMODE_MASK));
814
815 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
816 "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
817 (unsigned long) tx4927_ccfgptr->
818 ccfg & TX4927_CCFG_PCI66,
819 (unsigned long) tx4927_ccfgptr->
820 ccfg & TX4927_CCFG_PCIMIDE,
821 (unsigned long) tx4927_ccfgptr->
822 ccfg & TX4927_CCFG_PCIXARB);
823
824 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
825 switch ((unsigned long)tx4927_ccfgptr->
826 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
827 case TX4937_CCFG_PCIDIVMODE_8:
828 case TX4937_CCFG_PCIDIVMODE_4:
829 tx4927_cpu_clock = 266666666; /* 266MHz */
830 break;
831 case TX4937_CCFG_PCIDIVMODE_9:
832 case TX4937_CCFG_PCIDIVMODE_4_5:
833 tx4927_cpu_clock = 300000000; /* 300MHz */
834 break;
835 default:
836 tx4927_cpu_clock = 333333333; /* 333MHz */
837 }
838 else
839 switch ((unsigned long)tx4927_ccfgptr->
840 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
841 case TX4927_CCFG_PCIDIVMODE_2_5:
842 case TX4927_CCFG_PCIDIVMODE_5:
843 tx4927_cpu_clock = 166666666; /* 166MHz */
844 break;
845 default:
846 tx4927_cpu_clock = 200000000; /* 200MHz */
847 }
848
849 /* CCFG */
850 /* enable Timeout BusError */
851 if (tx4927_ccfg_toeon)
852 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
853
854 tx4927_pci_setup();
855 if (tx4927_using_backplane == 1)
856 printk("backplane board IS installed\n");
857 else
858 printk("No Backplane \n");
859
860 /* this is on ISA bus behind PCI bus, so need PCI up first */
861 #ifdef CONFIG_TOSHIBA_FPCIB0
862 {
863 if (tx4927_using_backplane) {
864 TOSHIBA_RBTX4927_SETUP_DPRINTK
865 (TOSHIBA_RBTX4927_SETUP_SETUP,
866 ":fpcibo=yes\n");
867
868 TOSHIBA_RBTX4927_SETUP_DPRINTK
869 (TOSHIBA_RBTX4927_SETUP_SETUP,
870 ":smsc_fdc37m81x_init()\n");
871 smsc_fdc37m81x_init(0x3f0);
872
873 TOSHIBA_RBTX4927_SETUP_DPRINTK
874 (TOSHIBA_RBTX4927_SETUP_SETUP,
875 ":smsc_fdc37m81x_config_beg()\n");
876 smsc_fdc37m81x_config_beg();
877
878 TOSHIBA_RBTX4927_SETUP_DPRINTK
879 (TOSHIBA_RBTX4927_SETUP_SETUP,
880 ":smsc_fdc37m81x_config_set(KBD)\n");
881 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
882 SMSC_FDC37M81X_KBD);
883 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
884 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
885 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
886 1);
887
888 smsc_fdc37m81x_config_end();
889 TOSHIBA_RBTX4927_SETUP_DPRINTK
890 (TOSHIBA_RBTX4927_SETUP_SETUP,
891 ":smsc_fdc37m81x_config_end()\n");
892 } else {
893 TOSHIBA_RBTX4927_SETUP_DPRINTK
894 (TOSHIBA_RBTX4927_SETUP_SETUP,
895 ":fpcibo=not_found\n");
896 }
897 }
898 #else
899 {
900 TOSHIBA_RBTX4927_SETUP_DPRINTK
901 (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
902 }
903 #endif
904
905 #endif /* CONFIG_PCI */
906
907 #ifdef CONFIG_SERIAL_TXX9
908 {
909 extern int early_serial_txx9_setup(struct uart_port *port);
910 int i;
911 struct uart_port req;
912 for(i = 0; i < 2; i++) {
913 memset(&req, 0, sizeof(req));
914 req.line = i;
915 req.iotype = UPIO_MEM;
916 req.membase = (char *)(0xff1ff300 + i * 0x100);
917 req.mapbase = 0xff1ff300 + i * 0x100;
918 req.irq = 32 + i;
919 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
920 req.uartclk = 50000000;
921 early_serial_txx9_setup(&req);
922 }
923 }
924 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
925 argptr = prom_getcmdline();
926 if (strstr(argptr, "console=") == NULL) {
927 strcat(argptr, " console=ttyS0,38400");
928 }
929 #endif
930 #endif
931
932 #ifdef CONFIG_ROOT_NFS
933 argptr = prom_getcmdline();
934 if (strstr(argptr, "root=") == NULL) {
935 strcat(argptr, " root=/dev/nfs rw");
936 }
937 #endif
938
939
940 #ifdef CONFIG_IP_PNP
941 argptr = prom_getcmdline();
942 if (strstr(argptr, "ip=") == NULL) {
943 strcat(argptr, " ip=any");
944 }
945 #endif
946
947
948 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
949 "+\n");
950 }
951
952 void __init
953 toshiba_rbtx4927_time_init(void)
954 {
955 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
956
957 mips_hpt_frequency = tx4927_cpu_clock / 2;
958
959 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n");
960
961 }
962
963 void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq)
964 {
965 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
966 "-\n");
967 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
968 "+\n");
969 }
970
971 static int __init toshiba_rbtx4927_rtc_init(void)
972 {
973 static struct resource __initdata res = {
974 .start = 0x1c010000,
975 .end = 0x1c010000 + 0x800 - 1,
976 .flags = IORESOURCE_MEM,
977 };
978 struct platform_device *dev =
979 platform_device_register_simple("ds1742", -1, &res, 1);
980 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
981 }
982 device_initcall(toshiba_rbtx4927_rtc_init);
983
984 static int __init rbtx4927_ne_init(void)
985 {
986 static struct resource __initdata res[] = {
987 {
988 .start = RBTX4927_RTL_8019_BASE,
989 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
990 .flags = IORESOURCE_IO,
991 }, {
992 .start = RBTX4927_RTL_8019_IRQ,
993 .flags = IORESOURCE_IRQ,
994 }
995 };
996 struct platform_device *dev =
997 platform_device_register_simple("ne", -1,
998 res, ARRAY_SIZE(res));
999 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
1000 }
1001 device_initcall(rbtx4927_ne_init);
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