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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
[mirror_ubuntu-artful-kernel.git] / arch / mips / tx4927 / toshiba_rbtx4927 / toshiba_rbtx4927_setup.c
1 /*
2 * Toshiba rbtx4927 specific setup
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright 2001-2002 MontaVista Software Inc.
8 *
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * Copyright (C) 2000 RidgeRun, Inc.
11 * Author: RidgeRun, Inc.
12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
13 *
14 * Copyright 2001 MontaVista Software Inc.
15 * Author: jsun@mvista.com or jsun@junsun.net
16 *
17 * Copyright 2002 MontaVista Software Inc.
18 * Author: Michael Pruznick, michael_pruznick@mvista.com
19 *
20 * Copyright (C) 2000-2001 Toshiba Corporation
21 *
22 * Copyright (C) 2004 MontaVista Software Inc.
23 * Author: Manish Lachwani, mlachwani@mvista.com
24 *
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
29 *
30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * You should have received a copy of the GNU General Public License along
42 * with this program; if not, write to the Free Software Foundation, Inc.,
43 * 675 Mass Ave, Cambridge, MA 02139, USA.
44 */
45 #include <linux/init.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
48 #include <linux/mm.h>
49 #include <linux/swap.h>
50 #include <linux/ioport.h>
51 #include <linux/sched.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/timex.h>
55 #include <linux/pm.h>
56 #include <linux/platform_device.h>
57
58 #include <asm/bootinfo.h>
59 #include <asm/page.h>
60 #include <asm/io.h>
61 #include <asm/irq.h>
62 #include <asm/irq_regs.h>
63 #include <asm/processor.h>
64 #include <asm/reboot.h>
65 #include <asm/time.h>
66 #include <linux/bootmem.h>
67 #include <linux/blkdev.h>
68 #ifdef CONFIG_TOSHIBA_FPCIB0
69 #include <asm/tx4927/smsc_fdc37m81x.h>
70 #endif
71 #include <asm/tx4927/toshiba_rbtx4927.h>
72 #ifdef CONFIG_PCI
73 #include <asm/tx4927/tx4927_pci.h>
74 #endif
75 #ifdef CONFIG_BLK_DEV_IDEPCI
76 #include <linux/hdreg.h>
77 #include <linux/ide.h>
78 #endif
79 #ifdef CONFIG_SERIAL_TXX9
80 #include <linux/tty.h>
81 #include <linux/serial.h>
82 #include <linux/serial_core.h>
83 #endif
84
85 #undef TOSHIBA_RBTX4927_SETUP_DEBUG
86
87 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
88 #define TOSHIBA_RBTX4927_SETUP_NONE 0x00000000
89
90 #define TOSHIBA_RBTX4927_SETUP_INFO ( 1 << 0 )
91 #define TOSHIBA_RBTX4927_SETUP_WARN ( 1 << 1 )
92 #define TOSHIBA_RBTX4927_SETUP_EROR ( 1 << 2 )
93
94 #define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
95 #define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
96 #define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
97 #define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 << 6 )
98 #define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
99 #define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
100 #define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
101 #define TOSHIBA_RBTX4927_SETUP_PCI66 ( 1 << 10 )
102
103 #define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
104 #endif
105
106 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
107 static const u32 toshiba_rbtx4927_setup_debug_flag =
108 (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
109 TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
110 TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
111 TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
112 | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
113 TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
114 #endif
115
116 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
117 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
118 if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
119 { \
120 char tmp[100]; \
121 sprintf( tmp, str ); \
122 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
123 }
124 #else
125 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...)
126 #endif
127
128 /* These functions are used for rebooting or halting the machine*/
129 extern void toshiba_rbtx4927_restart(char *command);
130 extern void toshiba_rbtx4927_halt(void);
131 extern void toshiba_rbtx4927_power_off(void);
132
133 int tx4927_using_backplane = 0;
134
135 extern void gt64120_time_init(void);
136 extern void toshiba_rbtx4927_irq_setup(void);
137
138 char *prom_getcmdline(void);
139
140 #ifdef CONFIG_PCI
141 #undef TX4927_SUPPORT_COMMAND_IO
142 #undef TX4927_SUPPORT_PCI_66
143 int tx4927_cpu_clock = 100000000; /* 100MHz */
144 unsigned long mips_pci_io_base;
145 unsigned long mips_pci_io_size;
146 unsigned long mips_pci_mem_base;
147 unsigned long mips_pci_mem_size;
148 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
149 unsigned long mips_pci_io_pciaddr = 0;
150 unsigned long mips_memory_upper;
151 static int tx4927_ccfg_toeon = 1;
152 static int tx4927_pcic_trdyto = 0; /* default: disabled */
153 unsigned long tx4927_ce_base[8];
154 void tx4927_reset_pci_pcic(void);
155 int tx4927_pci66 = 0; /* 0:auto */
156 #endif
157
158 char *toshiba_name = "";
159
160 #ifdef CONFIG_PCI
161 extern struct pci_controller tx4927_controller;
162
163 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
164 int top_bus, int busnr, int devfn)
165 {
166 static struct pci_dev dev;
167 static struct pci_bus bus;
168
169 dev.sysdata = (void *)hose;
170 dev.devfn = devfn;
171 bus.number = busnr;
172 bus.ops = hose->pci_ops;
173 bus.parent = NULL;
174 dev.bus = &bus;
175
176 return &dev;
177 }
178
179 #define EARLY_PCI_OP(rw, size, type) \
180 static int early_##rw##_config_##size(struct pci_controller *hose, \
181 int top_bus, int bus, int devfn, int offset, type value) \
182 { \
183 return pci_##rw##_config_##size( \
184 fake_pci_dev(hose, top_bus, bus, devfn), \
185 offset, value); \
186 }
187
188 EARLY_PCI_OP(read, byte, u8 *)
189 EARLY_PCI_OP(read, dword, u32 *)
190 EARLY_PCI_OP(write, byte, u8)
191 EARLY_PCI_OP(write, dword, u32)
192
193 static int __init tx4927_pcibios_init(void)
194 {
195 unsigned int id;
196 u32 pci_devfn;
197 int devfn_start = 0;
198 int devfn_stop = 0xff;
199 int busno = 0; /* One bus on the Toshiba */
200 struct pci_controller *hose = &tx4927_controller;
201
202 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
203 "-\n");
204
205 for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
206 early_read_config_dword(hose, busno, busno, pci_devfn,
207 PCI_VENDOR_ID, &id);
208
209 if (id == 0xffffffff) {
210 continue;
211 }
212
213 if (id == 0x94601055) {
214 u8 v08_64;
215 u32 v32_b0;
216 u8 v08_e1;
217 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
218 char *s = " sb/isa --";
219 #endif
220
221 TOSHIBA_RBTX4927_SETUP_DPRINTK
222 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
223 s);
224
225 early_read_config_byte(hose, busno, busno,
226 pci_devfn, 0x64, &v08_64);
227 early_read_config_dword(hose, busno, busno,
228 pci_devfn, 0xb0, &v32_b0);
229 early_read_config_byte(hose, busno, busno,
230 pci_devfn, 0xe1, &v08_e1);
231
232 TOSHIBA_RBTX4927_SETUP_DPRINTK
233 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
234 ":%s beg 0x64 = 0x%02x\n", s, v08_64);
235 TOSHIBA_RBTX4927_SETUP_DPRINTK
236 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
237 ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
238 TOSHIBA_RBTX4927_SETUP_DPRINTK
239 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
240 ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
241
242 /* serial irq control */
243 v08_64 = 0xd0;
244
245 /* serial irq pin */
246 v32_b0 |= 0x00010000;
247
248 /* ide irq on isa14 */
249 v08_e1 &= 0xf0;
250 v08_e1 |= 0x0d;
251
252 TOSHIBA_RBTX4927_SETUP_DPRINTK
253 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
254 ":%s mid 0x64 = 0x%02x\n", s, v08_64);
255 TOSHIBA_RBTX4927_SETUP_DPRINTK
256 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
257 ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
258 TOSHIBA_RBTX4927_SETUP_DPRINTK
259 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
260 ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
261
262 early_write_config_byte(hose, busno, busno,
263 pci_devfn, 0x64, v08_64);
264 early_write_config_dword(hose, busno, busno,
265 pci_devfn, 0xb0, v32_b0);
266 early_write_config_byte(hose, busno, busno,
267 pci_devfn, 0xe1, v08_e1);
268
269 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
270 {
271 early_read_config_byte(hose, busno, busno,
272 pci_devfn, 0x64,
273 &v08_64);
274 early_read_config_dword(hose, busno, busno,
275 pci_devfn, 0xb0,
276 &v32_b0);
277 early_read_config_byte(hose, busno, busno,
278 pci_devfn, 0xe1,
279 &v08_e1);
280
281 TOSHIBA_RBTX4927_SETUP_DPRINTK
282 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
283 ":%s end 0x64 = 0x%02x\n", s, v08_64);
284 TOSHIBA_RBTX4927_SETUP_DPRINTK
285 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
286 ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
287 TOSHIBA_RBTX4927_SETUP_DPRINTK
288 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
289 ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
290 }
291 #endif
292
293 TOSHIBA_RBTX4927_SETUP_DPRINTK
294 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
295 s);
296 }
297
298 if (id == 0x91301055) {
299 u8 v08_04;
300 u8 v08_09;
301 u8 v08_41;
302 u8 v08_43;
303 u8 v08_5c;
304 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
305 char *s = " sb/ide --";
306 #endif
307
308 TOSHIBA_RBTX4927_SETUP_DPRINTK
309 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
310 s);
311
312 early_read_config_byte(hose, busno, busno,
313 pci_devfn, 0x04, &v08_04);
314 early_read_config_byte(hose, busno, busno,
315 pci_devfn, 0x09, &v08_09);
316 early_read_config_byte(hose, busno, busno,
317 pci_devfn, 0x41, &v08_41);
318 early_read_config_byte(hose, busno, busno,
319 pci_devfn, 0x43, &v08_43);
320 early_read_config_byte(hose, busno, busno,
321 pci_devfn, 0x5c, &v08_5c);
322
323 TOSHIBA_RBTX4927_SETUP_DPRINTK
324 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
325 ":%s beg 0x04 = 0x%02x\n", s, v08_04);
326 TOSHIBA_RBTX4927_SETUP_DPRINTK
327 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
328 ":%s beg 0x09 = 0x%02x\n", s, v08_09);
329 TOSHIBA_RBTX4927_SETUP_DPRINTK
330 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
331 ":%s beg 0x41 = 0x%02x\n", s, v08_41);
332 TOSHIBA_RBTX4927_SETUP_DPRINTK
333 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
334 ":%s beg 0x43 = 0x%02x\n", s, v08_43);
335 TOSHIBA_RBTX4927_SETUP_DPRINTK
336 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
337 ":%s beg 0x5c = 0x%02x\n", s, v08_5c);
338
339 /* enable ide master/io */
340 v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
341
342 /* enable ide native mode */
343 v08_09 |= 0x05;
344
345 /* enable primary ide */
346 v08_41 |= 0x80;
347
348 /* enable secondary ide */
349 v08_43 |= 0x80;
350
351 /*
352 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
353 *
354 * This line of code is intended to provide the user with a work
355 * around solution to the anomalies cited in SMSC's anomaly sheet
356 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
357 *
358 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
359 */
360 v08_5c |= 0x01;
361
362 TOSHIBA_RBTX4927_SETUP_DPRINTK
363 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
364 ":%s mid 0x04 = 0x%02x\n", s, v08_04);
365 TOSHIBA_RBTX4927_SETUP_DPRINTK
366 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
367 ":%s mid 0x09 = 0x%02x\n", s, v08_09);
368 TOSHIBA_RBTX4927_SETUP_DPRINTK
369 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
370 ":%s mid 0x41 = 0x%02x\n", s, v08_41);
371 TOSHIBA_RBTX4927_SETUP_DPRINTK
372 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
373 ":%s mid 0x43 = 0x%02x\n", s, v08_43);
374 TOSHIBA_RBTX4927_SETUP_DPRINTK
375 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
376 ":%s mid 0x5c = 0x%02x\n", s, v08_5c);
377
378 early_write_config_byte(hose, busno, busno,
379 pci_devfn, 0x5c, v08_5c);
380 early_write_config_byte(hose, busno, busno,
381 pci_devfn, 0x04, v08_04);
382 early_write_config_byte(hose, busno, busno,
383 pci_devfn, 0x09, v08_09);
384 early_write_config_byte(hose, busno, busno,
385 pci_devfn, 0x41, v08_41);
386 early_write_config_byte(hose, busno, busno,
387 pci_devfn, 0x43, v08_43);
388
389 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
390 {
391 early_read_config_byte(hose, busno, busno,
392 pci_devfn, 0x04,
393 &v08_04);
394 early_read_config_byte(hose, busno, busno,
395 pci_devfn, 0x09,
396 &v08_09);
397 early_read_config_byte(hose, busno, busno,
398 pci_devfn, 0x41,
399 &v08_41);
400 early_read_config_byte(hose, busno, busno,
401 pci_devfn, 0x43,
402 &v08_43);
403 early_read_config_byte(hose, busno, busno,
404 pci_devfn, 0x5c,
405 &v08_5c);
406
407 TOSHIBA_RBTX4927_SETUP_DPRINTK
408 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
409 ":%s end 0x04 = 0x%02x\n", s, v08_04);
410 TOSHIBA_RBTX4927_SETUP_DPRINTK
411 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
412 ":%s end 0x09 = 0x%02x\n", s, v08_09);
413 TOSHIBA_RBTX4927_SETUP_DPRINTK
414 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
415 ":%s end 0x41 = 0x%02x\n", s, v08_41);
416 TOSHIBA_RBTX4927_SETUP_DPRINTK
417 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
418 ":%s end 0x43 = 0x%02x\n", s, v08_43);
419 TOSHIBA_RBTX4927_SETUP_DPRINTK
420 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
421 ":%s end 0x5c = 0x%02x\n", s, v08_5c);
422 }
423 #endif
424
425 TOSHIBA_RBTX4927_SETUP_DPRINTK
426 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
427 s);
428 }
429
430 }
431
432 register_pci_controller(&tx4927_controller);
433 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
434 "+\n");
435
436 return 0;
437 }
438
439 arch_initcall(tx4927_pcibios_init);
440
441 extern struct resource pci_io_resource;
442 extern struct resource pci_mem_resource;
443
444 void __init tx4927_pci_setup(void)
445 {
446 static int called = 0;
447 extern unsigned int tx4927_get_mem_size(void);
448
449 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
450
451 mips_memory_upper = tx4927_get_mem_size() << 20;
452 mips_memory_upper += KSEG0;
453 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
454 "0x%08lx=mips_memory_upper\n",
455 mips_memory_upper);
456 mips_pci_io_base = TX4927_PCIIO;
457 mips_pci_io_size = TX4927_PCIIO_SIZE;
458 mips_pci_mem_base = TX4927_PCIMEM;
459 mips_pci_mem_size = TX4927_PCIMEM_SIZE;
460
461 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
462 "0x%08lx=mips_pci_io_base\n",
463 mips_pci_io_base);
464 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
465 "0x%08lx=mips_pci_io_size\n",
466 mips_pci_io_size);
467 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
468 "0x%08lx=mips_pci_mem_base\n",
469 mips_pci_mem_base);
470 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
471 "0x%08lx=mips_pci_mem_size\n",
472 mips_pci_mem_size);
473 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
474 "0x%08lx=pci_io_resource.start\n",
475 pci_io_resource.start);
476 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
477 "0x%08lx=pci_io_resource.end\n",
478 pci_io_resource.end);
479 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
480 "0x%08lx=pci_mem_resource.start\n",
481 pci_mem_resource.start);
482 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
483 "0x%08lx=pci_mem_resource.end\n",
484 pci_mem_resource.end);
485 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
486 "0x%08lx=mips_io_port_base",
487 mips_io_port_base);
488 if (!called) {
489 printk
490 ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
491 toshiba_name,
492 (unsigned short) (tx4927_pcicptr->pciid >> 16),
493 (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
494 (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
495 (!(tx4927_ccfgptr->
496 ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
497 "Internal");
498 called = 1;
499 }
500 printk("%s PCIC --%s PCICLK:",toshiba_name,
501 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
502 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
503 int pciclk = 0;
504 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
505 switch ((unsigned long) tx4927_ccfgptr->
506 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
507 case TX4937_CCFG_PCIDIVMODE_4:
508 pciclk = tx4927_cpu_clock / 4;
509 break;
510 case TX4937_CCFG_PCIDIVMODE_4_5:
511 pciclk = tx4927_cpu_clock * 2 / 9;
512 break;
513 case TX4937_CCFG_PCIDIVMODE_5:
514 pciclk = tx4927_cpu_clock / 5;
515 break;
516 case TX4937_CCFG_PCIDIVMODE_5_5:
517 pciclk = tx4927_cpu_clock * 2 / 11;
518 break;
519 case TX4937_CCFG_PCIDIVMODE_8:
520 pciclk = tx4927_cpu_clock / 8;
521 break;
522 case TX4937_CCFG_PCIDIVMODE_9:
523 pciclk = tx4927_cpu_clock / 9;
524 break;
525 case TX4937_CCFG_PCIDIVMODE_10:
526 pciclk = tx4927_cpu_clock / 10;
527 break;
528 case TX4937_CCFG_PCIDIVMODE_11:
529 pciclk = tx4927_cpu_clock / 11;
530 break;
531 }
532
533 else
534 switch ((unsigned long) tx4927_ccfgptr->
535 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
536 case TX4927_CCFG_PCIDIVMODE_2_5:
537 pciclk = tx4927_cpu_clock * 2 / 5;
538 break;
539 case TX4927_CCFG_PCIDIVMODE_3:
540 pciclk = tx4927_cpu_clock / 3;
541 break;
542 case TX4927_CCFG_PCIDIVMODE_5:
543 pciclk = tx4927_cpu_clock / 5;
544 break;
545 case TX4927_CCFG_PCIDIVMODE_6:
546 pciclk = tx4927_cpu_clock / 6;
547 break;
548 }
549
550 printk("Internal(%dMHz)", pciclk / 1000000);
551 } else {
552 int pciclk = 0;
553 int pciclk_setting = *tx4927_pci_clk_ptr;
554 switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
555 case TX4927_PCI_CLK_33:
556 pciclk = 33333333;
557 break;
558 case TX4927_PCI_CLK_25:
559 pciclk = 25000000;
560 break;
561 case TX4927_PCI_CLK_66:
562 pciclk = 66666666;
563 break;
564 case TX4927_PCI_CLK_50:
565 pciclk = 50000000;
566 break;
567 }
568 printk("External(%dMHz)", pciclk / 1000000);
569 }
570 printk("\n");
571
572
573
574 /* GB->PCI mappings */
575 tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
576 tx4927_pcicptr->g2piogbase = mips_pci_io_base |
577 #ifdef __BIG_ENDIAN
578 TX4927_PCIC_G2PIOGBASE_ECHG
579 #else
580 TX4927_PCIC_G2PIOGBASE_BSDIS
581 #endif
582 ;
583
584 tx4927_pcicptr->g2piopbase = 0;
585
586 tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
587 tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
588 #ifdef __BIG_ENDIAN
589 TX4927_PCIC_G2PMnGBASE_ECHG
590 #else
591 TX4927_PCIC_G2PMnGBASE_BSDIS
592 #endif
593 ;
594 tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
595
596 tx4927_pcicptr->g2pmmask[1] = 0;
597 tx4927_pcicptr->g2pmgbase[1] = 0;
598 tx4927_pcicptr->g2pmpbase[1] = 0;
599 tx4927_pcicptr->g2pmmask[2] = 0;
600 tx4927_pcicptr->g2pmgbase[2] = 0;
601 tx4927_pcicptr->g2pmpbase[2] = 0;
602
603
604 /* PCI->GB mappings (I/O 256B) */
605 tx4927_pcicptr->p2giopbase = 0; /* 256B */
606
607 /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
608 tx4927_pcicptr->p2gm0plbase = 0;
609 tx4927_pcicptr->p2gm0pubase = 0;
610 tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
611 #ifdef __BIG_ENDIAN
612 TX4927_PCIC_P2GMnGBASE_TECHG
613 #else
614 TX4927_PCIC_P2GMnGBASE_TBSDIS
615 #endif
616 ;
617
618 /* PCI->GB mappings (MEM 16MB) -not used */
619 tx4927_pcicptr->p2gm1plbase = 0xffffffff;
620 tx4927_pcicptr->p2gm1pubase = 0xffffffff;
621 tx4927_pcicptr->p2gmgbase[1] = 0;
622
623 /* PCI->GB mappings (MEM 1MB) -not used */
624 tx4927_pcicptr->p2gm2pbase = 0xffffffff;
625 tx4927_pcicptr->p2gmgbase[2] = 0;
626
627
628 /* Enable Initiator Memory 0 Space, I/O Space, Config */
629 tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
630 tx4927_pcicptr->pciccfg |=
631 TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
632 TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
633
634
635 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
636 tx4927_pcicptr->pcicfg1 = 0;
637
638 if (tx4927_pcic_trdyto >= 0) {
639 tx4927_pcicptr->g2ptocnt &= ~0xff;
640 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
641 }
642
643 /* Clear All Local Bus Status */
644 tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
645 /* Enable All Local Bus Interrupts */
646 tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
647 /* Clear All Initiator Status */
648 tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
649 /* Enable All Initiator Interrupts */
650 tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
651 /* Clear All PCI Status Error */
652 tx4927_pcicptr->pcistatus =
653 (tx4927_pcicptr->pcistatus & 0x0000ffff) |
654 (TX4927_PCIC_PCISTATUS_ALL << 16);
655 /* Enable All PCI Status Error Interrupts */
656 tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
657
658 /* PCIC Int => IRC IRQ16 */
659 tx4927_pcicptr->pcicfg2 =
660 (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
661
662 if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
663 /* XXX */
664 } else {
665 /* Reset Bus Arbiter */
666 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
667 /* Enable Bus Arbiter */
668 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
669 }
670
671 tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
672 PCI_COMMAND_MEMORY |
673 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
674
675 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
676 ":pci setup complete:\n");
677 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
678 }
679
680 #endif /* CONFIG_PCI */
681
682 void toshiba_rbtx4927_restart(char *command)
683 {
684 printk(KERN_NOTICE "System Rebooting...\n");
685
686 /* enable the s/w reset register */
687 reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET);
688
689 /* wait for enable to be seen */
690 while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) &
691 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
692
693 /* do a s/w reset */
694 reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET);
695
696 /* do something passive while waiting for reset */
697 local_irq_disable();
698 while (1)
699 asm_wait();
700
701 /* no return */
702 }
703
704
705 void toshiba_rbtx4927_halt(void)
706 {
707 printk(KERN_NOTICE "System Halted\n");
708 local_irq_disable();
709 while (1) {
710 asm_wait();
711 }
712 /* no return */
713 }
714
715 void toshiba_rbtx4927_power_off(void)
716 {
717 toshiba_rbtx4927_halt();
718 /* no return */
719 }
720
721 void __init toshiba_rbtx4927_setup(void)
722 {
723 vu32 cp0_config;
724 char *argptr;
725
726 printk("CPU is %s\n", toshiba_name);
727
728 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
729 "-\n");
730
731 /* f/w leaves this on at startup */
732 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
733 ":Clearing STO_ERL.\n");
734 clear_c0_status(ST0_ERL);
735
736 /* enable caches -- HCP5 does this, pmon does not */
737 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
738 ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
739 cp0_config = read_c0_config();
740 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
741 write_c0_config(cp0_config);
742
743 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
744 {
745 extern void dump_cp0(char *);
746 dump_cp0("toshiba_rbtx4927_early_fw_fixup");
747 }
748 #endif
749
750 /* setup serial stuff */
751 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
752 ":Setting up tx4927 sio.\n");
753 TX4927_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
754 TX4927_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
755
756 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
757 "+\n");
758
759 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
760 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
761 ":mips_io_port_base=0x%08lx\n",
762 mips_io_port_base);
763
764 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
765 ":Resource\n");
766 ioport_resource.end = 0xffffffff;
767 iomem_resource.end = 0xffffffff;
768
769 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
770 ":ResetRoutines\n");
771 _machine_restart = toshiba_rbtx4927_restart;
772 _machine_halt = toshiba_rbtx4927_halt;
773 pm_power_off = toshiba_rbtx4927_power_off;
774
775 #ifdef CONFIG_PCI
776
777 /* PCIC */
778 /*
779 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
780 *
781 * For TX4927:
782 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
783 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
784 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
785 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
786 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
787 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
788 *
789 * For TX4937:
790 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
791 * PCIDIVMODE[10] is 0.
792 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
793 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
794 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
795 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
796 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
797 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
798 *
799 */
800 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
801 "ccfg is %lx, PCIDIVMODE is %x\n",
802 (unsigned long) tx4927_ccfgptr->ccfg,
803 (unsigned long) tx4927_ccfgptr->ccfg &
804 (mips_machtype == MACH_TOSHIBA_RBTX4937 ?
805 TX4937_CCFG_PCIDIVMODE_MASK :
806 TX4927_CCFG_PCIDIVMODE_MASK));
807
808 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
809 "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
810 (unsigned long) tx4927_ccfgptr->
811 ccfg & TX4927_CCFG_PCI66,
812 (unsigned long) tx4927_ccfgptr->
813 ccfg & TX4927_CCFG_PCIMIDE,
814 (unsigned long) tx4927_ccfgptr->
815 ccfg & TX4927_CCFG_PCIXARB);
816
817 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
818 switch ((unsigned long)tx4927_ccfgptr->
819 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
820 case TX4937_CCFG_PCIDIVMODE_8:
821 case TX4937_CCFG_PCIDIVMODE_4:
822 tx4927_cpu_clock = 266666666; /* 266MHz */
823 break;
824 case TX4937_CCFG_PCIDIVMODE_9:
825 case TX4937_CCFG_PCIDIVMODE_4_5:
826 tx4927_cpu_clock = 300000000; /* 300MHz */
827 break;
828 default:
829 tx4927_cpu_clock = 333333333; /* 333MHz */
830 }
831 else
832 switch ((unsigned long)tx4927_ccfgptr->
833 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
834 case TX4927_CCFG_PCIDIVMODE_2_5:
835 case TX4927_CCFG_PCIDIVMODE_5:
836 tx4927_cpu_clock = 166666666; /* 166MHz */
837 break;
838 default:
839 tx4927_cpu_clock = 200000000; /* 200MHz */
840 }
841
842 /* CCFG */
843 /* enable Timeout BusError */
844 if (tx4927_ccfg_toeon)
845 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
846
847 tx4927_pci_setup();
848 if (tx4927_using_backplane == 1)
849 printk("backplane board IS installed\n");
850 else
851 printk("No Backplane \n");
852
853 /* this is on ISA bus behind PCI bus, so need PCI up first */
854 #ifdef CONFIG_TOSHIBA_FPCIB0
855 {
856 if (tx4927_using_backplane) {
857 TOSHIBA_RBTX4927_SETUP_DPRINTK
858 (TOSHIBA_RBTX4927_SETUP_SETUP,
859 ":fpcibo=yes\n");
860
861 TOSHIBA_RBTX4927_SETUP_DPRINTK
862 (TOSHIBA_RBTX4927_SETUP_SETUP,
863 ":smsc_fdc37m81x_init()\n");
864 smsc_fdc37m81x_init(0x3f0);
865
866 TOSHIBA_RBTX4927_SETUP_DPRINTK
867 (TOSHIBA_RBTX4927_SETUP_SETUP,
868 ":smsc_fdc37m81x_config_beg()\n");
869 smsc_fdc37m81x_config_beg();
870
871 TOSHIBA_RBTX4927_SETUP_DPRINTK
872 (TOSHIBA_RBTX4927_SETUP_SETUP,
873 ":smsc_fdc37m81x_config_set(KBD)\n");
874 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
875 SMSC_FDC37M81X_KBD);
876 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
877 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
878 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
879 1);
880
881 smsc_fdc37m81x_config_end();
882 TOSHIBA_RBTX4927_SETUP_DPRINTK
883 (TOSHIBA_RBTX4927_SETUP_SETUP,
884 ":smsc_fdc37m81x_config_end()\n");
885 } else {
886 TOSHIBA_RBTX4927_SETUP_DPRINTK
887 (TOSHIBA_RBTX4927_SETUP_SETUP,
888 ":fpcibo=not_found\n");
889 }
890 }
891 #else
892 {
893 TOSHIBA_RBTX4927_SETUP_DPRINTK
894 (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
895 }
896 #endif
897
898 #endif /* CONFIG_PCI */
899
900 #ifdef CONFIG_SERIAL_TXX9
901 {
902 extern int early_serial_txx9_setup(struct uart_port *port);
903 int i;
904 struct uart_port req;
905 for(i = 0; i < 2; i++) {
906 memset(&req, 0, sizeof(req));
907 req.line = i;
908 req.iotype = UPIO_MEM;
909 req.membase = (char *)(0xff1ff300 + i * 0x100);
910 req.mapbase = 0xff1ff300 + i * 0x100;
911 req.irq = TX4927_IRQ_PIC_BEG + 8 + i;
912 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
913 req.uartclk = 50000000;
914 early_serial_txx9_setup(&req);
915 }
916 }
917 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
918 argptr = prom_getcmdline();
919 if (strstr(argptr, "console=") == NULL) {
920 strcat(argptr, " console=ttyS0,38400");
921 }
922 #endif
923 #endif
924
925 #ifdef CONFIG_ROOT_NFS
926 argptr = prom_getcmdline();
927 if (strstr(argptr, "root=") == NULL) {
928 strcat(argptr, " root=/dev/nfs rw");
929 }
930 #endif
931
932
933 #ifdef CONFIG_IP_PNP
934 argptr = prom_getcmdline();
935 if (strstr(argptr, "ip=") == NULL) {
936 strcat(argptr, " ip=any");
937 }
938 #endif
939
940
941 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
942 "+\n");
943 }
944
945 void __init
946 toshiba_rbtx4927_time_init(void)
947 {
948 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
949
950 mips_hpt_frequency = tx4927_cpu_clock / 2;
951
952 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n");
953
954 }
955
956 void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq)
957 {
958 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
959 "-\n");
960 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
961 "+\n");
962 }
963
964 static int __init toshiba_rbtx4927_rtc_init(void)
965 {
966 static struct resource __initdata res = {
967 .start = 0x1c010000,
968 .end = 0x1c010000 + 0x800 - 1,
969 .flags = IORESOURCE_MEM,
970 };
971 struct platform_device *dev =
972 platform_device_register_simple("ds1742", -1, &res, 1);
973 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
974 }
975 device_initcall(toshiba_rbtx4927_rtc_init);
976
977 static int __init rbtx4927_ne_init(void)
978 {
979 static struct resource __initdata res[] = {
980 {
981 .start = RBTX4927_RTL_8019_BASE,
982 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
983 .flags = IORESOURCE_IO,
984 }, {
985 .start = RBTX4927_RTL_8019_IRQ,
986 .flags = IORESOURCE_IRQ,
987 }
988 };
989 struct platform_device *dev =
990 platform_device_register_simple("ne", -1,
991 res, ARRAY_SIZE(res));
992 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
993 }
994 device_initcall(rbtx4927_ne_init);
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