arch/mips/txx9/generic/pci.c

   1 /*
   2  * linux/arch/mips/txx9/pci.c
   3  *
   4  * Based on linux/arch/mips/txx9/rbtx4927/setup.c,
   5  *          linux/arch/mips/txx9/rbtx4938/setup.c,
   6  *          and RBTX49xx patch from CELF patch archive.
   7  *
   8  * Copyright 2001-2005 MontaVista Software Inc.
   9  * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
  10  * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file "COPYING" in the main directory of this archive
  14  * for more details.
  15  */
  16 #include <linux/delay.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/io.h>
  19 #include <asm/txx9/generic.h>
  20 #include <asm/txx9/pci.h>
  21 #ifdef CONFIG_TOSHIBA_FPCIB0
  22 #include <linux/interrupt.h>
  23 #include <linux/slab.h>
  24 #include <asm/i8259.h>
  25 #include <asm/txx9/smsc_fdc37m81x.h>
  26 #endif
  27
  28 static int __init
  29 early_read_config_word(struct pci_controller *hose,
  30                        int top_bus, int bus, int devfn, int offset, u16 *value)
  31 {
  32         struct pci_bus fake_bus;
  33
  34         fake_bus.number = bus;
  35         fake_bus.sysdata = hose;
  36         fake_bus.ops = hose->pci_ops;
  37
  38         if (bus != top_bus)
  39                 /* Fake a parent bus structure. */
  40                 fake_bus.parent = &fake_bus;
  41         else
  42                 fake_bus.parent = NULL;
  43
  44         return pci_bus_read_config_word(&fake_bus, devfn, offset, value);
  45 }
  46
  47 int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
  48                             int current_bus)
  49 {
  50         u32 pci_devfn;
  51         unsigned short vid;
  52         int cap66 = -1;
  53         u16 stat;
  54
  55         /* It seems SLC90E66 needs some time after PCI reset... */
  56         mdelay(80);
  57
  58         pr_info("PCI: Checking 66MHz capabilities...\n");
  59
  60         for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
  61                 if (PCI_FUNC(pci_devfn))
  62                         continue;
  63                 if (early_read_config_word(hose, top_bus, current_bus,
  64                                            pci_devfn, PCI_VENDOR_ID, &vid) !=
  65                     PCIBIOS_SUCCESSFUL)
  66                         continue;
  67                 if (vid == 0xffff)
  68                         continue;
  69
  70                 /* check 66MHz capability */
  71                 if (cap66 < 0)
  72                         cap66 = 1;
  73                 if (cap66) {
  74                         early_read_config_word(hose, top_bus, current_bus,
  75                                                pci_devfn, PCI_STATUS, &stat);
  76                         if (!(stat & PCI_STATUS_66MHZ)) {
  77                                 pr_debug("PCI: %02x:%02x not 66MHz capable.\n",
  78                                          current_bus, pci_devfn);
  79                                 cap66 = 0;
  80                                 break;
  81                         }
  82                 }
  83         }
  84         return cap66 > 0;
  85 }
  86
  87 static struct resource primary_pci_mem_res[2] = {
  88         { .name = "PCI MEM" },
  89         { .name = "PCI MMIO" },
  90 };
  91 static struct resource primary_pci_io_res = { .name = "PCI IO" };
  92 struct pci_controller txx9_primary_pcic = {
  93         .mem_resource = &primary_pci_mem_res[0],
  94         .io_resource = &primary_pci_io_res,
  95 };
  96
  97 #ifdef CONFIG_64BIT
  98 int txx9_pci_mem_high __initdata = 1;
  99 #else
 100 int txx9_pci_mem_high __initdata;
 101 #endif
 102
 103 /*
 104  * allocate pci_controller and resources.
 105  * mem_base, io_base: physical address.  0 for auto assignment.
 106  * mem_size and io_size means max size on auto assignment.
 107  * pcic must be &txx9_primary_pcic or NULL.
 108  */
 109 struct pci_controller *__init
 110 txx9_alloc_pci_controller(struct pci_controller *pcic,
 111                           unsigned long mem_base, unsigned long mem_size,
 112                           unsigned long io_base, unsigned long io_size)
 113 {
 114         struct pcic {
 115                 struct pci_controller c;
 116                 struct resource r_mem[2];
 117                 struct resource r_io;
 118         } *new = NULL;
 119         int min_size = 0x10000;
 120
 121         if (!pcic) {
 122                 new = kzalloc(sizeof(*new), GFP_KERNEL);
 123                 if (!new)
 124                         return NULL;
 125                 new->r_mem[0].name = "PCI mem";
 126                 new->r_mem[1].name = "PCI mmio";
 127                 new->r_io.name = "PCI io";
 128                 new->c.mem_resource = new->r_mem;
 129                 new->c.io_resource = &new->r_io;
 130                 pcic = &new->c;
 131         } else
 132                 BUG_ON(pcic != &txx9_primary_pcic);
 133         pcic->io_resource->flags = IORESOURCE_IO;
 134
 135         /*
 136          * for auto assignment, first search a (big) region for PCI
 137          * MEM, then search a region for PCI IO.
 138          */
 139         if (mem_base) {
 140                 pcic->mem_resource[0].start = mem_base;
 141                 pcic->mem_resource[0].end = mem_base + mem_size - 1;
 142                 if (request_resource(&iomem_resource, &pcic->mem_resource[0]))
 143                         goto free_and_exit;
 144         } else {
 145                 unsigned long min = 0, max = 0x20000000; /* low 512MB */
 146                 if (!mem_size) {
 147                         /* default size for auto assignment */
 148                         if (txx9_pci_mem_high)
 149                                 mem_size = 0x20000000;  /* mem:512M(max) */
 150                         else
 151                                 mem_size = 0x08000000;  /* mem:128M(max) */
 152                 }
 153                 if (txx9_pci_mem_high) {
 154                         min = 0x20000000;
 155                         max = 0xe0000000;
 156                 }
 157                 /* search free region for PCI MEM */
 158                 for (; mem_size >= min_size; mem_size /= 2) {
 159                         if (allocate_resource(&iomem_resource,
 160                                               &pcic->mem_resource[0],
 161                                               mem_size, min, max,
 162                                               mem_size, NULL, NULL) == 0)
 163                                 break;
 164                 }
 165                 if (mem_size < min_size)
 166                         goto free_and_exit;
 167         }
 168
 169         pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 170         if (io_base) {
 171                 pcic->mem_resource[1].start = io_base;
 172                 pcic->mem_resource[1].end = io_base + io_size - 1;
 173                 if (request_resource(&iomem_resource, &pcic->mem_resource[1]))
 174                         goto release_and_exit;
 175         } else {
 176                 if (!io_size)
 177                         /* default size for auto assignment */
 178                         io_size = 0x01000000;   /* io:16M(max) */
 179                 /* search free region for PCI IO in low 512MB */
 180                 for (; io_size >= min_size; io_size /= 2) {
 181                         if (allocate_resource(&iomem_resource,
 182                                               &pcic->mem_resource[1],
 183                                               io_size, 0, 0x20000000,
 184                                               io_size, NULL, NULL) == 0)
 185                                 break;
 186                 }
 187                 if (io_size < min_size)
 188                         goto release_and_exit;
 189                 io_base = pcic->mem_resource[1].start;
 190         }
 191
 192         pcic->mem_resource[0].flags = IORESOURCE_MEM;
 193         if (pcic == &txx9_primary_pcic &&
 194             mips_io_port_base == (unsigned long)-1) {
 195                 /* map ioport 0 to PCI I/O space address 0 */
 196                 set_io_port_base(IO_BASE + pcic->mem_resource[1].start);
 197                 pcic->io_resource->start = 0;
 198                 pcic->io_offset = 0;    /* busaddr == ioaddr */
 199                 pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start;
 200         } else {
 201                 /* physaddr to ioaddr */
 202                 pcic->io_resource->start =
 203                         io_base - (mips_io_port_base - IO_BASE);
 204                 pcic->io_offset = io_base - (mips_io_port_base - IO_BASE);
 205                 pcic->io_map_base = mips_io_port_base;
 206         }
 207         pcic->io_resource->end = pcic->io_resource->start + io_size - 1;
 208
 209         pcic->mem_offset = 0;   /* busaddr == physaddr */
 210
 211         pr_info("PCI: IO %pR MEM %pR\n", &pcic->mem_resource[1],
 212                 &pcic->mem_resource[0]);
 213
 214         /* register_pci_controller() will request MEM resource */
 215         release_resource(&pcic->mem_resource[0]);
 216         return pcic;
 217  release_and_exit:
 218         release_resource(&pcic->mem_resource[0]);
 219  free_and_exit:
 220         kfree(new);
 221         pr_err("PCI: Failed to allocate resources.\n");
 222         return NULL;
 223 }
 224
 225 static int __init
 226 txx9_arch_pci_init(void)
 227 {
 228         PCIBIOS_MIN_IO = 0x8000;        /* reseve legacy I/O space */
 229         return 0;
 230 }
 231 arch_initcall(txx9_arch_pci_init);
 232
 233 /* IRQ/IDSEL mapping */
 234 int txx9_pci_option =
 235 #ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT
 236         TXX9_PCI_OPT_PICMG |
 237 #endif
 238         TXX9_PCI_OPT_CLK_AUTO;
 239
 240 enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT;
 241
 242 #ifdef CONFIG_TOSHIBA_FPCIB0
 243 static irqreturn_t i8259_interrupt(int irq, void *dev_id)
 244 {
 245         int isairq;
 246
 247         isairq = i8259_irq();
 248         if (unlikely(isairq <= I8259A_IRQ_BASE))
 249                 return IRQ_NONE;
 250         generic_handle_irq(isairq);
 251         return IRQ_HANDLED;
 252 }
 253
 254 static int txx9_i8259_irq_setup(int irq)
 255 {
 256         int err;
 257
 258         init_i8259_irqs();
 259         err = request_irq(irq, &i8259_interrupt, IRQF_SHARED,
 260                           "cascade(i8259)", (void *)(long)irq);
 261         if (!err)
 262                 pr_info("PCI-ISA bridge PIC (irq %d)\n", irq);
 263         return err;
 264 }
 265
 266 static void __ref quirk_slc90e66_bridge(struct pci_dev *dev)
 267 {
 268         int irq;        /* PCI/ISA Bridge interrupt */
 269         u8 reg_64;
 270         u32 reg_b0;
 271         u8 reg_e1;
 272         irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */
 273         if (!irq)
 274                 return;
 275         txx9_i8259_irq_setup(irq);
 276         pci_read_config_byte(dev, 0x64, &reg_64);
 277         pci_read_config_dword(dev, 0xb0, &reg_b0);
 278         pci_read_config_byte(dev, 0xe1, &reg_e1);
 279         /* serial irq control */
 280         reg_64 = 0xd0;
 281         /* serial irq pin */
 282         reg_b0 |= 0x00010000;
 283         /* ide irq on isa14 */
 284         reg_e1 &= 0xf0;
 285         reg_e1 |= 0x0d;
 286         pci_write_config_byte(dev, 0x64, reg_64);
 287         pci_write_config_dword(dev, 0xb0, reg_b0);
 288         pci_write_config_byte(dev, 0xe1, reg_e1);
 289
 290         smsc_fdc37m81x_init(0x3f0);
 291         smsc_fdc37m81x_config_beg();
 292         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
 293                                   SMSC_FDC37M81X_KBD);
 294         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
 295         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
 296         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
 297                                   1);
 298         smsc_fdc37m81x_config_end();
 299 }
 300
 301 static void quirk_slc90e66_ide(struct pci_dev *dev)
 302 {
 303         unsigned char dat;
 304         int regs[2] = {0x41, 0x43};
 305         int i;
 306
 307         /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
 308         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
 309         pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
 310         pr_info("PCI: %s: IRQ %02x", pci_name(dev), dat);
 311         /* enable SMSC SLC90E66 IDE */
 312         for (i = 0; i < ARRAY_SIZE(regs); i++) {
 313                 pci_read_config_byte(dev, regs[i], &dat);
 314                 pci_write_config_byte(dev, regs[i], dat | 0x80);
 315                 pci_read_config_byte(dev, regs[i], &dat);
 316                 pr_cont(" IDETIM%d %02x", i, dat);
 317         }
 318         pci_read_config_byte(dev, 0x5c, &dat);
 319         /*
 320          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 321          *
 322          * This line of code is intended to provide the user with a work
 323          * around solution to the anomalies cited in SMSC's anomaly sheet
 324          * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
 325          *
 326          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 327          */
 328         dat |= 0x01;
 329         pci_write_config_byte(dev, 0x5c, dat);
 330         pci_read_config_byte(dev, 0x5c, &dat);
 331         pr_cont(" REG5C %02x\n", dat);
 332 }
 333 #endif /* CONFIG_TOSHIBA_FPCIB0 */
 334
 335 static void tc35815_fixup(struct pci_dev *dev)
 336 {
 337         /* This device may have PM registers but not they are not supported. */
 338         if (dev->pm_cap) {
 339                 dev_info(&dev->dev, "PM disabled\n");
 340                 dev->pm_cap = 0;
 341         }
 342 }
 343
 344 static void final_fixup(struct pci_dev *dev)
 345 {
 346         unsigned char bist;
 347
 348         /* Do build-in self test */
 349         if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL &&
 350             (bist & PCI_BIST_CAPABLE)) {
 351                 unsigned long timeout;
 352                 pci_set_power_state(dev, PCI_D0);
 353                 pr_info("PCI: %s BIST...", pci_name(dev));
 354                 pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
 355                 timeout = jiffies + HZ * 2;     /* timeout after 2 sec */
 356                 do {
 357                         pci_read_config_byte(dev, PCI_BIST, &bist);
 358                         if (time_after(jiffies, timeout))
 359                                 break;
 360                 } while (bist & PCI_BIST_START);
 361                 if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
 362                         pr_cont("failed. (0x%x)\n", bist);
 363                 else
 364                         pr_cont("OK.\n");
 365         }
 366 }
 367
 368 #ifdef CONFIG_TOSHIBA_FPCIB0
 369 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
 370 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
 371         quirk_slc90e66_bridge);
 372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
 373         quirk_slc90e66_ide);
 374 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
 375         quirk_slc90e66_ide);
 376 #endif
 377 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
 378                         PCI_DEVICE_ID_TOSHIBA_TC35815_NWU, tc35815_fixup);
 379 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
 380                         PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939, tc35815_fixup);
 381 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
 382 DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
 383
 384 int pcibios_plat_dev_init(struct pci_dev *dev)
 385 {
 386         return 0;
 387 }
 388
 389 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 390 {
 391         return txx9_board_vec->pci_map_irq(dev, slot, pin);
 392 }
 393
 394 char * (*txx9_board_pcibios_setup)(char *str) __initdata;
 395
 396 char *__init txx9_pcibios_setup(char *str)
 397 {
 398         if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
 399                 return NULL;
 400         if (!strcmp(str, "picmg")) {
 401                 /* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX
 402                    (5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */
 403                 txx9_pci_option |= TXX9_PCI_OPT_PICMG;
 404                 return NULL;
 405         } else if (!strcmp(str, "nopicmg")) {
 406                 /* non-PICMG compliant backplane (TOSHIBA
 407                    RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */
 408                 txx9_pci_option &= ~TXX9_PCI_OPT_PICMG;
 409                 return NULL;
 410         } else if (!strncmp(str, "clk=", 4)) {
 411                 char *val = str + 4;
 412                 txx9_pci_option &= ~TXX9_PCI_OPT_CLK_MASK;
 413                 if (strcmp(val, "33") == 0)
 414                         txx9_pci_option |= TXX9_PCI_OPT_CLK_33;
 415                 else if (strcmp(val, "66") == 0)
 416                         txx9_pci_option |= TXX9_PCI_OPT_CLK_66;
 417                 else /* "auto" */
 418                         txx9_pci_option |= TXX9_PCI_OPT_CLK_AUTO;
 419                 return NULL;
 420         } else if (!strncmp(str, "err=", 4)) {
 421                 if (!strcmp(str + 4, "panic"))
 422                         txx9_pci_err_action = TXX9_PCI_ERR_PANIC;
 423                 else if (!strcmp(str + 4, "ignore"))
 424                         txx9_pci_err_action = TXX9_PCI_ERR_IGNORE;
 425                 return NULL;
 426         }
 427         return str;
 428 }