arch/mips/txx9/generic/setup_tx4927.c

   1 /*
   2  * TX4927 setup routines
   3  * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
   4  *          and RBTX49xx patch from CELF patch archive.
   5  *
   6  * 2003-2005 (c) MontaVista Software, Inc.
   7  * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/ioport.h>
  15 #include <linux/delay.h>
  16 #include <linux/param.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/mtd/physmap.h>
  19 #include <asm/reboot.h>
  20 #include <asm/traps.h>
  21 #include <asm/txx9irq.h>
  22 #include <asm/txx9tmr.h>
  23 #include <asm/txx9pio.h>
  24 #include <asm/txx9/generic.h>
  25 #include <asm/txx9/dmac.h>
  26 #include <asm/txx9/tx4927.h>
  27
  28 static void __init tx4927_wdr_init(void)
  29 {
  30         /* report watchdog reset status */
  31         if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDRST)
  32                 pr_warn("Watchdog reset detected at 0x%lx\n",
  33                         read_c0_errorepc());
  34         /* clear WatchDogReset (W1C) */
  35         tx4927_ccfg_set(TX4927_CCFG_WDRST);
  36         /* do reset on watchdog */
  37         tx4927_ccfg_set(TX4927_CCFG_WR);
  38 }
  39
  40 void __init tx4927_wdt_init(void)
  41 {
  42         txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
  43 }
  44
  45 static void tx4927_machine_restart(char *command)
  46 {
  47         local_irq_disable();
  48         pr_emerg("Rebooting (with %s watchdog reset)...\n",
  49                  (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDREXEN) ?
  50                  "external" : "internal");
  51         /* clear watchdog status */
  52         tx4927_ccfg_set(TX4927_CCFG_WDRST);     /* W1C */
  53         txx9_wdt_now(TX4927_TMR_REG(2) & 0xfffffffffULL);
  54         while (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDRST))
  55                 ;
  56         mdelay(10);
  57         if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDREXEN) {
  58                 pr_emerg("Rebooting (with internal watchdog reset)...\n");
  59                 /* External WDRST failed.  Do internal watchdog reset */
  60                 tx4927_ccfg_clear(TX4927_CCFG_WDREXEN);
  61         }
  62         /* fallback */
  63         (*_machine_halt)();
  64 }
  65
  66 void show_registers(struct pt_regs *regs);
  67 static int tx4927_be_handler(struct pt_regs *regs, int is_fixup)
  68 {
  69         int data = regs->cp0_cause & 4;
  70         console_verbose();
  71         pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc);
  72         pr_err("ccfg:%llx, toea:%llx\n",
  73                (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
  74                (unsigned long long)____raw_readq(&tx4927_ccfgptr->toea));
  75 #ifdef CONFIG_PCI
  76         tx4927_report_pcic_status();
  77 #endif
  78         show_registers(regs);
  79         panic("BusError!");
  80 }
  81 static void __init tx4927_be_init(void)
  82 {
  83         board_be_handler = tx4927_be_handler;
  84 }
  85
  86 static struct resource tx4927_sdram_resource[4];
  87
  88 void __init tx4927_setup(void)
  89 {
  90         int i;
  91         __u32 divmode;
  92         unsigned int cpuclk = 0;
  93         u64 ccfg;
  94
  95         txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
  96                           TX4927_REG_SIZE);
  97         set_c0_config(TX49_CONF_CWFON);
  98
  99         /* SDRAMC,EBUSC are configured by PROM */
 100         for (i = 0; i < 8; i++) {
 101                 if (!(TX4927_EBUSC_CR(i) & 0x8))
 102                         continue;       /* disabled */
 103                 txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i);
 104                 txx9_ce_res[i].end =
 105                         txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1;
 106                 request_resource(&iomem_resource, &txx9_ce_res[i]);
 107         }
 108
 109         /* clocks */
 110         ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg);
 111         if (txx9_master_clock) {
 112                 /* calculate gbus_clock and cpu_clock from master_clock */
 113                 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
 114                 switch (divmode) {
 115                 case TX4927_CCFG_DIVMODE_8:
 116                 case TX4927_CCFG_DIVMODE_10:
 117                 case TX4927_CCFG_DIVMODE_12:
 118                 case TX4927_CCFG_DIVMODE_16:
 119                         txx9_gbus_clock = txx9_master_clock * 4; break;
 120                 default:
 121                         txx9_gbus_clock = txx9_master_clock;
 122                 }
 123                 switch (divmode) {
 124                 case TX4927_CCFG_DIVMODE_2:
 125                 case TX4927_CCFG_DIVMODE_8:
 126                         cpuclk = txx9_gbus_clock * 2; break;
 127                 case TX4927_CCFG_DIVMODE_2_5:
 128                 case TX4927_CCFG_DIVMODE_10:
 129                         cpuclk = txx9_gbus_clock * 5 / 2; break;
 130                 case TX4927_CCFG_DIVMODE_3:
 131                 case TX4927_CCFG_DIVMODE_12:
 132                         cpuclk = txx9_gbus_clock * 3; break;
 133                 case TX4927_CCFG_DIVMODE_4:
 134                 case TX4927_CCFG_DIVMODE_16:
 135                         cpuclk = txx9_gbus_clock * 4; break;
 136                 }
 137                 txx9_cpu_clock = cpuclk;
 138         } else {
 139                 if (txx9_cpu_clock == 0)
 140                         txx9_cpu_clock = 200000000;     /* 200MHz */
 141                 /* calculate gbus_clock and master_clock from cpu_clock */
 142                 cpuclk = txx9_cpu_clock;
 143                 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
 144                 switch (divmode) {
 145                 case TX4927_CCFG_DIVMODE_2:
 146                 case TX4927_CCFG_DIVMODE_8:
 147                         txx9_gbus_clock = cpuclk / 2; break;
 148                 case TX4927_CCFG_DIVMODE_2_5:
 149                 case TX4927_CCFG_DIVMODE_10:
 150                         txx9_gbus_clock = cpuclk * 2 / 5; break;
 151                 case TX4927_CCFG_DIVMODE_3:
 152                 case TX4927_CCFG_DIVMODE_12:
 153                         txx9_gbus_clock = cpuclk / 3; break;
 154                 case TX4927_CCFG_DIVMODE_4:
 155                 case TX4927_CCFG_DIVMODE_16:
 156                         txx9_gbus_clock = cpuclk / 4; break;
 157                 }
 158                 switch (divmode) {
 159                 case TX4927_CCFG_DIVMODE_8:
 160                 case TX4927_CCFG_DIVMODE_10:
 161                 case TX4927_CCFG_DIVMODE_12:
 162                 case TX4927_CCFG_DIVMODE_16:
 163                         txx9_master_clock = txx9_gbus_clock / 4; break;
 164                 default:
 165                         txx9_master_clock = txx9_gbus_clock;
 166                 }
 167         }
 168         /* change default value to udelay/mdelay take reasonable time */
 169         loops_per_jiffy = txx9_cpu_clock / HZ / 2;
 170
 171         /* CCFG */
 172         tx4927_wdr_init();
 173         /* clear BusErrorOnWrite flag (W1C) */
 174         tx4927_ccfg_set(TX4927_CCFG_BEOW);
 175         /* enable Timeout BusError */
 176         if (txx9_ccfg_toeon)
 177                 tx4927_ccfg_set(TX4927_CCFG_TOE);
 178
 179         /* DMA selection */
 180         txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL);
 181
 182         /* Use external clock for external arbiter */
 183         if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
 184                 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);
 185
 186         printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
 187                txx9_pcode_str,
 188                (cpuclk + 500000) / 1000000,
 189                (txx9_master_clock + 500000) / 1000000,
 190                (__u32)____raw_readq(&tx4927_ccfgptr->crir),
 191                (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
 192                (unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));
 193
 194         printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
 195         for (i = 0; i < 4; i++) {
 196                 __u64 cr = TX4927_SDRAMC_CR(i);
 197                 unsigned long base, size;
 198                 if (!((__u32)cr & 0x00000400))
 199                         continue;       /* disabled */
 200                 base = (unsigned long)(cr >> 49) << 21;
 201                 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
 202                 printk(" CR%d:%016llx", i, (unsigned long long)cr);
 203                 tx4927_sdram_resource[i].name = "SDRAM";
 204                 tx4927_sdram_resource[i].start = base;
 205                 tx4927_sdram_resource[i].end = base + size - 1;
 206                 tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
 207                 request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
 208         }
 209         printk(" TR:%09llx\n",
 210                (unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));
 211
 212         /* TMR */
 213         /* disable all timers */
 214         for (i = 0; i < TX4927_NR_TMR; i++)
 215                 txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL);
 216
 217         /* PIO */
 218         __raw_writel(0, &tx4927_pioptr->maskcpu);
 219         __raw_writel(0, &tx4927_pioptr->maskext);
 220
 221         _machine_restart = tx4927_machine_restart;
 222         board_be_init = tx4927_be_init;
 223 }
 224
 225 void __init tx4927_time_init(unsigned int tmrnr)
 226 {
 227         if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
 228                 txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL,
 229                                      TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr),
 230                                      TXX9_IMCLK);
 231 }
 232
 233 void __init tx4927_sio_init(unsigned int sclk, unsigned int cts_mask)
 234 {
 235         int i;
 236
 237         for (i = 0; i < 2; i++)
 238                 txx9_sio_init(TX4927_SIO_REG(i) & 0xfffffffffULL,
 239                               TXX9_IRQ_BASE + TX4927_IR_SIO(i),
 240                               i, sclk, (1 << i) & cts_mask);
 241 }
 242
 243 void __init tx4927_mtd_init(int ch)
 244 {
 245         struct physmap_flash_data pdata = {
 246                 .width = TX4927_EBUSC_WIDTH(ch) / 8,
 247         };
 248         unsigned long start = txx9_ce_res[ch].start;
 249         unsigned long size = txx9_ce_res[ch].end - start + 1;
 250
 251         if (!(TX4927_EBUSC_CR(ch) & 0x8))
 252                 return; /* disabled */
 253         txx9_physmap_flash_init(ch, start, size, &pdata);
 254 }
 255
 256 void __init tx4927_dmac_init(int memcpy_chan)
 257 {
 258         struct txx9dmac_platform_data plat_data = {
 259                 .memcpy_chan = memcpy_chan,
 260                 .have_64bit_regs = true,
 261         };
 262
 263         txx9_dmac_init(0, TX4927_DMA_REG & 0xfffffffffULL,
 264                        TXX9_IRQ_BASE + TX4927_IR_DMA(0), &plat_data);
 265 }
 266
 267 void __init tx4927_aclc_init(unsigned int dma_chan_out,
 268                              unsigned int dma_chan_in)
 269 {
 270         u64 pcfg = __raw_readq(&tx4927_ccfgptr->pcfg);
 271         __u64 dmasel_mask = 0, dmasel = 0;
 272         unsigned long flags;
 273
 274         if (!(pcfg & TX4927_PCFG_SEL2))
 275                 return;
 276         /* setup DMASEL (playback:ACLC ch0, capture:ACLC ch1) */
 277         switch (dma_chan_out) {
 278         case 0:
 279                 dmasel_mask |= TX4927_PCFG_DMASEL0_MASK;
 280                 dmasel |= TX4927_PCFG_DMASEL0_ACL0;
 281                 break;
 282         case 2:
 283                 dmasel_mask |= TX4927_PCFG_DMASEL2_MASK;
 284                 dmasel |= TX4927_PCFG_DMASEL2_ACL0;
 285                 break;
 286         default:
 287                 return;
 288         }
 289         switch (dma_chan_in) {
 290         case 1:
 291                 dmasel_mask |= TX4927_PCFG_DMASEL1_MASK;
 292                 dmasel |= TX4927_PCFG_DMASEL1_ACL1;
 293                 break;
 294         case 3:
 295                 dmasel_mask |= TX4927_PCFG_DMASEL3_MASK;
 296                 dmasel |= TX4927_PCFG_DMASEL3_ACL1;
 297                 break;
 298         default:
 299                 return;
 300         }
 301         local_irq_save(flags);
 302         txx9_clear64(&tx4927_ccfgptr->pcfg, dmasel_mask);
 303         txx9_set64(&tx4927_ccfgptr->pcfg, dmasel);
 304         local_irq_restore(flags);
 305         txx9_aclc_init(TX4927_ACLC_REG & 0xfffffffffULL,
 306                        TXX9_IRQ_BASE + TX4927_IR_ACLC,
 307                        0, dma_chan_out, dma_chan_in);
 308 }
 309
 310 static void __init tx4927_stop_unused_modules(void)
 311 {
 312         __u64 pcfg, rst = 0, ckd = 0;
 313         char buf[128];
 314
 315         buf[0] = '\0';
 316         local_irq_disable();
 317         pcfg = ____raw_readq(&tx4927_ccfgptr->pcfg);
 318         if (!(pcfg & TX4927_PCFG_SEL2)) {
 319                 rst |= TX4927_CLKCTR_ACLRST;
 320                 ckd |= TX4927_CLKCTR_ACLCKD;
 321                 strcat(buf, " ACLC");
 322         }
 323         if (rst | ckd) {
 324                 txx9_set64(&tx4927_ccfgptr->clkctr, rst);
 325                 txx9_set64(&tx4927_ccfgptr->clkctr, ckd);
 326         }
 327         local_irq_enable();
 328         if (buf[0])
 329                 pr_info("%s: stop%s\n", txx9_pcode_str, buf);
 330 }
 331
 332 static int __init tx4927_late_init(void)
 333 {
 334         if (txx9_pcode != 0x4927)
 335                 return -ENODEV;
 336         tx4927_stop_unused_modules();
 337         return 0;
 338 }
 339 late_initcall(tx4927_late_init);