arch/mips/txx9/jmr3927/setup.c

   1 /*
   2  *  This program is free software; you can redistribute  it and/or modify it
   3  *  under  the terms of  the GNU General  Public License as published by the
   4  *  Free Software Foundation;  either version 2 of the  License, or (at your
   5  *  option) any later version.
   6  *
   7  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
   8  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
   9  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  10  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  11  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  12  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  13  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  14  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  15  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  16  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  17  *
  18  *  You should have received a copy of the  GNU General Public License along
  19  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  20  *  675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  * Copyright 2001 MontaVista Software Inc.
  23  * Author: MontaVista Software, Inc.
  24  *              ahennessy@mvista.com
  25  *
  26  * Copyright (C) 2000-2001 Toshiba Corporation
  27  * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
  28  */
  29
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/types.h>
  33 #include <linux/ioport.h>
  34 #include <linux/delay.h>
  35 #include <linux/pm.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/gpio.h>
  38 #ifdef CONFIG_SERIAL_TXX9
  39 #include <linux/serial_core.h>
  40 #endif
  41 #include <asm/txx9tmr.h>
  42 #include <asm/txx9pio.h>
  43 #include <asm/reboot.h>
  44 #include <asm/txx9/generic.h>
  45 #include <asm/txx9/pci.h>
  46 #include <asm/txx9/jmr3927.h>
  47 #include <asm/mipsregs.h>
  48
  49 extern void puts(const char *cp);
  50
  51 /* don't enable - see errata */
  52 static int jmr3927_ccfg_toeon;
  53
  54 static inline void do_reset(void)
  55 {
  56 #if 1   /* Resetting PCI bus */
  57         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
  58         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
  59         (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR);       /* flush WB */
  60         mdelay(1);
  61         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
  62 #endif
  63         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
  64 }
  65
  66 static void jmr3927_machine_restart(char *command)
  67 {
  68         local_irq_disable();
  69         puts("Rebooting...");
  70         do_reset();
  71 }
  72
  73 static void jmr3927_machine_halt(void)
  74 {
  75         puts("JMR-TX3927 halted.\n");
  76         while (1);
  77 }
  78
  79 static void jmr3927_machine_power_off(void)
  80 {
  81         puts("JMR-TX3927 halted. Please turn off the power.\n");
  82         while (1);
  83 }
  84
  85 static void __init jmr3927_time_init(void)
  86 {
  87         txx9_clockevent_init(TX3927_TMR_REG(0),
  88                              TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0),
  89                              JMR3927_IMCLK);
  90         txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK);
  91 }
  92
  93 #define DO_WRITE_THROUGH
  94 #define DO_ENABLE_CACHE
  95
  96 static void jmr3927_board_init(void);
  97
  98 static void __init jmr3927_mem_setup(void)
  99 {
 100         char *argptr;
 101
 102         set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
 103
 104         _machine_restart = jmr3927_machine_restart;
 105         _machine_halt = jmr3927_machine_halt;
 106         pm_power_off = jmr3927_machine_power_off;
 107
 108         /* Reboot on panic */
 109         panic_timeout = 180;
 110
 111         /* cache setup */
 112         {
 113                 unsigned int conf;
 114 #ifdef DO_ENABLE_CACHE
 115                 int mips_ic_disable = 0, mips_dc_disable = 0;
 116 #else
 117                 int mips_ic_disable = 1, mips_dc_disable = 1;
 118 #endif
 119 #ifdef DO_WRITE_THROUGH
 120                 int mips_config_cwfon = 0;
 121                 int mips_config_wbon = 0;
 122 #else
 123                 int mips_config_cwfon = 1;
 124                 int mips_config_wbon = 1;
 125 #endif
 126
 127                 conf = read_c0_conf();
 128                 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
 129                 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
 130                 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
 131                 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
 132                 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
 133
 134                 write_c0_conf(conf);
 135                 write_c0_cache(0);
 136         }
 137
 138         /* initialize board */
 139         jmr3927_board_init();
 140
 141         argptr = prom_getcmdline();
 142
 143         if ((argptr = strstr(argptr, "toeon")) != NULL)
 144                 jmr3927_ccfg_toeon = 1;
 145         argptr = prom_getcmdline();
 146         if ((argptr = strstr(argptr, "ip=")) == NULL) {
 147                 argptr = prom_getcmdline();
 148                 strcat(argptr, " ip=bootp");
 149         }
 150
 151 #ifdef CONFIG_SERIAL_TXX9
 152         {
 153                 extern int early_serial_txx9_setup(struct uart_port *port);
 154                 int i;
 155                 struct uart_port req;
 156                 for(i = 0; i < 2; i++) {
 157                         memset(&req, 0, sizeof(req));
 158                         req.line = i;
 159                         req.iotype = UPIO_MEM;
 160                         req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i);
 161                         req.mapbase = TX3927_SIO_REG(i);
 162                         req.irq = i == 0 ?
 163                                 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
 164                         if (i == 0)
 165                                 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 166                         req.uartclk = JMR3927_IMCLK;
 167                         early_serial_txx9_setup(&req);
 168                 }
 169         }
 170 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 171         argptr = prom_getcmdline();
 172         if ((argptr = strstr(argptr, "console=")) == NULL) {
 173                 argptr = prom_getcmdline();
 174                 strcat(argptr, " console=ttyS1,115200");
 175         }
 176 #endif
 177 #endif
 178 }
 179
 180 static void tx3927_setup(void);
 181
 182 static void __init jmr3927_pci_setup(void)
 183 {
 184 #ifdef CONFIG_PCI
 185         int extarb = !(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB);
 186         struct pci_controller *c;
 187
 188         c = txx9_alloc_pci_controller(&txx9_primary_pcic,
 189                                       JMR3927_PCIMEM, JMR3927_PCIMEM_SIZE,
 190                                       JMR3927_PCIIO, JMR3927_PCIIO_SIZE);
 191         register_pci_controller(c);
 192         if (!extarb) {
 193                 /* Reset PCI Bus */
 194                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 195                 udelay(100);
 196                 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
 197                                     JMR3927_IOC_RESET_ADDR);
 198                 udelay(100);
 199                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 200         }
 201         tx3927_pcic_setup(c, JMR3927_SDRAM_SIZE, extarb);
 202 #endif /* CONFIG_PCI */
 203 }
 204
 205 static void __init jmr3927_board_init(void)
 206 {
 207         tx3927_setup();
 208         jmr3927_pci_setup();
 209
 210         /* SIO0 DTR on */
 211         jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
 212
 213         jmr3927_led_set(0);
 214
 215         printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
 216                jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
 217                jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
 218                jmr3927_dipsw1(), jmr3927_dipsw2(),
 219                jmr3927_dipsw3(), jmr3927_dipsw4());
 220 }
 221
 222 static void __init tx3927_setup(void)
 223 {
 224         int i;
 225
 226         txx9_cpu_clock = JMR3927_CORECLK;
 227         txx9_gbus_clock = JMR3927_GBUSCLK;
 228         /* SDRAMC are configured by PROM */
 229
 230         /* ROMC */
 231         tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
 232         tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
 233         tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
 234         tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
 235
 236         /* CCFG */
 237         /* enable Timeout BusError */
 238         if (jmr3927_ccfg_toeon)
 239                 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
 240
 241         /* clear BusErrorOnWrite flag */
 242         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
 243         /* Disable PCI snoop */
 244         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
 245         /* do reset on watchdog */
 246         tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;
 247
 248 #ifdef DO_WRITE_THROUGH
 249         /* Enable PCI SNOOP - with write through only */
 250         tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
 251 #endif
 252
 253         /* Pin selection */
 254         tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
 255         tx3927_ccfgptr->pcfg |=
 256                 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
 257                 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
 258
 259         printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
 260                tx3927_ccfgptr->crir,
 261                tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
 262
 263         /* TMR */
 264         for (i = 0; i < TX3927_NR_TMR; i++)
 265                 txx9_tmr_init(TX3927_TMR_REG(i));
 266
 267         /* DMA */
 268         tx3927_dmaptr->mcr = 0;
 269         for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
 270                 /* reset channel */
 271                 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
 272                 tx3927_dmaptr->ch[i].ccr = 0;
 273         }
 274         /* enable DMA */
 275 #ifdef __BIG_ENDIAN
 276         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
 277 #else
 278         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
 279 #endif
 280
 281         /* PIO */
 282         /* PIO[15:12] connected to LEDs */
 283         __raw_writel(0x0000f000, &tx3927_pioptr->dir);
 284         __raw_writel(0, &tx3927_pioptr->maskcpu);
 285         __raw_writel(0, &tx3927_pioptr->maskext);
 286         txx9_gpio_init(TX3927_PIO_REG, 0, 16);
 287         gpio_request(11, "dipsw1");
 288         gpio_request(10, "dipsw2");
 289         {
 290                 unsigned int conf;
 291
 292         conf = read_c0_conf();
 293                if (!(conf & TX39_CONF_ICE))
 294                        printk("TX3927 I-Cache disabled.\n");
 295                if (!(conf & TX39_CONF_DCE))
 296                        printk("TX3927 D-Cache disabled.\n");
 297                else if (!(conf & TX39_CONF_WBON))
 298                        printk("TX3927 D-Cache WriteThrough.\n");
 299                else if (!(conf & TX39_CONF_CWFON))
 300                        printk("TX3927 D-Cache WriteBack.\n");
 301                else
 302                        printk("TX3927 D-Cache WriteBack (CWF) .\n");
 303         }
 304 }
 305
 306 /* This trick makes rtc-ds1742 driver usable as is. */
 307 static unsigned long jmr3927_swizzle_addr_b(unsigned long port)
 308 {
 309         if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR)
 310                 return port;
 311         port = (port & 0xffff0000) | (port & 0x7fff << 1);
 312 #ifdef __BIG_ENDIAN
 313         return port;
 314 #else
 315         return port | 1;
 316 #endif
 317 }
 318
 319 static int __init jmr3927_rtc_init(void)
 320 {
 321         static struct resource __initdata res = {
 322                 .start  = JMR3927_IOC_NVRAMB_ADDR - IO_BASE,
 323                 .end    = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1,
 324                 .flags  = IORESOURCE_MEM,
 325         };
 326         struct platform_device *dev;
 327         dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1);
 328         return IS_ERR(dev) ? PTR_ERR(dev) : 0;
 329 }
 330
 331 /* Watchdog support */
 332
 333 static int __init txx9_wdt_init(unsigned long base)
 334 {
 335         struct resource res = {
 336                 .start  = base,
 337                 .end    = base + 0x100 - 1,
 338                 .flags  = IORESOURCE_MEM,
 339         };
 340         struct platform_device *dev =
 341                 platform_device_register_simple("txx9wdt", -1, &res, 1);
 342         return IS_ERR(dev) ? PTR_ERR(dev) : 0;
 343 }
 344
 345 static int __init jmr3927_wdt_init(void)
 346 {
 347         return txx9_wdt_init(TX3927_TMR_REG(2));
 348 }
 349
 350 static void __init jmr3927_device_init(void)
 351 {
 352         __swizzle_addr_b = jmr3927_swizzle_addr_b;
 353         jmr3927_rtc_init();
 354         jmr3927_wdt_init();
 355 }
 356
 357 struct txx9_board_vec jmr3927_vec __initdata = {
 358         .system = "Toshiba JMR_TX3927",
 359         .prom_init = jmr3927_prom_init,
 360         .mem_setup = jmr3927_mem_setup,
 361         .irq_setup = jmr3927_irq_setup,
 362         .time_init = jmr3927_time_init,
 363         .device_init = jmr3927_device_init,
 364 #ifdef CONFIG_PCI
 365         .pci_map_irq = jmr3927_pci_map_irq,
 366 #endif
 367 };