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[mirror_ubuntu-bionic-kernel.git] / arch / mips / txx9 / rbtx4927 / setup.c
1 /*
2 * Toshiba rbtx4927 specific setup
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright 2001-2002 MontaVista Software Inc.
8 *
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * Copyright (C) 2000 RidgeRun, Inc.
11 * Author: RidgeRun, Inc.
12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
13 *
14 * Copyright 2001 MontaVista Software Inc.
15 * Author: jsun@mvista.com or jsun@junsun.net
16 *
17 * Copyright 2002 MontaVista Software Inc.
18 * Author: Michael Pruznick, michael_pruznick@mvista.com
19 *
20 * Copyright (C) 2000-2001 Toshiba Corporation
21 *
22 * Copyright (C) 2004 MontaVista Software Inc.
23 * Author: Manish Lachwani, mlachwani@mvista.com
24 *
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
29 *
30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * You should have received a copy of the GNU General Public License along
42 * with this program; if not, write to the Free Software Foundation, Inc.,
43 * 675 Mass Ave, Cambridge, MA 02139, USA.
44 */
45 #include <linux/init.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
48 #include <linux/ioport.h>
49 #include <linux/interrupt.h>
50 #include <linux/pci.h>
51 #include <linux/pm.h>
52 #include <linux/platform_device.h>
53 #include <linux/clk.h>
54
55 #include <asm/bootinfo.h>
56 #include <asm/io.h>
57 #include <asm/processor.h>
58 #include <asm/reboot.h>
59 #include <asm/time.h>
60 #include <asm/txx9tmr.h>
61 #ifdef CONFIG_TOSHIBA_FPCIB0
62 #include <asm/txx9/smsc_fdc37m81x.h>
63 #endif
64 #include <asm/txx9/rbtx4927.h>
65 #ifdef CONFIG_SERIAL_TXX9
66 #include <linux/serial_core.h>
67 #endif
68
69 /* These functions are used for rebooting or halting the machine*/
70 extern void toshiba_rbtx4927_restart(char *command);
71 extern void toshiba_rbtx4927_halt(void);
72 extern void toshiba_rbtx4927_power_off(void);
73
74 int tx4927_using_backplane = 0;
75
76 extern void toshiba_rbtx4927_irq_setup(void);
77
78 char *prom_getcmdline(void);
79
80 #ifdef CONFIG_PCI
81 #undef TX4927_SUPPORT_COMMAND_IO
82 #undef TX4927_SUPPORT_PCI_66
83 int tx4927_cpu_clock = 100000000; /* 100MHz */
84 unsigned long mips_pci_io_base;
85 unsigned long mips_pci_io_size;
86 unsigned long mips_pci_mem_base;
87 unsigned long mips_pci_mem_size;
88 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
89 unsigned long mips_pci_io_pciaddr = 0;
90 unsigned long mips_memory_upper;
91 static int tx4927_ccfg_toeon = 1;
92 static int tx4927_pcic_trdyto = 0; /* default: disabled */
93 unsigned long tx4927_ce_base[8];
94 int tx4927_pci66 = 0; /* 0:auto */
95 #endif
96
97 char *toshiba_name = "";
98
99 #ifdef CONFIG_PCI
100 extern struct pci_controller tx4927_controller;
101
102 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
103 int top_bus, int busnr, int devfn)
104 {
105 static struct pci_dev dev;
106 static struct pci_bus bus;
107
108 dev.sysdata = (void *)hose;
109 dev.devfn = devfn;
110 bus.number = busnr;
111 bus.ops = hose->pci_ops;
112 bus.parent = NULL;
113 dev.bus = &bus;
114
115 return &dev;
116 }
117
118 #define EARLY_PCI_OP(rw, size, type) \
119 static int early_##rw##_config_##size(struct pci_controller *hose, \
120 int top_bus, int bus, int devfn, int offset, type value) \
121 { \
122 return pci_##rw##_config_##size( \
123 fake_pci_dev(hose, top_bus, bus, devfn), \
124 offset, value); \
125 }
126
127 EARLY_PCI_OP(read, byte, u8 *)
128 EARLY_PCI_OP(read, dword, u32 *)
129 EARLY_PCI_OP(write, byte, u8)
130 EARLY_PCI_OP(write, dword, u32)
131
132 static int __init tx4927_pcibios_init(void)
133 {
134 unsigned int id;
135 u32 pci_devfn;
136 int devfn_start = 0;
137 int devfn_stop = 0xff;
138 int busno = 0; /* One bus on the Toshiba */
139 struct pci_controller *hose = &tx4927_controller;
140
141 for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
142 early_read_config_dword(hose, busno, busno, pci_devfn,
143 PCI_VENDOR_ID, &id);
144
145 if (id == 0xffffffff) {
146 continue;
147 }
148
149 if (id == 0x94601055) {
150 u8 v08_64;
151 u32 v32_b0;
152 u8 v08_e1;
153
154 early_read_config_byte(hose, busno, busno,
155 pci_devfn, 0x64, &v08_64);
156 early_read_config_dword(hose, busno, busno,
157 pci_devfn, 0xb0, &v32_b0);
158 early_read_config_byte(hose, busno, busno,
159 pci_devfn, 0xe1, &v08_e1);
160
161 /* serial irq control */
162 v08_64 = 0xd0;
163
164 /* serial irq pin */
165 v32_b0 |= 0x00010000;
166
167 /* ide irq on isa14 */
168 v08_e1 &= 0xf0;
169 v08_e1 |= 0x0d;
170
171 early_write_config_byte(hose, busno, busno,
172 pci_devfn, 0x64, v08_64);
173 early_write_config_dword(hose, busno, busno,
174 pci_devfn, 0xb0, v32_b0);
175 early_write_config_byte(hose, busno, busno,
176 pci_devfn, 0xe1, v08_e1);
177 }
178
179 if (id == 0x91301055) {
180 u8 v08_04;
181 u8 v08_09;
182 u8 v08_41;
183 u8 v08_43;
184 u8 v08_5c;
185
186 early_read_config_byte(hose, busno, busno,
187 pci_devfn, 0x04, &v08_04);
188 early_read_config_byte(hose, busno, busno,
189 pci_devfn, 0x09, &v08_09);
190 early_read_config_byte(hose, busno, busno,
191 pci_devfn, 0x41, &v08_41);
192 early_read_config_byte(hose, busno, busno,
193 pci_devfn, 0x43, &v08_43);
194 early_read_config_byte(hose, busno, busno,
195 pci_devfn, 0x5c, &v08_5c);
196
197 /* enable ide master/io */
198 v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
199
200 /* enable ide native mode */
201 v08_09 |= 0x05;
202
203 /* enable primary ide */
204 v08_41 |= 0x80;
205
206 /* enable secondary ide */
207 v08_43 |= 0x80;
208
209 /*
210 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
211 *
212 * This line of code is intended to provide the user with a work
213 * around solution to the anomalies cited in SMSC's anomaly sheet
214 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
215 *
216 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
217 */
218 v08_5c |= 0x01;
219
220 early_write_config_byte(hose, busno, busno,
221 pci_devfn, 0x5c, v08_5c);
222 early_write_config_byte(hose, busno, busno,
223 pci_devfn, 0x04, v08_04);
224 early_write_config_byte(hose, busno, busno,
225 pci_devfn, 0x09, v08_09);
226 early_write_config_byte(hose, busno, busno,
227 pci_devfn, 0x41, v08_41);
228 early_write_config_byte(hose, busno, busno,
229 pci_devfn, 0x43, v08_43);
230 }
231
232 }
233
234 register_pci_controller(&tx4927_controller);
235 return 0;
236 }
237
238 arch_initcall(tx4927_pcibios_init);
239
240 extern struct resource pci_io_resource;
241 extern struct resource pci_mem_resource;
242
243 void __init tx4927_pci_setup(void)
244 {
245 static int called = 0;
246 extern unsigned int tx4927_get_mem_size(void);
247
248 mips_memory_upper = tx4927_get_mem_size() << 20;
249 mips_memory_upper += KSEG0;
250 mips_pci_io_base = TX4927_PCIIO;
251 mips_pci_io_size = TX4927_PCIIO_SIZE;
252 mips_pci_mem_base = TX4927_PCIMEM;
253 mips_pci_mem_size = TX4927_PCIMEM_SIZE;
254
255 if (!called) {
256 printk
257 ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
258 toshiba_name,
259 (unsigned short) (tx4927_pcicptr->pciid >> 16),
260 (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
261 (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
262 (!(tx4927_ccfgptr->
263 ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
264 "Internal");
265 called = 1;
266 }
267 printk("%s PCIC --%s PCICLK:", toshiba_name,
268 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
269 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
270 int pciclk = 0;
271 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
272 switch ((unsigned long) tx4927_ccfgptr->
273 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
274 case TX4937_CCFG_PCIDIVMODE_4:
275 pciclk = tx4927_cpu_clock / 4;
276 break;
277 case TX4937_CCFG_PCIDIVMODE_4_5:
278 pciclk = tx4927_cpu_clock * 2 / 9;
279 break;
280 case TX4937_CCFG_PCIDIVMODE_5:
281 pciclk = tx4927_cpu_clock / 5;
282 break;
283 case TX4937_CCFG_PCIDIVMODE_5_5:
284 pciclk = tx4927_cpu_clock * 2 / 11;
285 break;
286 case TX4937_CCFG_PCIDIVMODE_8:
287 pciclk = tx4927_cpu_clock / 8;
288 break;
289 case TX4937_CCFG_PCIDIVMODE_9:
290 pciclk = tx4927_cpu_clock / 9;
291 break;
292 case TX4937_CCFG_PCIDIVMODE_10:
293 pciclk = tx4927_cpu_clock / 10;
294 break;
295 case TX4937_CCFG_PCIDIVMODE_11:
296 pciclk = tx4927_cpu_clock / 11;
297 break;
298 }
299
300 else
301 switch ((unsigned long) tx4927_ccfgptr->
302 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
303 case TX4927_CCFG_PCIDIVMODE_2_5:
304 pciclk = tx4927_cpu_clock * 2 / 5;
305 break;
306 case TX4927_CCFG_PCIDIVMODE_3:
307 pciclk = tx4927_cpu_clock / 3;
308 break;
309 case TX4927_CCFG_PCIDIVMODE_5:
310 pciclk = tx4927_cpu_clock / 5;
311 break;
312 case TX4927_CCFG_PCIDIVMODE_6:
313 pciclk = tx4927_cpu_clock / 6;
314 break;
315 }
316
317 printk("Internal(%dMHz)", pciclk / 1000000);
318 } else
319 printk("External");
320 printk("\n");
321
322 /* GB->PCI mappings */
323 tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
324 tx4927_pcicptr->g2piogbase = mips_pci_io_base |
325 #ifdef __BIG_ENDIAN
326 TX4927_PCIC_G2PIOGBASE_ECHG
327 #else
328 TX4927_PCIC_G2PIOGBASE_BSDIS
329 #endif
330 ;
331
332 tx4927_pcicptr->g2piopbase = 0;
333
334 tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
335 tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
336 #ifdef __BIG_ENDIAN
337 TX4927_PCIC_G2PMnGBASE_ECHG
338 #else
339 TX4927_PCIC_G2PMnGBASE_BSDIS
340 #endif
341 ;
342 tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
343
344 tx4927_pcicptr->g2pmmask[1] = 0;
345 tx4927_pcicptr->g2pmgbase[1] = 0;
346 tx4927_pcicptr->g2pmpbase[1] = 0;
347 tx4927_pcicptr->g2pmmask[2] = 0;
348 tx4927_pcicptr->g2pmgbase[2] = 0;
349 tx4927_pcicptr->g2pmpbase[2] = 0;
350
351
352 /* PCI->GB mappings (I/O 256B) */
353 tx4927_pcicptr->p2giopbase = 0; /* 256B */
354
355 /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
356 tx4927_pcicptr->p2gm0plbase = 0;
357 tx4927_pcicptr->p2gm0pubase = 0;
358 tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
359 #ifdef __BIG_ENDIAN
360 TX4927_PCIC_P2GMnGBASE_TECHG
361 #else
362 TX4927_PCIC_P2GMnGBASE_TBSDIS
363 #endif
364 ;
365
366 /* PCI->GB mappings (MEM 16MB) -not used */
367 tx4927_pcicptr->p2gm1plbase = 0xffffffff;
368 tx4927_pcicptr->p2gm1pubase = 0xffffffff;
369 tx4927_pcicptr->p2gmgbase[1] = 0;
370
371 /* PCI->GB mappings (MEM 1MB) -not used */
372 tx4927_pcicptr->p2gm2pbase = 0xffffffff;
373 tx4927_pcicptr->p2gmgbase[2] = 0;
374
375
376 /* Enable Initiator Memory 0 Space, I/O Space, Config */
377 tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
378 tx4927_pcicptr->pciccfg |=
379 TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
380 TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
381
382
383 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
384 tx4927_pcicptr->pcicfg1 = 0;
385
386 if (tx4927_pcic_trdyto >= 0) {
387 tx4927_pcicptr->g2ptocnt &= ~0xff;
388 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
389 }
390
391 /* Clear All Local Bus Status */
392 tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
393 /* Enable All Local Bus Interrupts */
394 tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
395 /* Clear All Initiator Status */
396 tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
397 /* Enable All Initiator Interrupts */
398 tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
399 /* Clear All PCI Status Error */
400 tx4927_pcicptr->pcistatus =
401 (tx4927_pcicptr->pcistatus & 0x0000ffff) |
402 (TX4927_PCIC_PCISTATUS_ALL << 16);
403 /* Enable All PCI Status Error Interrupts */
404 tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
405
406 /* PCIC Int => IRC IRQ16 */
407 tx4927_pcicptr->pcicfg2 =
408 (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
409
410 if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
411 /* XXX */
412 } else {
413 /* Reset Bus Arbiter */
414 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
415 /* Enable Bus Arbiter */
416 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
417 }
418
419 tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
420 PCI_COMMAND_MEMORY |
421 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
422 }
423 #endif /* CONFIG_PCI */
424
425 static void __noreturn wait_forever(void)
426 {
427 while (1)
428 if (cpu_wait)
429 (*cpu_wait)();
430 }
431
432 void toshiba_rbtx4927_restart(char *command)
433 {
434 printk(KERN_NOTICE "System Rebooting...\n");
435
436 /* enable the s/w reset register */
437 writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);
438
439 /* wait for enable to be seen */
440 while ((readb(RBTX4927_SW_RESET_ENABLE) &
441 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
442
443 /* do a s/w reset */
444 writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);
445
446 /* do something passive while waiting for reset */
447 local_irq_disable();
448 wait_forever();
449 /* no return */
450 }
451
452 void toshiba_rbtx4927_halt(void)
453 {
454 printk(KERN_NOTICE "System Halted\n");
455 local_irq_disable();
456 wait_forever();
457 /* no return */
458 }
459
460 void toshiba_rbtx4927_power_off(void)
461 {
462 toshiba_rbtx4927_halt();
463 /* no return */
464 }
465
466 void __init plat_mem_setup(void)
467 {
468 int i;
469 u32 cp0_config;
470 char *argptr;
471
472 printk("CPU is %s\n", toshiba_name);
473
474 /* f/w leaves this on at startup */
475 clear_c0_status(ST0_ERL);
476
477 /* enable caches -- HCP5 does this, pmon does not */
478 cp0_config = read_c0_config();
479 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
480 write_c0_config(cp0_config);
481
482 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
483
484 ioport_resource.end = 0xffffffff;
485 iomem_resource.end = 0xffffffff;
486
487 _machine_restart = toshiba_rbtx4927_restart;
488 _machine_halt = toshiba_rbtx4927_halt;
489 pm_power_off = toshiba_rbtx4927_power_off;
490
491 for (i = 0; i < TX4927_NR_TMR; i++)
492 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
493
494 #ifdef CONFIG_PCI
495
496 /* PCIC */
497 /*
498 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
499 *
500 * For TX4927:
501 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
502 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
503 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
504 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
505 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
506 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
507 *
508 * For TX4937:
509 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
510 * PCIDIVMODE[10] is 0.
511 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
512 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
513 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
514 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
515 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
516 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
517 *
518 */
519 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
520 switch ((unsigned long)tx4927_ccfgptr->
521 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
522 case TX4937_CCFG_PCIDIVMODE_8:
523 case TX4937_CCFG_PCIDIVMODE_4:
524 tx4927_cpu_clock = 266666666; /* 266MHz */
525 break;
526 case TX4937_CCFG_PCIDIVMODE_9:
527 case TX4937_CCFG_PCIDIVMODE_4_5:
528 tx4927_cpu_clock = 300000000; /* 300MHz */
529 break;
530 default:
531 tx4927_cpu_clock = 333333333; /* 333MHz */
532 }
533 else
534 switch ((unsigned long)tx4927_ccfgptr->
535 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
536 case TX4927_CCFG_PCIDIVMODE_2_5:
537 case TX4927_CCFG_PCIDIVMODE_5:
538 tx4927_cpu_clock = 166666666; /* 166MHz */
539 break;
540 default:
541 tx4927_cpu_clock = 200000000; /* 200MHz */
542 }
543
544 /* CCFG */
545 /* do reset on watchdog */
546 tx4927_ccfgptr->ccfg |= TX4927_CCFG_WR;
547 /* enable Timeout BusError */
548 if (tx4927_ccfg_toeon)
549 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
550
551 tx4927_pci_setup();
552 if (tx4927_using_backplane == 1)
553 printk("backplane board IS installed\n");
554 else
555 printk("No Backplane \n");
556
557 /* this is on ISA bus behind PCI bus, so need PCI up first */
558 #ifdef CONFIG_TOSHIBA_FPCIB0
559 if (tx4927_using_backplane) {
560 smsc_fdc37m81x_init(0x3f0);
561 smsc_fdc37m81x_config_beg();
562 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
563 SMSC_FDC37M81X_KBD);
564 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
565 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
566 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
567 1);
568 smsc_fdc37m81x_config_end();
569 }
570 #endif
571 #endif /* CONFIG_PCI */
572
573 #ifdef CONFIG_SERIAL_TXX9
574 {
575 extern int early_serial_txx9_setup(struct uart_port *port);
576 struct uart_port req;
577 for(i = 0; i < 2; i++) {
578 memset(&req, 0, sizeof(req));
579 req.line = i;
580 req.iotype = UPIO_MEM;
581 req.membase = (char *)(0xff1ff300 + i * 0x100);
582 req.mapbase = 0xff1ff300 + i * 0x100;
583 req.irq = TX4927_IRQ_PIC_BEG + 8 + i;
584 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
585 req.uartclk = 50000000;
586 early_serial_txx9_setup(&req);
587 }
588 }
589 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
590 argptr = prom_getcmdline();
591 if (strstr(argptr, "console=") == NULL) {
592 strcat(argptr, " console=ttyS0,38400");
593 }
594 #endif
595 #endif
596
597 #ifdef CONFIG_ROOT_NFS
598 argptr = prom_getcmdline();
599 if (strstr(argptr, "root=") == NULL) {
600 strcat(argptr, " root=/dev/nfs rw");
601 }
602 #endif
603
604 #ifdef CONFIG_IP_PNP
605 argptr = prom_getcmdline();
606 if (strstr(argptr, "ip=") == NULL) {
607 strcat(argptr, " ip=any");
608 }
609 #endif
610 }
611
612 void __init plat_time_init(void)
613 {
614 mips_hpt_frequency = tx4927_cpu_clock / 2;
615 if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS)
616 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
617 TXX9_IRQ_BASE + 17,
618 50000000);
619 }
620
621 static int __init toshiba_rbtx4927_rtc_init(void)
622 {
623 static struct resource __initdata res = {
624 .start = 0x1c010000,
625 .end = 0x1c010000 + 0x800 - 1,
626 .flags = IORESOURCE_MEM,
627 };
628 struct platform_device *dev =
629 platform_device_register_simple("rtc-ds1742", -1, &res, 1);
630 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
631 }
632 device_initcall(toshiba_rbtx4927_rtc_init);
633
634 static int __init rbtx4927_ne_init(void)
635 {
636 static struct resource __initdata res[] = {
637 {
638 .start = RBTX4927_RTL_8019_BASE,
639 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
640 .flags = IORESOURCE_IO,
641 }, {
642 .start = RBTX4927_RTL_8019_IRQ,
643 .flags = IORESOURCE_IRQ,
644 }
645 };
646 struct platform_device *dev =
647 platform_device_register_simple("ne", -1,
648 res, ARRAY_SIZE(res));
649 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
650 }
651 device_initcall(rbtx4927_ne_init);
652
653 /* Watchdog support */
654
655 static int __init txx9_wdt_init(unsigned long base)
656 {
657 struct resource res = {
658 .start = base,
659 .end = base + 0x100 - 1,
660 .flags = IORESOURCE_MEM,
661 };
662 struct platform_device *dev =
663 platform_device_register_simple("txx9wdt", -1, &res, 1);
664 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
665 }
666
667 static int __init rbtx4927_wdt_init(void)
668 {
669 return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
670 }
671 device_initcall(rbtx4927_wdt_init);
672
673 /* Minimum CLK support */
674
675 struct clk *clk_get(struct device *dev, const char *id)
676 {
677 if (!strcmp(id, "imbus_clk"))
678 return (struct clk *)50000000;
679 return ERR_PTR(-ENOENT);
680 }
681 EXPORT_SYMBOL(clk_get);
682
683 int clk_enable(struct clk *clk)
684 {
685 return 0;
686 }
687 EXPORT_SYMBOL(clk_enable);
688
689 void clk_disable(struct clk *clk)
690 {
691 }
692 EXPORT_SYMBOL(clk_disable);
693
694 unsigned long clk_get_rate(struct clk *clk)
695 {
696 return (unsigned long)clk;
697 }
698 EXPORT_SYMBOL(clk_get_rate);
699
700 void clk_put(struct clk *clk)
701 {
702 }
703 EXPORT_SYMBOL(clk_put);
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