arch/mips/txx9/rbtx4938/irq.c

   1 /*
   2  * Toshiba RBTX4938 specific interrupt handlers
   3  * Copyright (C) 2000-2001 Toshiba Corporation
   4  *
   5  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
   6  * terms of the GNU General Public License version 2. This program is
   7  * licensed "as is" without any warranty of any kind, whether express
   8  * or implied.
   9  *
  10  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  11  */
  12
  13 /*
  14  * MIPS_CPU_IRQ_BASE+00 Software 0
  15  * MIPS_CPU_IRQ_BASE+01 Software 1
  16  * MIPS_CPU_IRQ_BASE+02 Cascade TX4938-CP0
  17  * MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use
  18  * MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use
  19  * MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use
  20  * MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use
  21  * MIPS_CPU_IRQ_BASE+07 CPU TIMER
  22  *
  23  * TXX9_IRQ_BASE+00
  24  * TXX9_IRQ_BASE+01
  25  * TXX9_IRQ_BASE+02 Cascade RBTX4938-IOC
  26  * TXX9_IRQ_BASE+03 RBTX4938 RTL-8019AS Ethernet
  27  * TXX9_IRQ_BASE+04
  28  * TXX9_IRQ_BASE+05 TX4938 ETH1
  29  * TXX9_IRQ_BASE+06 TX4938 ETH0
  30  * TXX9_IRQ_BASE+07
  31  * TXX9_IRQ_BASE+08 TX4938 SIO 0
  32  * TXX9_IRQ_BASE+09 TX4938 SIO 1
  33  * TXX9_IRQ_BASE+10 TX4938 DMA0
  34  * TXX9_IRQ_BASE+11 TX4938 DMA1
  35  * TXX9_IRQ_BASE+12 TX4938 DMA2
  36  * TXX9_IRQ_BASE+13 TX4938 DMA3
  37  * TXX9_IRQ_BASE+14
  38  * TXX9_IRQ_BASE+15
  39  * TXX9_IRQ_BASE+16 TX4938 PCIC
  40  * TXX9_IRQ_BASE+17 TX4938 TMR0
  41  * TXX9_IRQ_BASE+18 TX4938 TMR1
  42  * TXX9_IRQ_BASE+19 TX4938 TMR2
  43  * TXX9_IRQ_BASE+20
  44  * TXX9_IRQ_BASE+21
  45  * TXX9_IRQ_BASE+22 TX4938 PCIERR
  46  * TXX9_IRQ_BASE+23
  47  * TXX9_IRQ_BASE+24
  48  * TXX9_IRQ_BASE+25
  49  * TXX9_IRQ_BASE+26
  50  * TXX9_IRQ_BASE+27
  51  * TXX9_IRQ_BASE+28
  52  * TXX9_IRQ_BASE+29
  53  * TXX9_IRQ_BASE+30
  54  * TXX9_IRQ_BASE+31 TX4938 SPI
  55  *
  56  * RBTX4938_IRQ_IOC+00 PCI-D
  57  * RBTX4938_IRQ_IOC+01 PCI-C
  58  * RBTX4938_IRQ_IOC+02 PCI-B
  59  * RBTX4938_IRQ_IOC+03 PCI-A
  60  * RBTX4938_IRQ_IOC+04 RTC
  61  * RBTX4938_IRQ_IOC+05 ATA
  62  * RBTX4938_IRQ_IOC+06 MODEM
  63  * RBTX4938_IRQ_IOC+07 SWINT
  64  */
  65 #include <linux/init.h>
  66 #include <linux/interrupt.h>
  67 #include <linux/irq.h>
  68 #include <asm/mipsregs.h>
  69 #include <asm/txx9/generic.h>
  70 #include <asm/txx9/rbtx4938.h>
  71
  72 static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
  73 static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
  74
  75 #define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
  76 static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
  77         .name = TOSHIBA_RBTX4938_IOC_NAME,
  78         .ack = toshiba_rbtx4938_irq_ioc_disable,
  79         .mask = toshiba_rbtx4938_irq_ioc_disable,
  80         .mask_ack = toshiba_rbtx4938_irq_ioc_disable,
  81         .unmask = toshiba_rbtx4938_irq_ioc_enable,
  82 };
  83
  84 static int toshiba_rbtx4938_irq_nested(int sw_irq)
  85 {
  86         u8 level3;
  87
  88         level3 = readb(rbtx4938_imstat_addr);
  89         if (unlikely(!level3))
  90                 return -1;
  91         /* must use fls so onboard ATA has priority */
  92         return RBTX4938_IRQ_IOC + __fls8(level3);
  93 }
  94
  95 static void __init
  96 toshiba_rbtx4938_irq_ioc_init(void)
  97 {
  98         int i;
  99
 100         for (i = RBTX4938_IRQ_IOC;
 101              i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
 102                 set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
 103                                          handle_level_irq);
 104
 105         set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
 106 }
 107
 108 static void
 109 toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
 110 {
 111         unsigned char v;
 112
 113         v = readb(rbtx4938_imask_addr);
 114         v |= (1 << (irq - RBTX4938_IRQ_IOC));
 115         writeb(v, rbtx4938_imask_addr);
 116         mmiowb();
 117 }
 118
 119 static void
 120 toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
 121 {
 122         unsigned char v;
 123
 124         v = readb(rbtx4938_imask_addr);
 125         v &= ~(1 << (irq - RBTX4938_IRQ_IOC));
 126         writeb(v, rbtx4938_imask_addr);
 127         mmiowb();
 128 }
 129
 130 static int rbtx4938_irq_dispatch(int pending)
 131 {
 132         int irq;
 133
 134         if (pending & STATUSF_IP7)
 135                 irq = MIPS_CPU_IRQ_BASE + 7;
 136         else if (pending & STATUSF_IP2) {
 137                 irq = txx9_irq();
 138                 if (irq == RBTX4938_IRQ_IOCINT)
 139                         irq = toshiba_rbtx4938_irq_nested(irq);
 140         } else if (pending & STATUSF_IP1)
 141                 irq = MIPS_CPU_IRQ_BASE + 0;
 142         else if (pending & STATUSF_IP0)
 143                 irq = MIPS_CPU_IRQ_BASE + 1;
 144         else
 145                 irq = -1;
 146         return irq;
 147 }
 148
 149 void __init rbtx4938_irq_setup(void)
 150 {
 151         txx9_irq_dispatch = rbtx4938_irq_dispatch;
 152         /* Now, interrupt control disabled, */
 153         /* all IRC interrupts are masked, */
 154         /* all IRC interrupt mode are Low Active. */
 155
 156         /* mask all IOC interrupts */
 157         writeb(0, rbtx4938_imask_addr);
 158
 159         /* clear SoftInt interrupts */
 160         writeb(0, rbtx4938_softint_addr);
 161         tx4938_irq_init();
 162         toshiba_rbtx4938_irq_ioc_init();
 163         /* Onboard 10M Ether: High Active */
 164         set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
 165 }