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[MIPS] vr41xx: Move IRQ numbers to asm-mips/vr41xx/irq.h
[mirror_ubuntu-zesty-kernel.git] / arch / mips / vr41xx / common / irq.c
1 /*
2 * Interrupt handing routines for NEC VR4100 series.
3 *
4 * Copyright (C) 2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22
23 #include <asm/irq_cpu.h>
24 #include <asm/system.h>
25 #include <asm/vr41xx/irq.h>
26
27 typedef struct irq_cascade {
28 int (*get_irq)(unsigned int, struct pt_regs *);
29 } irq_cascade_t;
30
31 static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned;
32
33 static struct irqaction cascade_irqaction = {
34 .handler = no_action,
35 .mask = CPU_MASK_NONE,
36 .name = "cascade",
37 };
38
39 int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *))
40 {
41 int retval = 0;
42
43 if (irq >= NR_IRQS)
44 return -EINVAL;
45
46 if (irq_cascade[irq].get_irq != NULL)
47 free_irq(irq, NULL);
48
49 irq_cascade[irq].get_irq = get_irq;
50
51 if (get_irq != NULL) {
52 retval = setup_irq(irq, &cascade_irqaction);
53 if (retval < 0)
54 irq_cascade[irq].get_irq = NULL;
55 }
56
57 return retval;
58 }
59
60 EXPORT_SYMBOL_GPL(cascade_irq);
61
62 static void irq_dispatch(unsigned int irq, struct pt_regs *regs)
63 {
64 irq_cascade_t *cascade;
65 struct irq_desc *desc;
66
67 if (irq >= NR_IRQS) {
68 atomic_inc(&irq_err_count);
69 return;
70 }
71
72 cascade = irq_cascade + irq;
73 if (cascade->get_irq != NULL) {
74 unsigned int source_irq = irq;
75 desc = irq_desc + source_irq;
76 desc->chip->ack(source_irq);
77 irq = cascade->get_irq(irq, regs);
78 if (irq < 0)
79 atomic_inc(&irq_err_count);
80 else
81 irq_dispatch(irq, regs);
82 desc->chip->end(source_irq);
83 } else
84 do_IRQ(irq, regs);
85 }
86
87 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
88 {
89 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
90
91 if (pending & CAUSEF_IP7)
92 do_IRQ(7, regs);
93 else if (pending & 0x7800) {
94 if (pending & CAUSEF_IP3)
95 irq_dispatch(3, regs);
96 else if (pending & CAUSEF_IP4)
97 irq_dispatch(4, regs);
98 else if (pending & CAUSEF_IP5)
99 irq_dispatch(5, regs);
100 else if (pending & CAUSEF_IP6)
101 irq_dispatch(6, regs);
102 } else if (pending & CAUSEF_IP2)
103 irq_dispatch(2, regs);
104 else if (pending & CAUSEF_IP0)
105 do_IRQ(0, regs);
106 else if (pending & CAUSEF_IP1)
107 do_IRQ(1, regs);
108 else
109 spurious_interrupt(regs);
110 }
111
112 void __init arch_init_irq(void)
113 {
114 mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
115 }