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MN10300: Make the boot wrapper able to use writeback caching
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1 /* Boot entry point for a compressed MN10300 kernel
2 *
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11 .section .text
12
13 #define DEBUG
14
15 #include <linux/linkage.h>
16 #include <asm/cpu-regs.h>
17 #include <asm/cache.h>
18
19 .globl startup_32
20 startup_32:
21 # first save off parameters from bootloader
22 mov param_save_area,a0
23 mov d0,(a0)
24 mov d1,(4,a0)
25 mov d2,(8,a0)
26
27 mov sp,a3
28 mov decomp_stack+0x2000-4,a0
29 mov a0,sp
30
31 # invalidate and enable both of the caches
32 mov CHCTR,a0
33 clr d0
34 movhu d0,(a0) # turn off first
35 mov CHCTR_ICINV|CHCTR_DCINV,d0
36 movhu d0,(a0)
37 setlb
38 mov (a0),d0
39 btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy
40 lne
41
42 #ifdef CONFIG_MN10300_CACHE_ENABLED
43 #ifdef CONFIG_MN10300_CACHE_WBACK
44 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0
45 #else
46 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0
47 #endif /* WBACK */
48 movhu d0,(a0) # enable
49 #endif /* !ENABLED */
50
51 # clear the BSS area
52 mov __bss_start,a0
53 mov _end,a1
54 clr d0
55 bssclear:
56 cmp a1,a0
57 bge bssclear_end
58 movbu d0,(a0)
59 inc a0
60 bra bssclear
61 bssclear_end:
62
63 # decompress the kernel
64 call decompress_kernel[],0
65 #ifdef CONFIG_MN10300_CACHE_WBACK
66 call mn10300_dcache_flush_inv[],0
67 #endif
68
69 # disable caches again
70 mov CHCTR,a0
71 clr d0
72 movhu d0,(a0)
73 setlb
74 mov (a0),d0
75 btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy
76 lne
77
78 mov param_save_area,a0
79 mov (a0),d0
80 mov (4,a0),d1
81 mov (8,a0),d2
82
83 # jump to the kernel proper entry point
84 mov a3,sp
85 mov CONFIG_KERNEL_TEXT_ADDRESS,a0
86 jmp (a0)
87
88
89 ###############################################################################
90 #
91 # Cache flush routines
92 #
93 ###############################################################################
94 #ifdef CONFIG_MN10300_CACHE_WBACK
95 mn10300_dcache_flush_inv:
96 movhu (CHCTR),d0
97 btst CHCTR_DCEN,d0
98 beq mn10300_dcache_flush_inv_end
99
100 mov L1_CACHE_NENTRIES,d1
101 clr a1
102
103 mn10300_dcache_flush_inv_loop:
104 mov (DCACHE_PURGE_WAY0(0),a1),d0 # unconditional purge
105 mov (DCACHE_PURGE_WAY1(0),a1),d0 # unconditional purge
106 mov (DCACHE_PURGE_WAY2(0),a1),d0 # unconditional purge
107 mov (DCACHE_PURGE_WAY3(0),a1),d0 # unconditional purge
108
109 add L1_CACHE_BYTES,a1
110 add -1,d1
111 bne mn10300_dcache_flush_inv_loop
112
113 mn10300_dcache_flush_inv_end:
114 ret [],0
115 #endif /* CONFIG_MN10300_CACHE_WBACK */
116
117
118 ###############################################################################
119 #
120 # Data areas
121 #
122 ###############################################################################
123 .data
124 .align 4
125 param_save_area:
126 .rept 3
127 .word 0
128 .endr
129
130 .section .bss
131 .align 4
132 decomp_stack:
133 .space 0x2000