arch/mn10300/unit-asb2364/include/unit/timex.h

   1 /* timex.h: MN2WS0038 architecture timer specifications
   2  *
   3  * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
   4  * Written by David Howells (dhowells@redhat.com)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #ifndef _ASM_UNIT_TIMEX_H
  12 #define _ASM_UNIT_TIMEX_H
  13
  14 #ifndef __ASSEMBLY__
  15 #include <linux/irq.h>
  16 #endif /* __ASSEMBLY__ */
  17
  18 #include <asm/timer-regs.h>
  19 #include <unit/clock.h>
  20 #include <asm/param.h>
  21
  22 /*
  23  * jiffies counter specifications
  24  */
  25
  26 #define TMJCBR_MAX              0xffffff        /* 24bit */
  27 #define TMJCBC                  TMTBC
  28
  29 #define TMJCMD                  TMTMD
  30 #define TMJCBR                  TMTBR
  31 #define TMJCIRQ                 TMTIRQ
  32 #define TMJCICR                 TMTICR
  33
  34 #ifndef __ASSEMBLY__
  35
  36 #define MN10300_SRC_IOBCLK      MN10300_IOBCLK
  37
  38 #ifndef HZ
  39 # error HZ undeclared.
  40 #endif /* !HZ */
  41
  42 #define MN10300_JCCLK           (MN10300_SRC_IOBCLK)
  43 #define MN10300_TSCCLK          (MN10300_SRC_IOBCLK)
  44
  45 #define MN10300_JC_PER_HZ       ((MN10300_JCCLK + HZ / 2) / HZ)
  46 #define MN10300_TSC_PER_HZ      ((MN10300_TSCCLK + HZ / 2) / HZ)
  47
  48 /* Check bit width of MTM interval value that sets base register */
  49 #if (MN10300_JC_PER_HZ - 1) > TMJCBR_MAX
  50 # error MTM tick timer interval value is overflow.
  51 #endif
  52
  53
  54 static inline void startup_jiffies_counter(void)
  55 {
  56         u32 sync;
  57
  58         TMJCBR = MN10300_JC_PER_HZ - 1;
  59         sync = TMJCBR;
  60
  61         TMJCMD = TMTMD_TMTLDE;
  62         TMJCMD = TMTMD_TMTCNE;
  63         sync = TMJCMD;
  64
  65         TMJCICR |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST;
  66         sync = TMJCICR;
  67 }
  68
  69 static inline void shutdown_jiffies_counter(void)
  70 {
  71 }
  72
  73 #endif /* !__ASSEMBLY__ */
  74
  75
  76 /*
  77  * timestamp counter specifications
  78  */
  79
  80 #define TMTSCBR_MAX     0xffffffff
  81 #define TMTSCMD         TMSMD
  82 #define TMTSCBR         TMSBR
  83 #define TMTSCBC         TMSBC
  84 #define TMTSCICR        TMSICR
  85
  86 #ifndef __ASSEMBLY__
  87
  88 static inline void startup_timestamp_counter(void)
  89 {
  90         u32 sync;
  91
  92         /* set up TMS(Timestamp) 32bit timer register to count real time
  93          * - count down from 4Gig-1 to 0 and wrap at IOBCLK rate
  94          */
  95
  96         TMTSCBR = TMTSCBR_MAX;
  97         sync = TMTSCBR;
  98
  99         TMTSCICR = 0;
 100         sync = TMTSCICR;
 101
 102         TMTSCMD = TMTMD_TMTLDE;
 103         TMTSCMD = TMTMD_TMTCNE;
 104         sync = TMTSCMD;
 105 }
 106
 107 static inline void shutdown_timestamp_counter(void)
 108 {
 109         TMTSCMD = 0;
 110 }
 111
 112 /*
 113  * we use a cascaded pair of 16-bit down-counting timers to count I/O
 114  * clock cycles for the purposes of time keeping
 115  */
 116 typedef unsigned long cycles_t;
 117
 118 static inline cycles_t read_timestamp_counter(void)
 119 {
 120         return (cycles_t)TMTSCBC;
 121 }
 122
 123 #endif /* !__ASSEMBLY__ */
 124
 125 #endif /* _ASM_UNIT_TIMEX_H */