arch/openrisc/include/asm/pgtable.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * OpenRISC Linux
   4  *
   5  * Linux architectural port borrowing liberally from similar works of
   6  * others.  All original copyrights apply as per the original source
   7  * declaration.
   8  *
   9  * OpenRISC implementation:
  10  * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
  11  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  12  * et al.
  13  */
  14
  15 /* or32 pgtable.h - macros and functions to manipulate page tables
  16  *
  17  * Based on:
  18  * include/asm-cris/pgtable.h
  19  */
  20
  21 #ifndef __ASM_OPENRISC_PGTABLE_H
  22 #define __ASM_OPENRISC_PGTABLE_H
  23
  24 #define __ARCH_USE_5LEVEL_HACK
  25 #include <asm-generic/pgtable-nopmd.h>
  26
  27 #ifndef __ASSEMBLY__
  28 #include <asm/mmu.h>
  29 #include <asm/fixmap.h>
  30
  31 /*
  32  * The Linux memory management assumes a three-level page table setup. On
  33  * or32, we use that, but "fold" the mid level into the top-level page
  34  * table. Since the MMU TLB is software loaded through an interrupt, it
  35  * supports any page table structure, so we could have used a three-level
  36  * setup, but for the amounts of memory we normally use, a two-level is
  37  * probably more efficient.
  38  *
  39  * This file contains the functions and defines necessary to modify and use
  40  * the or32 page table tree.
  41  */
  42
  43 extern void paging_init(void);
  44
  45 /* Certain architectures need to do special things when pte's
  46  * within a page table are directly modified.  Thus, the following
  47  * hook is made available.
  48  */
  49 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
  50 #define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
  51 /*
  52  * (pmds are folded into pgds so this doesn't get actually called,
  53  * but the define is needed for a generic inline function.)
  54  */
  55 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
  56
  57 #define PGDIR_SHIFT     (PAGE_SHIFT + (PAGE_SHIFT-2))
  58 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  59 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  60
  61 /*
  62  * entries per page directory level: we use a two-level, so
  63  * we don't really have any PMD directory physically.
  64  * pointers are 4 bytes so we can use the page size and
  65  * divide it by 4 (shift by 2).
  66  */
  67 #define PTRS_PER_PTE    (1UL << (PAGE_SHIFT-2))
  68
  69 #define PTRS_PER_PGD    (1UL << (32-PGDIR_SHIFT))
  70
  71 /* calculate how many PGD entries a user-level program can use
  72  * the first mappable virtual address is 0
  73  * (TASK_SIZE is the maximum virtual address space)
  74  */
  75
  76 #define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
  77 #define FIRST_USER_ADDRESS      0UL
  78
  79 /*
  80  * Kernels own virtual memory area.
  81  */
  82
  83 /*
  84  * The size and location of the vmalloc area are chosen so that modules
  85  * placed in this area aren't more than a 28-bit signed offset from any
  86  * kernel functions that they may need.  This greatly simplifies handling
  87  * of the relocations for l.j and l.jal instructions as we don't need to
  88  * introduce any trampolines for reaching "distant" code.
  89  *
  90  * 64 MB of vmalloc area is comparable to what's available on other arches.
  91  */
  92
  93 #define VMALLOC_START   (PAGE_OFFSET-0x04000000UL)
  94 #define VMALLOC_END     (PAGE_OFFSET)
  95 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
  96
  97 /* Define some higher level generic page attributes.
  98  *
  99  * If you change _PAGE_CI definition be sure to change it in
 100  * io.h for ioremap_nocache() too.
 101  */
 102
 103 /*
 104  * An OR32 PTE looks like this:
 105  *
 106  * |  31 ... 10 |  9  |  8 ... 6  |  5  |  4  |  3  |  2  |  1  |  0  |
 107  *  Phys pg.num    L     PP Index    D     A    WOM   WBC   CI    CC
 108  *
 109  *  L  : link
 110  *  PPI: Page protection index
 111  *  D  : Dirty
 112  *  A  : Accessed
 113  *  WOM: Weakly ordered memory
 114  *  WBC: Write-back cache
 115  *  CI : Cache inhibit
 116  *  CC : Cache coherent
 117  *
 118  * The protection bits below should correspond to the layout of the actual
 119  * PTE as per above
 120  */
 121
 122 #define _PAGE_CC       0x001 /* software: pte contains a translation */
 123 #define _PAGE_CI       0x002 /* cache inhibit          */
 124 #define _PAGE_WBC      0x004 /* write back cache       */
 125 #define _PAGE_WOM      0x008 /* weakly ordered memory  */
 126
 127 #define _PAGE_A        0x010 /* accessed               */
 128 #define _PAGE_D        0x020 /* dirty                  */
 129 #define _PAGE_URE      0x040 /* user read enable       */
 130 #define _PAGE_UWE      0x080 /* user write enable      */
 131
 132 #define _PAGE_SRE      0x100 /* superuser read enable  */
 133 #define _PAGE_SWE      0x200 /* superuser write enable */
 134 #define _PAGE_EXEC     0x400 /* software: page is executable */
 135 #define _PAGE_U_SHARED 0x800 /* software: page is shared in user space */
 136
 137 /* 0x001 is cache coherency bit, which should always be set to
 138  *       1 - for SMP (when we support it)
 139  *       0 - otherwise
 140  *
 141  * we just reuse this bit in software for _PAGE_PRESENT and
 142  * force it to 0 when loading it into TLB.
 143  */
 144 #define _PAGE_PRESENT  _PAGE_CC
 145 #define _PAGE_USER     _PAGE_URE
 146 #define _PAGE_WRITE    (_PAGE_UWE | _PAGE_SWE)
 147 #define _PAGE_DIRTY    _PAGE_D
 148 #define _PAGE_ACCESSED _PAGE_A
 149 #define _PAGE_NO_CACHE _PAGE_CI
 150 #define _PAGE_SHARED   _PAGE_U_SHARED
 151 #define _PAGE_READ     (_PAGE_URE | _PAGE_SRE)
 152
 153 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 154 #define _PAGE_BASE     (_PAGE_PRESENT | _PAGE_ACCESSED)
 155 #define _PAGE_ALL      (_PAGE_PRESENT | _PAGE_ACCESSED)
 156 #define _KERNPG_TABLE \
 157         (_PAGE_BASE | _PAGE_SRE | _PAGE_SWE | _PAGE_ACCESSED | _PAGE_DIRTY)
 158
 159 #define PAGE_NONE       __pgprot(_PAGE_ALL)
 160 #define PAGE_READONLY   __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE)
 161 #define PAGE_READONLY_X __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_EXEC)
 162 #define PAGE_SHARED \
 163         __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_UWE | _PAGE_SWE \
 164                  | _PAGE_SHARED)
 165 #define PAGE_SHARED_X \
 166         __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_UWE | _PAGE_SWE \
 167                  | _PAGE_SHARED | _PAGE_EXEC)
 168 #define PAGE_COPY       __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE)
 169 #define PAGE_COPY_X     __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_EXEC)
 170
 171 #define PAGE_KERNEL \
 172         __pgprot(_PAGE_ALL | _PAGE_SRE | _PAGE_SWE \
 173                  | _PAGE_SHARED | _PAGE_DIRTY | _PAGE_EXEC)
 174 #define PAGE_KERNEL_RO \
 175         __pgprot(_PAGE_ALL | _PAGE_SRE \
 176                  | _PAGE_SHARED | _PAGE_DIRTY | _PAGE_EXEC)
 177 #define PAGE_KERNEL_NOCACHE \
 178         __pgprot(_PAGE_ALL | _PAGE_SRE | _PAGE_SWE \
 179                  | _PAGE_SHARED | _PAGE_DIRTY | _PAGE_EXEC | _PAGE_CI)
 180
 181 #define __P000  PAGE_NONE
 182 #define __P001  PAGE_READONLY_X
 183 #define __P010  PAGE_COPY
 184 #define __P011  PAGE_COPY_X
 185 #define __P100  PAGE_READONLY
 186 #define __P101  PAGE_READONLY_X
 187 #define __P110  PAGE_COPY
 188 #define __P111  PAGE_COPY_X
 189
 190 #define __S000  PAGE_NONE
 191 #define __S001  PAGE_READONLY_X
 192 #define __S010  PAGE_SHARED
 193 #define __S011  PAGE_SHARED_X
 194 #define __S100  PAGE_READONLY
 195 #define __S101  PAGE_READONLY_X
 196 #define __S110  PAGE_SHARED
 197 #define __S111  PAGE_SHARED_X
 198
 199 /* zero page used for uninitialized stuff */
 200 extern unsigned long empty_zero_page[2048];
 201 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
 202
 203 /* number of bits that fit into a memory pointer */
 204 #define BITS_PER_PTR                    (8*sizeof(unsigned long))
 205
 206 /* to align the pointer to a pointer address */
 207 #define PTR_MASK                        (~(sizeof(void *)-1))
 208
 209 /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
 210 /* 64-bit machines, beware!  SRB. */
 211 #define SIZEOF_PTR_LOG2                 2
 212
 213 /* to find an entry in a page-table */
 214 #define PAGE_PTR(address) \
 215 ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
 216
 217 /* to set the page-dir */
 218 #define SET_PAGE_DIR(tsk, pgdir)
 219
 220 #define pte_none(x)     (!pte_val(x))
 221 #define pte_present(x)  (pte_val(x) & _PAGE_PRESENT)
 222 #define pte_clear(mm, addr, xp) do { pte_val(*(xp)) = 0; } while (0)
 223
 224 #define pmd_none(x)     (!pmd_val(x))
 225 #define pmd_bad(x)      ((pmd_val(x) & (~PAGE_MASK)) != _KERNPG_TABLE)
 226 #define pmd_present(x)  (pmd_val(x) & _PAGE_PRESENT)
 227 #define pmd_clear(xp)   do { pmd_val(*(xp)) = 0; } while (0)
 228
 229 /*
 230  * The following only work if pte_present() is true.
 231  * Undefined behaviour if not..
 232  */
 233
 234 static inline int pte_read(pte_t pte)  { return pte_val(pte) & _PAGE_READ; }
 235 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
 236 static inline int pte_exec(pte_t pte)  { return pte_val(pte) & _PAGE_EXEC; }
 237 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
 238 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
 239 static inline int pte_special(pte_t pte) { return 0; }
 240 static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
 241
 242 static inline pte_t pte_wrprotect(pte_t pte)
 243 {
 244         pte_val(pte) &= ~(_PAGE_WRITE);
 245         return pte;
 246 }
 247
 248 static inline pte_t pte_rdprotect(pte_t pte)
 249 {
 250         pte_val(pte) &= ~(_PAGE_READ);
 251         return pte;
 252 }
 253
 254 static inline pte_t pte_exprotect(pte_t pte)
 255 {
 256         pte_val(pte) &= ~(_PAGE_EXEC);
 257         return pte;
 258 }
 259
 260 static inline pte_t pte_mkclean(pte_t pte)
 261 {
 262         pte_val(pte) &= ~(_PAGE_DIRTY);
 263         return pte;
 264 }
 265
 266 static inline pte_t pte_mkold(pte_t pte)
 267 {
 268         pte_val(pte) &= ~(_PAGE_ACCESSED);
 269         return pte;
 270 }
 271
 272 static inline pte_t pte_mkwrite(pte_t pte)
 273 {
 274         pte_val(pte) |= _PAGE_WRITE;
 275         return pte;
 276 }
 277
 278 static inline pte_t pte_mkread(pte_t pte)
 279 {
 280         pte_val(pte) |= _PAGE_READ;
 281         return pte;
 282 }
 283
 284 static inline pte_t pte_mkexec(pte_t pte)
 285 {
 286         pte_val(pte) |= _PAGE_EXEC;
 287         return pte;
 288 }
 289
 290 static inline pte_t pte_mkdirty(pte_t pte)
 291 {
 292         pte_val(pte) |= _PAGE_DIRTY;
 293         return pte;
 294 }
 295
 296 static inline pte_t pte_mkyoung(pte_t pte)
 297 {
 298         pte_val(pte) |= _PAGE_ACCESSED;
 299         return pte;
 300 }
 301
 302 /*
 303  * Conversion functions: convert a page and protection to a page entry,
 304  * and a page entry and page directory to the page they refer to.
 305  */
 306
 307 /* What actually goes as arguments to the various functions is less than
 308  * obvious, but a rule of thumb is that struct page's goes as struct page *,
 309  * really physical DRAM addresses are unsigned long's, and DRAM "virtual"
 310  * addresses (the 0xc0xxxxxx's) goes as void *'s.
 311  */
 312
 313 static inline pte_t __mk_pte(void *page, pgprot_t pgprot)
 314 {
 315         pte_t pte;
 316         /* the PTE needs a physical address */
 317         pte_val(pte) = __pa(page) | pgprot_val(pgprot);
 318         return pte;
 319 }
 320
 321 #define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot))
 322
 323 #define mk_pte_phys(physpage, pgprot) \
 324 ({                                                                      \
 325         pte_t __pte;                                                    \
 326                                                                         \
 327         pte_val(__pte) = (physpage) + pgprot_val(pgprot);               \
 328         __pte;                                                          \
 329 })
 330
 331 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 332 {
 333         pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
 334         return pte;
 335 }
 336
 337
 338 /*
 339  * pte_val refers to a page in the 0x0xxxxxxx physical DRAM interval
 340  * __pte_page(pte_val) refers to the "virtual" DRAM interval
 341  * pte_pagenr refers to the page-number counted starting from the virtual
 342  * DRAM start
 343  */
 344
 345 static inline unsigned long __pte_page(pte_t pte)
 346 {
 347         /* the PTE contains a physical address */
 348         return (unsigned long)__va(pte_val(pte) & PAGE_MASK);
 349 }
 350
 351 #define pte_pagenr(pte)         ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
 352
 353 /* permanent address of a page */
 354
 355 #define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
 356 #define pte_page(pte)           (mem_map+pte_pagenr(pte))
 357
 358 /*
 359  * only the pte's themselves need to point to physical DRAM (see above)
 360  * the pagetable links are purely handled within the kernel SW and thus
 361  * don't need the __pa and __va transformations.
 362  */
 363 static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
 364 {
 365         pmd_val(*pmdp) = _KERNPG_TABLE | (unsigned long) ptep;
 366 }
 367
 368 #define pmd_page(pmd)           (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
 369 #define pmd_page_kernel(pmd)    ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 370
 371 /* to find an entry in a page-table-directory. */
 372 #define pgd_index(address)      ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
 373
 374 #define __pgd_offset(address)   pgd_index(address)
 375
 376 #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
 377
 378 /* to find an entry in a kernel page-table-directory */
 379 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 380
 381 #define __pmd_offset(address) \
 382         (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
 383
 384 /*
 385  * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
 386  *
 387  * this macro returns the index of the entry in the pte page which would
 388  * control the given virtual address
 389  */
 390 #define __pte_offset(address)                   \
 391         (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 392 #define pte_offset_kernel(dir, address)         \
 393         ((pte_t *) pmd_page_kernel(*(dir)) +  __pte_offset(address))
 394 #define pte_offset_map(dir, address)            \
 395         ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
 396 #define pte_offset_map_nested(dir, address)     \
 397         pte_offset_map(dir, address)
 398
 399 #define pte_unmap(pte)          do { } while (0)
 400 #define pte_unmap_nested(pte)   do { } while (0)
 401 #define pte_pfn(x)              ((unsigned long)(((x).pte)) >> PAGE_SHIFT)
 402 #define pfn_pte(pfn, prot)  __pte((((pfn) << PAGE_SHIFT)) | pgprot_val(prot))
 403
 404 #define pte_ERROR(e) \
 405         printk(KERN_ERR "%s:%d: bad pte %p(%08lx).\n", \
 406                __FILE__, __LINE__, &(e), pte_val(e))
 407 #define pgd_ERROR(e) \
 408         printk(KERN_ERR "%s:%d: bad pgd %p(%08lx).\n", \
 409                __FILE__, __LINE__, &(e), pgd_val(e))
 410
 411 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
 412
 413 struct vm_area_struct;
 414
 415 static inline void update_tlb(struct vm_area_struct *vma,
 416         unsigned long address, pte_t *pte)
 417 {
 418 }
 419
 420 extern void update_cache(struct vm_area_struct *vma,
 421         unsigned long address, pte_t *pte);
 422
 423 static inline void update_mmu_cache(struct vm_area_struct *vma,
 424         unsigned long address, pte_t *pte)
 425 {
 426         update_tlb(vma, address, pte);
 427         update_cache(vma, address, pte);
 428 }
 429
 430 /* __PHX__ FIXME, SWAP, this probably doesn't work */
 431
 432 /* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
 433 /* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */
 434
 435 #define __swp_type(x)                   (((x).val >> 5) & 0x7f)
 436 #define __swp_offset(x)                 ((x).val >> 12)
 437 #define __swp_entry(type, offset) \
 438         ((swp_entry_t) { ((type) << 5) | ((offset) << 12) })
 439 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
 440 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
 441
 442 #define kern_addr_valid(addr)           (1)
 443
 444 #include <asm-generic/pgtable.h>
 445
 446 /*
 447  * No page table caches to initialise
 448  */
 449 #define pgtable_cache_init()            do { } while (0)
 450
 451 typedef pte_t *pte_addr_t;
 452
 453 #endif /* __ASSEMBLY__ */
 454 #endif /* __ASM_OPENRISC_PGTABLE_H */