arch/openrisc/kernel/setup.c

   1 /*
   2  * OpenRISC setup.c
   3  *
   4  * Linux architectural port borrowing liberally from similar works of
   5  * others.  All original copyrights apply as per the original source
   6  * declaration.
   7  *
   8  * Modifications for the OpenRISC architecture:
   9  * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
  10  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  11  *
  12  *      This program is free software; you can redistribute it and/or
  13  *      modify it under the terms of the GNU General Public License
  14  *      as published by the Free Software Foundation; either version
  15  *      2 of the License, or (at your option) any later version.
  16  *
  17  * This file handles the architecture-dependent parts of initialization
  18  */
  19
  20 #include <linux/errno.h>
  21 #include <linux/sched.h>
  22 #include <linux/kernel.h>
  23 #include <linux/mm.h>
  24 #include <linux/stddef.h>
  25 #include <linux/unistd.h>
  26 #include <linux/ptrace.h>
  27 #include <linux/slab.h>
  28 #include <linux/tty.h>
  29 #include <linux/ioport.h>
  30 #include <linux/delay.h>
  31 #include <linux/console.h>
  32 #include <linux/init.h>
  33 #include <linux/memblock.h>
  34 #include <linux/seq_file.h>
  35 #include <linux/serial.h>
  36 #include <linux/initrd.h>
  37 #include <linux/of_fdt.h>
  38 #include <linux/of.h>
  39 #include <linux/device.h>
  40
  41 #include <asm/sections.h>
  42 #include <asm/segment.h>
  43 #include <asm/pgtable.h>
  44 #include <asm/types.h>
  45 #include <asm/setup.h>
  46 #include <asm/io.h>
  47 #include <asm/cpuinfo.h>
  48 #include <asm/delay.h>
  49
  50 #include "vmlinux.h"
  51
  52 static void __init setup_memory(void)
  53 {
  54         unsigned long ram_start_pfn;
  55         unsigned long ram_end_pfn;
  56         phys_addr_t memory_start, memory_end;
  57         struct memblock_region *region;
  58
  59         memory_end = memory_start = 0;
  60
  61         /* Find main memory where is the kernel, we assume its the only one */
  62         for_each_memblock(memory, region) {
  63                 memory_start = region->base;
  64                 memory_end = region->base + region->size;
  65                 printk(KERN_INFO "%s: Memory: 0x%x-0x%x\n", __func__,
  66                        memory_start, memory_end);
  67         }
  68
  69         if (!memory_end) {
  70                 panic("No memory!");
  71         }
  72
  73         ram_start_pfn = PFN_UP(memory_start);
  74         ram_end_pfn = PFN_DOWN(memblock_end_of_DRAM());
  75
  76         /* setup bootmem globals (we use no_bootmem, but mm still depends on this) */
  77         min_low_pfn = ram_start_pfn;
  78         max_low_pfn = ram_end_pfn;
  79         max_pfn = ram_end_pfn;
  80
  81         /*
  82          * initialize the boot-time allocator (with low memory only).
  83          *
  84          * This makes the memory from the end of the kernel to the end of
  85          * RAM usable.
  86          */
  87         memblock_reserve(__pa(_stext), _end - _stext);
  88
  89         early_init_fdt_reserve_self();
  90         early_init_fdt_scan_reserved_mem();
  91
  92         memblock_dump_all();
  93 }
  94
  95 struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];
  96
  97 static void print_cpuinfo(void)
  98 {
  99         unsigned long upr = mfspr(SPR_UPR);
 100         unsigned long vr = mfspr(SPR_VR);
 101         unsigned int version;
 102         unsigned int revision;
 103         struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
 104
 105         version = (vr & SPR_VR_VER) >> 24;
 106         revision = (vr & SPR_VR_REV);
 107
 108         printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n",
 109                version, revision, cpuinfo->clock_frequency / 1000000);
 110
 111         if (!(upr & SPR_UPR_UP)) {
 112                 printk(KERN_INFO
 113                        "-- no UPR register... unable to detect configuration\n");
 114                 return;
 115         }
 116
 117         if (upr & SPR_UPR_DCP)
 118                 printk(KERN_INFO
 119                        "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n",
 120                        cpuinfo->dcache_size, cpuinfo->dcache_block_size,
 121                        cpuinfo->dcache_ways);
 122         else
 123                 printk(KERN_INFO "-- dcache disabled\n");
 124         if (upr & SPR_UPR_ICP)
 125                 printk(KERN_INFO
 126                        "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n",
 127                        cpuinfo->icache_size, cpuinfo->icache_block_size,
 128                        cpuinfo->icache_ways);
 129         else
 130                 printk(KERN_INFO "-- icache disabled\n");
 131
 132         if (upr & SPR_UPR_DMP)
 133                 printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n",
 134                        1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
 135                        1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
 136         if (upr & SPR_UPR_IMP)
 137                 printk(KERN_INFO "-- immu: %4d entries, %lu way(s)\n",
 138                        1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
 139                        1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW));
 140
 141         printk(KERN_INFO "-- additional features:\n");
 142         if (upr & SPR_UPR_DUP)
 143                 printk(KERN_INFO "-- debug unit\n");
 144         if (upr & SPR_UPR_PCUP)
 145                 printk(KERN_INFO "-- performance counters\n");
 146         if (upr & SPR_UPR_PMP)
 147                 printk(KERN_INFO "-- power management\n");
 148         if (upr & SPR_UPR_PICP)
 149                 printk(KERN_INFO "-- PIC\n");
 150         if (upr & SPR_UPR_TTP)
 151                 printk(KERN_INFO "-- timer\n");
 152         if (upr & SPR_UPR_CUP)
 153                 printk(KERN_INFO "-- custom unit(s)\n");
 154 }
 155
 156 static struct device_node *setup_find_cpu_node(int cpu)
 157 {
 158         u32 hwid;
 159         struct device_node *cpun;
 160
 161         for_each_of_cpu_node(cpun) {
 162                 if (of_property_read_u32(cpun, "reg", &hwid))
 163                         continue;
 164                 if (hwid == cpu)
 165                         return cpun;
 166         }
 167
 168         return NULL;
 169 }
 170
 171 void __init setup_cpuinfo(void)
 172 {
 173         struct device_node *cpu;
 174         unsigned long iccfgr, dccfgr;
 175         unsigned long cache_set_size;
 176         int cpu_id = smp_processor_id();
 177         struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
 178
 179         cpu = setup_find_cpu_node(cpu_id);
 180         if (!cpu)
 181                 panic("Couldn't find CPU%d in device tree...\n", cpu_id);
 182
 183         iccfgr = mfspr(SPR_ICCFGR);
 184         cpuinfo->icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
 185         cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
 186         cpuinfo->icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
 187         cpuinfo->icache_size =
 188             cache_set_size * cpuinfo->icache_ways * cpuinfo->icache_block_size;
 189
 190         dccfgr = mfspr(SPR_DCCFGR);
 191         cpuinfo->dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
 192         cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
 193         cpuinfo->dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
 194         cpuinfo->dcache_size =
 195             cache_set_size * cpuinfo->dcache_ways * cpuinfo->dcache_block_size;
 196
 197         if (of_property_read_u32(cpu, "clock-frequency",
 198                                  &cpuinfo->clock_frequency)) {
 199                 printk(KERN_WARNING
 200                        "Device tree missing CPU 'clock-frequency' parameter."
 201                        "Assuming frequency 25MHZ"
 202                        "This is probably not what you want.");
 203         }
 204
 205         cpuinfo->coreid = mfspr(SPR_COREID);
 206
 207         of_node_put(cpu);
 208
 209         print_cpuinfo();
 210 }
 211
 212 /**
 213  * or32_early_setup
 214  *
 215  * Handles the pointer to the device tree that this kernel is to use
 216  * for establishing the available platform devices.
 217  *
 218  * Falls back on built-in device tree in case null pointer is passed.
 219  */
 220
 221 void __init or32_early_setup(void *fdt)
 222 {
 223         if (fdt)
 224                 pr_info("FDT at %p\n", fdt);
 225         else {
 226                 fdt = __dtb_start;
 227                 pr_info("Compiled-in FDT at %p\n", fdt);
 228         }
 229         early_init_devtree(fdt);
 230 }
 231
 232 static inline unsigned long extract_value_bits(unsigned long reg,
 233                                                short bit_nr, short width)
 234 {
 235         return (reg >> bit_nr) & (0 << width);
 236 }
 237
 238 static inline unsigned long extract_value(unsigned long reg, unsigned long mask)
 239 {
 240         while (!(mask & 0x1)) {
 241                 reg = reg >> 1;
 242                 mask = mask >> 1;
 243         }
 244         return mask & reg;
 245 }
 246
 247 void __init detect_unit_config(unsigned long upr, unsigned long mask,
 248                                char *text, void (*func) (void))
 249 {
 250         if (text != NULL)
 251                 printk("%s", text);
 252
 253         if (upr & mask) {
 254                 if (func != NULL)
 255                         func();
 256                 else
 257                         printk("present\n");
 258         } else
 259                 printk("not present\n");
 260 }
 261
 262 /*
 263  * calibrate_delay
 264  *
 265  * Lightweight calibrate_delay implementation that calculates loops_per_jiffy
 266  * from the clock frequency passed in via the device tree
 267  *
 268  */
 269
 270 void calibrate_delay(void)
 271 {
 272         const int *val;
 273         struct device_node *cpu = setup_find_cpu_node(smp_processor_id());
 274
 275         val = of_get_property(cpu, "clock-frequency", NULL);
 276         if (!val)
 277                 panic("no cpu 'clock-frequency' parameter in device tree");
 278         loops_per_jiffy = *val / HZ;
 279         pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n",
 280                 loops_per_jiffy / (500000 / HZ),
 281                 (loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy);
 282 }
 283
 284 void __init setup_arch(char **cmdline_p)
 285 {
 286         unflatten_and_copy_device_tree();
 287
 288         setup_cpuinfo();
 289
 290 #ifdef CONFIG_SMP
 291         smp_init_cpus();
 292 #endif
 293
 294         /* process 1's initial memory region is the kernel code/data */
 295         init_mm.start_code = (unsigned long)_stext;
 296         init_mm.end_code = (unsigned long)_etext;
 297         init_mm.end_data = (unsigned long)_edata;
 298         init_mm.brk = (unsigned long)_end;
 299
 300 #ifdef CONFIG_BLK_DEV_INITRD
 301         initrd_start = (unsigned long)&__initrd_start;
 302         initrd_end = (unsigned long)&__initrd_end;
 303         if (initrd_start == initrd_end) {
 304                 initrd_start = 0;
 305                 initrd_end = 0;
 306         }
 307         initrd_below_start_ok = 1;
 308 #endif
 309
 310         /* setup memblock allocator */
 311         setup_memory();
 312
 313         /* paging_init() sets up the MMU and marks all pages as reserved */
 314         paging_init();
 315
 316 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
 317         if (!conswitchp)
 318                 conswitchp = &dummy_con;
 319 #endif
 320
 321         *cmdline_p = boot_command_line;
 322
 323         printk(KERN_INFO "OpenRISC Linux -- http://openrisc.io\n");
 324 }
 325
 326 static int show_cpuinfo(struct seq_file *m, void *v)
 327 {
 328         unsigned int vr, cpucfgr;
 329         unsigned int avr;
 330         unsigned int version;
 331         struct cpuinfo_or1k *cpuinfo = v;
 332
 333         vr = mfspr(SPR_VR);
 334         cpucfgr = mfspr(SPR_CPUCFGR);
 335
 336 #ifdef CONFIG_SMP
 337         seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid);
 338 #endif
 339         if (vr & SPR_VR_UVRP) {
 340                 vr = mfspr(SPR_VR2);
 341                 version = vr & SPR_VR2_VER;
 342                 avr = mfspr(SPR_AVR);
 343                 seq_printf(m, "cpu architecture\t: "
 344                            "OpenRISC 1000 (%d.%d-rev%d)\n",
 345                            (avr >> 24) & 0xff,
 346                            (avr >> 16) & 0xff,
 347                            (avr >> 8) & 0xff);
 348                 seq_printf(m, "cpu implementation id\t: 0x%x\n",
 349                            (vr & SPR_VR2_CPUID) >> 24);
 350                 seq_printf(m, "cpu version\t\t: 0x%x\n", version);
 351         } else {
 352                 version = (vr & SPR_VR_VER) >> 24;
 353                 seq_printf(m, "cpu\t\t\t: OpenRISC-%x\n", version);
 354                 seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
 355         }
 356         seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
 357         seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache_size);
 358         seq_printf(m, "dcache block size\t: %d bytes\n",
 359                    cpuinfo->dcache_block_size);
 360         seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache_ways);
 361         seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache_size);
 362         seq_printf(m, "icache block size\t: %d bytes\n",
 363                    cpuinfo->icache_block_size);
 364         seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache_ways);
 365         seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
 366                    1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
 367                    1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
 368         seq_printf(m, "dmmu\t\t\t: %d entries, %lu ways\n",
 369                    1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
 370                    1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW));
 371         seq_printf(m, "bogomips\t\t: %lu.%02lu\n",
 372                    (loops_per_jiffy * HZ) / 500000,
 373                    ((loops_per_jiffy * HZ) / 5000) % 100);
 374
 375         seq_puts(m, "features\t\t: ");
 376         seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB32S ? "orbis32" : "");
 377         seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB64S ? "orbis64" : "");
 378         seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF32S ? "orfpx32" : "");
 379         seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF64S ? "orfpx64" : "");
 380         seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OV64S ? "orvdx64" : "");
 381         seq_puts(m, "\n");
 382
 383         seq_puts(m, "\n");
 384
 385         return 0;
 386 }
 387
 388 static void *c_start(struct seq_file *m, loff_t *pos)
 389 {
 390         *pos = cpumask_next(*pos - 1, cpu_online_mask);
 391         if ((*pos) < nr_cpu_ids)
 392                 return &cpuinfo_or1k[*pos];
 393         return NULL;
 394 }
 395
 396 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 397 {
 398         (*pos)++;
 399         return c_start(m, pos);
 400 }
 401
 402 static void c_stop(struct seq_file *m, void *v)
 403 {
 404 }
 405
 406 const struct seq_operations cpuinfo_op = {
 407         .start = c_start,
 408         .next = c_next,
 409         .stop = c_stop,
 410         .show = show_cpuinfo,
 411 };