arch/parisc/include/uapi/asm/pdc.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2 #ifndef _UAPI_PARISC_PDC_H
   3 #define _UAPI_PARISC_PDC_H
   4
   5 /*
   6  *      PDC return values ...
   7  *      All PDC calls return a subset of these errors.
   8  */
   9
  10 #define PDC_WARN                  3     /* Call completed with a warning */
  11 #define PDC_REQ_ERR_1             2     /* See above                     */
  12 #define PDC_REQ_ERR_0             1     /* Call would generate a requestor error */
  13 #define PDC_OK                    0     /* Call completed successfully  */
  14 #define PDC_BAD_PROC             -1     /* Called non-existent procedure*/
  15 #define PDC_BAD_OPTION           -2     /* Called with non-existent option */
  16 #define PDC_ERROR                -3     /* Call could not complete without an error */
  17 #define PDC_NE_MOD               -5     /* Module not found             */
  18 #define PDC_NE_CELL_MOD          -7     /* Cell module not found        */
  19 #define PDC_INVALID_ARG         -10     /* Called with an invalid argument */
  20 #define PDC_BUS_POW_WARN        -12     /* Call could not complete in allowed power budget */
  21 #define PDC_NOT_NARROW          -17     /* Narrow mode not supported    */
  22
  23 /*
  24  *      PDC entry points...
  25  */
  26
  27 #define PDC_POW_FAIL    1               /* perform a power-fail         */
  28 #define PDC_POW_FAIL_PREPARE    0       /* prepare for powerfail        */
  29
  30 #define PDC_CHASSIS     2               /* PDC-chassis functions        */
  31 #define PDC_CHASSIS_DISP        0       /* update chassis display       */
  32 #define PDC_CHASSIS_WARN        1       /* return chassis warnings      */
  33 #define PDC_CHASSIS_DISPWARN    2       /* update&return chassis status */
  34 #define PDC_RETURN_CHASSIS_INFO 128     /* HVERSION dependent: return chassis LED/LCD info  */
  35
  36 #define PDC_PIM         3               /* Get PIM data                 */
  37 #define PDC_PIM_HPMC            0       /* Transfer HPMC data           */
  38 #define PDC_PIM_RETURN_SIZE     1       /* Get Max buffer needed for PIM*/
  39 #define PDC_PIM_LPMC            2       /* Transfer HPMC data           */
  40 #define PDC_PIM_SOFT_BOOT       3       /* Transfer Soft Boot data      */
  41 #define PDC_PIM_TOC             4       /* Transfer TOC data            */
  42
  43 #define PDC_MODEL       4               /* PDC model information call   */
  44 #define PDC_MODEL_INFO          0       /* returns information          */
  45 #define PDC_MODEL_BOOTID        1       /* set the BOOT_ID              */
  46 #define PDC_MODEL_VERSIONS      2       /* returns cpu-internal versions*/
  47 #define PDC_MODEL_SYSMODEL      3       /* return system model info     */
  48 #define PDC_MODEL_ENSPEC        4       /* enable specific option       */
  49 #define PDC_MODEL_DISPEC        5       /* disable specific option      */
  50 #define PDC_MODEL_CPU_ID        6       /* returns cpu-id (only newer machines!) */
  51 #define PDC_MODEL_CAPABILITIES  7       /* returns OS32/OS64-flags      */
  52 /* Values for PDC_MODEL_CAPABILITIES non-equivalent virtual aliasing support */
  53 #define  PDC_MODEL_OS64                 (1 << 0)
  54 #define  PDC_MODEL_OS32                 (1 << 1)
  55 #define  PDC_MODEL_IOPDIR_FDC           (1 << 2)
  56 #define  PDC_MODEL_NVA_MASK             (3 << 4)
  57 #define  PDC_MODEL_NVA_SUPPORTED        (0 << 4)
  58 #define  PDC_MODEL_NVA_SLOW             (1 << 4)
  59 #define  PDC_MODEL_NVA_UNSUPPORTED      (3 << 4)
  60 #define PDC_MODEL_GET_BOOT__OP  8       /* returns boot test options    */
  61 #define PDC_MODEL_SET_BOOT__OP  9       /* set boot test options        */
  62
  63 #define PA89_INSTRUCTION_SET    0x4     /* capabilities returned        */
  64 #define PA90_INSTRUCTION_SET    0x8
  65
  66 #define PDC_CACHE       5               /* return/set cache (& TLB) info*/
  67 #define PDC_CACHE_INFO          0       /* returns information          */
  68 #define PDC_CACHE_SET_COH       1       /* set coherence state          */
  69 #define PDC_CACHE_RET_SPID      2       /* returns space-ID bits        */
  70
  71 #define PDC_HPA         6               /* return HPA of processor      */
  72 #define PDC_HPA_PROCESSOR       0
  73 #define PDC_HPA_MODULES         1
  74
  75 #define PDC_COPROC      7               /* Co-Processor (usually FP unit(s)) */
  76 #define PDC_COPROC_CFG          0       /* Co-Processor Cfg (FP unit(s) enabled?) */
  77
  78 #define PDC_IODC        8               /* talk to IODC                 */
  79 #define PDC_IODC_READ           0       /* read IODC entry point        */
  80 /*      PDC_IODC_RI_                     * INDEX parameter of PDC_IODC_READ */
  81 #define PDC_IODC_RI_DATA_BYTES  0       /* IODC Data Bytes              */
  82 /*                              1, 2       obsolete - HVERSION dependent*/
  83 #define PDC_IODC_RI_INIT        3       /* Initialize module            */
  84 #define PDC_IODC_RI_IO          4       /* Module input/output          */
  85 #define PDC_IODC_RI_SPA         5       /* Module input/output          */
  86 #define PDC_IODC_RI_CONFIG      6       /* Module input/output          */
  87 /*                              7         obsolete - HVERSION dependent */
  88 #define PDC_IODC_RI_TEST        8       /* Module input/output          */
  89 #define PDC_IODC_RI_TLB         9       /* Module input/output          */
  90 #define PDC_IODC_NINIT          2       /* non-destructive init         */
  91 #define PDC_IODC_DINIT          3       /* destructive init             */
  92 #define PDC_IODC_MEMERR         4       /* check for memory errors      */
  93 #define PDC_IODC_INDEX_DATA     0       /* get first 16 bytes from mod IODC */
  94 #define PDC_IODC_BUS_ERROR      -4      /* bus error return value       */
  95 #define PDC_IODC_INVALID_INDEX  -5      /* invalid index return value   */
  96 #define PDC_IODC_COUNT          -6      /* count is too small           */
  97
  98 #define PDC_TOD         9               /* time-of-day clock (TOD)      */
  99 #define PDC_TOD_READ            0       /* read TOD                     */
 100 #define PDC_TOD_WRITE           1       /* write TOD                    */
 101
 102
 103 #define PDC_STABLE      10              /* stable storage (sprockets)   */
 104 #define PDC_STABLE_READ         0
 105 #define PDC_STABLE_WRITE        1
 106 #define PDC_STABLE_RETURN_SIZE  2
 107 #define PDC_STABLE_VERIFY_CONTENTS 3
 108 #define PDC_STABLE_INITIALIZE   4
 109
 110 #define PDC_NVOLATILE   11              /* often not implemented        */
 111
 112 #define PDC_ADD_VALID   12              /* Memory validation PDC call   */
 113 #define PDC_ADD_VALID_VERIFY    0       /* Make PDC_ADD_VALID verify region */
 114
 115 #define PDC_INSTR       15              /* get instr to invoke PDCE_CHECK() */
 116
 117 #define PDC_PROC        16              /* (sprockets)                  */
 118
 119 #define PDC_CONFIG      16              /* (sprockets)                  */
 120 #define PDC_CONFIG_DECONFIG     0
 121 #define PDC_CONFIG_DRECONFIG    1
 122 #define PDC_CONFIG_DRETURN_CONFIG 2
 123
 124 #define PDC_BLOCK_TLB   18              /* manage hardware block-TLB    */
 125 #define PDC_BTLB_INFO           0       /* returns parameter            */
 126 #define PDC_BTLB_INSERT         1       /* insert BTLB entry            */
 127 #define PDC_BTLB_PURGE          2       /* purge BTLB entries           */
 128 #define PDC_BTLB_PURGE_ALL      3       /* purge all BTLB entries       */
 129
 130 #define PDC_TLB         19              /* manage hardware TLB miss handling */
 131 #define PDC_TLB_INFO            0       /* returns parameter            */
 132 #define PDC_TLB_SETUP           1       /* set up miss handling         */
 133
 134 #define PDC_MEM         20              /* Manage memory                */
 135 #define PDC_MEM_MEMINFO         0       /* Return PDT info              */
 136 #define PDC_MEM_ADD_PAGE        1       /* Add page to PDT              */
 137 #define PDC_MEM_CLEAR_PDT       2       /* Clear PDT                    */
 138 #define PDC_MEM_READ_PDT        3       /* Read PDT entry               */
 139 #define PDC_MEM_RESET_CLEAR     4       /* Reset PDT clear flag         */
 140 #define PDC_MEM_GOODMEM         5       /* Set good_mem value           */
 141 #define PDC_MEM_TABLE           128     /* Non contig mem map (sprockets) */
 142 #define PDC_MEM_RETURN_ADDRESS_TABLE    PDC_MEM_TABLE
 143 #define PDC_MEM_GET_MEMORY_SYSTEM_TABLES_SIZE   131
 144 #define PDC_MEM_GET_MEMORY_SYSTEM_TABLES        132
 145 #define PDC_MEM_GET_PHYSICAL_LOCATION_FROM_MEMORY_ADDRESS 133
 146
 147 #define PDC_MEM_RET_SBE_REPLACED        5       /* PDC_MEM return values */
 148 #define PDC_MEM_RET_DUPLICATE_ENTRY     4
 149 #define PDC_MEM_RET_BUF_SIZE_SMALL      1
 150 #define PDC_MEM_RET_PDT_FULL            -11
 151 #define PDC_MEM_RET_INVALID_PHYSICAL_LOCATION ~0ULL
 152
 153 #define PDC_PSW         21              /* Get/Set default System Mask  */
 154 #define PDC_PSW_MASK            0       /* Return mask                  */
 155 #define PDC_PSW_GET_DEFAULTS    1       /* Return defaults              */
 156 #define PDC_PSW_SET_DEFAULTS    2       /* Set default                  */
 157 #define PDC_PSW_ENDIAN_BIT      1       /* set for big endian           */
 158 #define PDC_PSW_WIDE_BIT        2       /* set for wide mode            */
 159
 160 #define PDC_SYSTEM_MAP  22              /* find system modules          */
 161 #define PDC_FIND_MODULE         0
 162 #define PDC_FIND_ADDRESS        1
 163 #define PDC_TRANSLATE_PATH      2
 164
 165 #define PDC_SOFT_POWER  23              /* soft power switch            */
 166 #define PDC_SOFT_POWER_INFO     0       /* return info about the soft power switch */
 167 #define PDC_SOFT_POWER_ENABLE   1       /* enable/disable soft power switch */
 168
 169
 170 /* HVERSION dependent */
 171
 172 /* The PDC_MEM_MAP calls */
 173 #define PDC_MEM_MAP     128             /* on s700: return page info    */
 174 #define PDC_MEM_MAP_HPA         0       /* returns hpa of a module      */
 175
 176 #define PDC_EEPROM      129             /* EEPROM access                */
 177 #define PDC_EEPROM_READ_WORD    0
 178 #define PDC_EEPROM_WRITE_WORD   1
 179 #define PDC_EEPROM_READ_BYTE    2
 180 #define PDC_EEPROM_WRITE_BYTE   3
 181 #define PDC_EEPROM_EEPROM_PASSWORD -1000
 182
 183 #define PDC_NVM         130             /* NVM (non-volatile memory) access */
 184 #define PDC_NVM_READ_WORD       0
 185 #define PDC_NVM_WRITE_WORD      1
 186 #define PDC_NVM_READ_BYTE       2
 187 #define PDC_NVM_WRITE_BYTE      3
 188
 189 #define PDC_SEED_ERROR  132             /* (sprockets)                  */
 190
 191 #define PDC_IO          135             /* log error info, reset IO system */
 192 #define PDC_IO_READ_AND_CLEAR_ERRORS    0
 193 #define PDC_IO_RESET                    1
 194 #define PDC_IO_RESET_DEVICES            2
 195 /* sets bits 6&7 (little endian) of the HcControl Register */
 196 #define PDC_IO_USB_SUSPEND      0xC000000000000000
 197 #define PDC_IO_EEPROM_IO_ERR_TABLE_FULL -5      /* return value */
 198 #define PDC_IO_NO_SUSPEND               -6      /* return value */
 199
 200 #define PDC_BROADCAST_RESET 136         /* reset all processors         */
 201 #define PDC_DO_RESET            0       /* option: perform a broadcast reset */
 202 #define PDC_DO_FIRM_TEST_RESET  1       /* Do broadcast reset with bitmap */
 203 #define PDC_BR_RECONFIGURATION  2       /* reset w/reconfiguration      */
 204 #define PDC_FIRM_TEST_MAGIC     0xab9ec36fUL    /* for this reboot only */
 205
 206 #define PDC_LAN_STATION_ID 138          /* Hversion dependent mechanism for */
 207 #define PDC_LAN_STATION_ID_READ 0       /* getting the lan station address  */
 208
 209 #define PDC_LAN_STATION_ID_SIZE 6
 210
 211 #define PDC_CHECK_RANGES 139            /* (sprockets)                  */
 212
 213 #define PDC_NV_SECTIONS 141             /* (sprockets)                  */
 214
 215 #define PDC_PERFORMANCE 142             /* performance monitoring       */
 216
 217 #define PDC_SYSTEM_INFO 143             /* system information           */
 218 #define PDC_SYSINFO_RETURN_INFO_SIZE    0
 219 #define PDC_SYSINFO_RRETURN_SYS_INFO    1
 220 #define PDC_SYSINFO_RRETURN_ERRORS      2
 221 #define PDC_SYSINFO_RRETURN_WARNINGS    3
 222 #define PDC_SYSINFO_RETURN_REVISIONS    4
 223 #define PDC_SYSINFO_RRETURN_DIAGNOSE    5
 224 #define PDC_SYSINFO_RRETURN_HV_DIAGNOSE 1005
 225
 226 #define PDC_RDR         144             /* (sprockets)                  */
 227 #define PDC_RDR_READ_BUFFER     0
 228 #define PDC_RDR_READ_SINGLE     1
 229 #define PDC_RDR_WRITE_SINGLE    2
 230
 231 #define PDC_INTRIGUE    145             /* (sprockets)                  */
 232 #define PDC_INTRIGUE_WRITE_BUFFER        0
 233 #define PDC_INTRIGUE_GET_SCRATCH_BUFSIZE 1
 234 #define PDC_INTRIGUE_START_CPU_COUNTERS  2
 235 #define PDC_INTRIGUE_STOP_CPU_COUNTERS   3
 236
 237 #define PDC_STI         146             /* STI access                   */
 238 /* same as PDC_PCI_XXX values (see below) */
 239
 240 /* Legacy PDC definitions for same stuff */
 241 #define PDC_PCI_INDEX   147
 242 #define PDC_PCI_INTERFACE_INFO          0
 243 #define PDC_PCI_SLOT_INFO               1
 244 #define PDC_PCI_INFLIGHT_BYTES          2
 245 #define PDC_PCI_READ_CONFIG             3
 246 #define PDC_PCI_WRITE_CONFIG            4
 247 #define PDC_PCI_READ_PCI_IO             5
 248 #define PDC_PCI_WRITE_PCI_IO            6
 249 #define PDC_PCI_READ_CONFIG_DELAY       7
 250 #define PDC_PCI_UPDATE_CONFIG_DELAY     8
 251 #define PDC_PCI_PCI_PATH_TO_PCI_HPA     9
 252 #define PDC_PCI_PCI_HPA_TO_PCI_PATH     10
 253 #define PDC_PCI_PCI_PATH_TO_PCI_BUS     11
 254 #define PDC_PCI_PCI_RESERVED            12
 255 #define PDC_PCI_PCI_INT_ROUTE_SIZE      13
 256 #define PDC_PCI_GET_INT_TBL_SIZE        PDC_PCI_PCI_INT_ROUTE_SIZE
 257 #define PDC_PCI_PCI_INT_ROUTE           14
 258 #define PDC_PCI_GET_INT_TBL             PDC_PCI_PCI_INT_ROUTE
 259 #define PDC_PCI_READ_MON_TYPE           15
 260 #define PDC_PCI_WRITE_MON_TYPE          16
 261
 262
 263 /* Get SCSI Interface Card info:  SDTR, SCSI ID, mode (SE vs LVD) */
 264 #define PDC_INITIATOR   163
 265 #define PDC_GET_INITIATOR       0
 266 #define PDC_SET_INITIATOR       1
 267 #define PDC_DELETE_INITIATOR    2
 268 #define PDC_RETURN_TABLE_SIZE   3
 269 #define PDC_RETURN_TABLE        4
 270
 271 #define PDC_LINK        165             /* (sprockets)                  */
 272 #define PDC_LINK_PCI_ENTRY_POINTS       0  /* list (Arg1) = 0 */
 273 #define PDC_LINK_USB_ENTRY_POINTS       1  /* list (Arg1) = 1 */
 274
 275 /* cl_class
 276  * page 3-33 of IO-Firmware ARS
 277  * IODC ENTRY_INIT(Search first) RET[1]
 278  */
 279 #define CL_NULL         0       /* invalid */
 280 #define CL_RANDOM       1       /* random access (as disk) */
 281 #define CL_SEQU         2       /* sequential access (as tape) */
 282 #define CL_DUPLEX       7       /* full-duplex point-to-point (RS-232, Net) */
 283 #define CL_KEYBD        8       /* half-duplex console (HIL Keyboard) */
 284 #define CL_DISPL        9       /* half-duplex console (display) */
 285 #define CL_FC           10      /* FiberChannel access media */
 286
 287 /* IODC ENTRY_INIT() */
 288 #define ENTRY_INIT_SRCH_FRST    2
 289 #define ENTRY_INIT_SRCH_NEXT    3
 290 #define ENTRY_INIT_MOD_DEV      4
 291 #define ENTRY_INIT_DEV          5
 292 #define ENTRY_INIT_MOD          6
 293 #define ENTRY_INIT_MSG          9
 294
 295 /* IODC ENTRY_IO() */
 296 #define ENTRY_IO_BOOTIN         0
 297 #define ENTRY_IO_BOOTOUT        1
 298 #define ENTRY_IO_CIN            2
 299 #define ENTRY_IO_COUT           3
 300 #define ENTRY_IO_CLOSE          4
 301 #define ENTRY_IO_GETMSG         9
 302 #define ENTRY_IO_BBLOCK_IN      16
 303 #define ENTRY_IO_BBLOCK_OUT     17
 304
 305 /* IODC ENTRY_SPA() */
 306
 307 /* IODC ENTRY_CONFIG() */
 308
 309 /* IODC ENTRY_TEST() */
 310
 311 /* IODC ENTRY_TLB() */
 312
 313 /* constants for OS (NVM...) */
 314 #define OS_ID_NONE              0       /* Undefined OS ID      */
 315 #define OS_ID_HPUX              1       /* HP-UX OS             */
 316 #define OS_ID_MPEXL             2       /* MPE XL OS            */
 317 #define OS_ID_OSF               3       /* OSF OS               */
 318 #define OS_ID_HPRT              4       /* HP-RT OS             */
 319 #define OS_ID_NOVEL             5       /* NOVELL OS            */
 320 #define OS_ID_LINUX             6       /* Linux                */
 321
 322
 323 /* constants for PDC_CHASSIS */
 324 #define OSTAT_OFF               0
 325 #define OSTAT_FLT               1
 326 #define OSTAT_TEST              2
 327 #define OSTAT_INIT              3
 328 #define OSTAT_SHUT              4
 329 #define OSTAT_WARN              5
 330 #define OSTAT_RUN               6
 331 #define OSTAT_ON                7
 332
 333 /* Page Zero constant offsets used by the HPMC handler */
 334 #define BOOT_CONSOLE_HPA_OFFSET  0x3c0
 335 #define BOOT_CONSOLE_SPA_OFFSET  0x3c4
 336 #define BOOT_CONSOLE_PATH_OFFSET 0x3a8
 337
 338 /* size of the pdc_result buffer for firmware.c */
 339 #define NUM_PDC_RESULT  32
 340
 341 #if !defined(__ASSEMBLY__)
 342
 343 #include <linux/types.h>
 344
 345
 346 /* flags of the device_path */
 347 #define PF_AUTOBOOT     0x80
 348 #define PF_AUTOSEARCH   0x40
 349 #define PF_TIMER        0x0F
 350
 351 struct device_path {            /* page 1-69 */
 352         unsigned char flags;    /* flags see above! */
 353         unsigned char bc[6];    /* bus converter routing info */
 354         unsigned char mod;
 355         unsigned int  layers[6];/* device-specific layer-info */
 356 } __attribute__((aligned(8))) ;
 357
 358 struct pz_device {
 359         struct  device_path dp; /* see above */
 360         /* struct       iomod *hpa; */
 361         unsigned int hpa;       /* HPA base address */
 362         /* char *spa; */
 363         unsigned int spa;       /* SPA base address */
 364         /* int  (*iodc_io)(struct iomod*, ...); */
 365         unsigned int iodc_io;   /* device entry point */
 366         short   pad;            /* reserved */
 367         unsigned short cl_class;/* see below */
 368 } __attribute__((aligned(8))) ;
 369
 370 struct zeropage {
 371         /* [0x000] initialize vectors (VEC) */
 372         unsigned int    vec_special;            /* must be zero */
 373         /* int  (*vec_pow_fail)(void);*/
 374         unsigned int    vec_pow_fail; /* power failure handler */
 375         /* int  (*vec_toc)(void); */
 376         unsigned int    vec_toc;
 377         unsigned int    vec_toclen;
 378         /* int  (*vec_rendz)(void); */
 379         unsigned int vec_rendz;
 380         int     vec_pow_fail_flen;
 381         int     vec_pad[10];
 382
 383         /* [0x040] reserved processor dependent */
 384         int     pad0[112];
 385
 386         /* [0x200] reserved */
 387         int     pad1[84];
 388
 389         /* [0x350] memory configuration (MC) */
 390         int     memc_cont;              /* contiguous mem size (bytes) */
 391         int     memc_phsize;            /* physical memory size */
 392         int     memc_adsize;            /* additional mem size, bytes of SPA space used by PDC */
 393         unsigned int mem_pdc_hi;        /* used for 64-bit */
 394
 395         /* [0x360] various parameters for the boot-CPU */
 396         /* unsigned int *mem_booterr[8]; */
 397         unsigned int mem_booterr[8];    /* ptr to boot errors */
 398         unsigned int mem_free;          /* first location, where OS can be loaded */
 399         /* struct iomod *mem_hpa; */
 400         unsigned int mem_hpa;           /* HPA of the boot-CPU */
 401         /* int (*mem_pdc)(int, ...); */
 402         unsigned int mem_pdc;           /* PDC entry point */
 403         unsigned int mem_10msec;        /* number of clock ticks in 10msec */
 404
 405         /* [0x390] initial memory module (IMM) */
 406         /* struct iomod *imm_hpa; */
 407         unsigned int imm_hpa;           /* HPA of the IMM */
 408         int     imm_soft_boot;          /* 0 = was hard boot, 1 = was soft boot */
 409         unsigned int    imm_spa_size;           /* SPA size of the IMM in bytes */
 410         unsigned int    imm_max_mem;            /* bytes of mem in IMM */
 411
 412         /* [0x3A0] boot console, display device and keyboard */
 413         struct pz_device mem_cons;      /* description of console device */
 414         struct pz_device mem_boot;      /* description of boot device */
 415         struct pz_device mem_kbd;       /* description of keyboard device */
 416
 417         /* [0x430] reserved */
 418         int     pad430[116];
 419
 420         /* [0x600] processor dependent */
 421         __u32   pad600[1];
 422         __u32   proc_sti;               /* pointer to STI ROM */
 423         __u32   pad608[126];
 424 };
 425
 426 #endif /* !defined(__ASSEMBLY__) */
 427
 428 #endif /* _UAPI_PARISC_PDC_H */