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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Code to handle x86 style IRQs plus some generic interrupt stuff.
4 *
5 * Copyright (C) 1992 Linus Torvalds
6 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
7 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
8 * Copyright (C) 1999-2000 Grant Grundler
9 * Copyright (c) 2005 Matthew Wilcox
10 */
11 #include <linux/bitops.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/types.h>
18 #include <asm/io.h>
19
20 #include <asm/smp.h>
21 #include <asm/ldcw.h>
22
23 #undef PARISC_IRQ_CR16_COUNTS
24
25 extern irqreturn_t timer_interrupt(int, void *);
26 extern irqreturn_t ipi_interrupt(int, void *);
27
28 #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
29
30 /* Bits in EIEM correlate with cpu_irq_action[].
31 ** Numbered *Big Endian*! (ie bit 0 is MSB)
32 */
33 static volatile unsigned long cpu_eiem = 0;
34
35 /*
36 ** local ACK bitmap ... habitually set to 1, but reset to zero
37 ** between ->ack() and ->end() of the interrupt to prevent
38 ** re-interruption of a processing interrupt.
39 */
40 static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;
41
42 static void cpu_mask_irq(struct irq_data *d)
43 {
44 unsigned long eirr_bit = EIEM_MASK(d->irq);
45
46 cpu_eiem &= ~eirr_bit;
47 /* Do nothing on the other CPUs. If they get this interrupt,
48 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
49 * handle it, and the set_eiem() at the bottom will ensure it
50 * then gets disabled */
51 }
52
53 static void __cpu_unmask_irq(unsigned int irq)
54 {
55 unsigned long eirr_bit = EIEM_MASK(irq);
56
57 cpu_eiem |= eirr_bit;
58
59 /* This is just a simple NOP IPI. But what it does is cause
60 * all the other CPUs to do a set_eiem(cpu_eiem) at the end
61 * of the interrupt handler */
62 smp_send_all_nop();
63 }
64
65 static void cpu_unmask_irq(struct irq_data *d)
66 {
67 __cpu_unmask_irq(d->irq);
68 }
69
70 void cpu_ack_irq(struct irq_data *d)
71 {
72 unsigned long mask = EIEM_MASK(d->irq);
73 int cpu = smp_processor_id();
74
75 /* Clear in EIEM so we can no longer process */
76 per_cpu(local_ack_eiem, cpu) &= ~mask;
77
78 /* disable the interrupt */
79 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
80
81 /* and now ack it */
82 mtctl(mask, 23);
83 }
84
85 void cpu_eoi_irq(struct irq_data *d)
86 {
87 unsigned long mask = EIEM_MASK(d->irq);
88 int cpu = smp_processor_id();
89
90 /* set it in the eiems---it's no longer in process */
91 per_cpu(local_ack_eiem, cpu) |= mask;
92
93 /* enable the interrupt */
94 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
95 }
96
97 #ifdef CONFIG_SMP
98 int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest)
99 {
100 int cpu_dest;
101
102 /* timer and ipi have to always be received on all CPUs */
103 if (irqd_is_per_cpu(d))
104 return -EINVAL;
105
106 /* whatever mask they set, we just allow one CPU */
107 cpu_dest = cpumask_next_and(d->irq & (num_online_cpus()-1),
108 dest, cpu_online_mask);
109 if (cpu_dest >= nr_cpu_ids)
110 cpu_dest = cpumask_first_and(dest, cpu_online_mask);
111
112 return cpu_dest;
113 }
114
115 static int cpu_set_affinity_irq(struct irq_data *d, const struct cpumask *dest,
116 bool force)
117 {
118 int cpu_dest;
119
120 cpu_dest = cpu_check_affinity(d, dest);
121 if (cpu_dest < 0)
122 return -1;
123
124 cpumask_copy(irq_data_get_affinity_mask(d), dest);
125
126 return 0;
127 }
128 #endif
129
130 static struct irq_chip cpu_interrupt_type = {
131 .name = "CPU",
132 .irq_mask = cpu_mask_irq,
133 .irq_unmask = cpu_unmask_irq,
134 .irq_ack = cpu_ack_irq,
135 .irq_eoi = cpu_eoi_irq,
136 #ifdef CONFIG_SMP
137 .irq_set_affinity = cpu_set_affinity_irq,
138 #endif
139 /* XXX: Needs to be written. We managed without it so far, but
140 * we really ought to write it.
141 */
142 .irq_retrigger = NULL,
143 };
144
145 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
146 #define irq_stats(x) (&per_cpu(irq_stat, x))
147
148 /*
149 * /proc/interrupts printing for arch specific interrupts
150 */
151 int arch_show_interrupts(struct seq_file *p, int prec)
152 {
153 int j;
154
155 #ifdef CONFIG_DEBUG_STACKOVERFLOW
156 seq_printf(p, "%*s: ", prec, "STK");
157 for_each_online_cpu(j)
158 seq_printf(p, "%10u ", irq_stats(j)->kernel_stack_usage);
159 seq_puts(p, " Kernel stack usage\n");
160 # ifdef CONFIG_IRQSTACKS
161 seq_printf(p, "%*s: ", prec, "IST");
162 for_each_online_cpu(j)
163 seq_printf(p, "%10u ", irq_stats(j)->irq_stack_usage);
164 seq_puts(p, " Interrupt stack usage\n");
165 # endif
166 #endif
167 #ifdef CONFIG_SMP
168 if (num_online_cpus() > 1) {
169 seq_printf(p, "%*s: ", prec, "RES");
170 for_each_online_cpu(j)
171 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
172 seq_puts(p, " Rescheduling interrupts\n");
173 seq_printf(p, "%*s: ", prec, "CAL");
174 for_each_online_cpu(j)
175 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
176 seq_puts(p, " Function call interrupts\n");
177 }
178 #endif
179 seq_printf(p, "%*s: ", prec, "UAH");
180 for_each_online_cpu(j)
181 seq_printf(p, "%10u ", irq_stats(j)->irq_unaligned_count);
182 seq_puts(p, " Unaligned access handler traps\n");
183 seq_printf(p, "%*s: ", prec, "FPA");
184 for_each_online_cpu(j)
185 seq_printf(p, "%10u ", irq_stats(j)->irq_fpassist_count);
186 seq_puts(p, " Floating point assist traps\n");
187 seq_printf(p, "%*s: ", prec, "TLB");
188 for_each_online_cpu(j)
189 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
190 seq_puts(p, " TLB shootdowns\n");
191 return 0;
192 }
193
194 int show_interrupts(struct seq_file *p, void *v)
195 {
196 int i = *(loff_t *) v, j;
197 unsigned long flags;
198
199 if (i == 0) {
200 seq_puts(p, " ");
201 for_each_online_cpu(j)
202 seq_printf(p, " CPU%d", j);
203
204 #ifdef PARISC_IRQ_CR16_COUNTS
205 seq_printf(p, " [min/avg/max] (CPU cycle counts)");
206 #endif
207 seq_putc(p, '\n');
208 }
209
210 if (i < NR_IRQS) {
211 struct irq_desc *desc = irq_to_desc(i);
212 struct irqaction *action;
213
214 raw_spin_lock_irqsave(&desc->lock, flags);
215 action = desc->action;
216 if (!action)
217 goto skip;
218 seq_printf(p, "%3d: ", i);
219
220 for_each_online_cpu(j)
221 seq_printf(p, "%10u ", irq_desc_kstat_cpu(desc, j));
222
223 seq_printf(p, " %14s", irq_desc_get_chip(desc)->name);
224 #ifndef PARISC_IRQ_CR16_COUNTS
225 seq_printf(p, " %s", action->name);
226
227 while ((action = action->next))
228 seq_printf(p, ", %s", action->name);
229 #else
230 for ( ;action; action = action->next) {
231 unsigned int k, avg, min, max;
232
233 min = max = action->cr16_hist[0];
234
235 for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
236 int hist = action->cr16_hist[k];
237
238 if (hist) {
239 avg += hist;
240 } else
241 break;
242
243 if (hist > max) max = hist;
244 if (hist < min) min = hist;
245 }
246
247 avg /= k;
248 seq_printf(p, " %s[%d/%d/%d]", action->name,
249 min,avg,max);
250 }
251 #endif
252
253 seq_putc(p, '\n');
254 skip:
255 raw_spin_unlock_irqrestore(&desc->lock, flags);
256 }
257
258 if (i == NR_IRQS)
259 arch_show_interrupts(p, 3);
260
261 return 0;
262 }
263
264
265
266 /*
267 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
268 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
269 **
270 ** To use txn_XXX() interfaces, get a Virtual IRQ first.
271 ** Then use that to get the Transaction address and data.
272 */
273
274 int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
275 {
276 if (irq_has_action(irq))
277 return -EBUSY;
278 if (irq_get_chip(irq) != &cpu_interrupt_type)
279 return -EBUSY;
280
281 /* for iosapic interrupts */
282 if (type) {
283 irq_set_chip_and_handler(irq, type, handle_percpu_irq);
284 irq_set_chip_data(irq, data);
285 __cpu_unmask_irq(irq);
286 }
287 return 0;
288 }
289
290 int txn_claim_irq(int irq)
291 {
292 return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
293 }
294
295 /*
296 * The bits_wide parameter accommodates the limitations of the HW/SW which
297 * use these bits:
298 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
299 * V-class (EPIC): 6 bits
300 * N/L/A-class (iosapic): 8 bits
301 * PCI 2.2 MSI: 16 bits
302 * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric)
303 *
304 * On the service provider side:
305 * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
306 * o PA 2.0 wide mode 6-bits (per processor)
307 * o IA64 8-bits (0-256 total)
308 *
309 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
310 * by the processor...and the N/L-class I/O subsystem supports more bits than
311 * PA2.0 has. The first case is the problem.
312 */
313 int txn_alloc_irq(unsigned int bits_wide)
314 {
315 int irq;
316
317 /* never return irq 0 cause that's the interval timer */
318 for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
319 if (cpu_claim_irq(irq, NULL, NULL) < 0)
320 continue;
321 if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
322 continue;
323 return irq;
324 }
325
326 /* unlikely, but be prepared */
327 return -1;
328 }
329
330
331 unsigned long txn_affinity_addr(unsigned int irq, int cpu)
332 {
333 #ifdef CONFIG_SMP
334 struct irq_data *d = irq_get_irq_data(irq);
335 cpumask_copy(irq_data_get_affinity_mask(d), cpumask_of(cpu));
336 #endif
337
338 return per_cpu(cpu_data, cpu).txn_addr;
339 }
340
341
342 unsigned long txn_alloc_addr(unsigned int virt_irq)
343 {
344 static int next_cpu = -1;
345
346 next_cpu++; /* assign to "next" CPU we want this bugger on */
347
348 /* validate entry */
349 while ((next_cpu < nr_cpu_ids) &&
350 (!per_cpu(cpu_data, next_cpu).txn_addr ||
351 !cpu_online(next_cpu)))
352 next_cpu++;
353
354 if (next_cpu >= nr_cpu_ids)
355 next_cpu = 0; /* nothing else, assign monarch */
356
357 return txn_affinity_addr(virt_irq, next_cpu);
358 }
359
360
361 unsigned int txn_alloc_data(unsigned int virt_irq)
362 {
363 return virt_irq - CPU_IRQ_BASE;
364 }
365
366 static inline int eirr_to_irq(unsigned long eirr)
367 {
368 int bit = fls_long(eirr);
369 return (BITS_PER_LONG - bit) + TIMER_IRQ;
370 }
371
372 #ifdef CONFIG_IRQSTACKS
373 /*
374 * IRQ STACK - used for irq handler
375 */
376 #define IRQ_STACK_SIZE (4096 << 3) /* 32k irq stack size */
377
378 union irq_stack_union {
379 unsigned long stack[IRQ_STACK_SIZE/sizeof(unsigned long)];
380 volatile unsigned int slock[4];
381 volatile unsigned int lock[1];
382 };
383
384 DEFINE_PER_CPU(union irq_stack_union, irq_stack_union) = {
385 .slock = { 1,1,1,1 },
386 };
387 #endif
388
389
390 int sysctl_panic_on_stackoverflow = 1;
391
392 static inline void stack_overflow_check(struct pt_regs *regs)
393 {
394 #ifdef CONFIG_DEBUG_STACKOVERFLOW
395 #define STACK_MARGIN (256*6)
396
397 /* Our stack starts directly behind the thread_info struct. */
398 unsigned long stack_start = (unsigned long) current_thread_info();
399 unsigned long sp = regs->gr[30];
400 unsigned long stack_usage;
401 unsigned int *last_usage;
402 int cpu = smp_processor_id();
403
404 /* if sr7 != 0, we interrupted a userspace process which we do not want
405 * to check for stack overflow. We will only check the kernel stack. */
406 if (regs->sr[7])
407 return;
408
409 /* exit if already in panic */
410 if (sysctl_panic_on_stackoverflow < 0)
411 return;
412
413 /* calculate kernel stack usage */
414 stack_usage = sp - stack_start;
415 #ifdef CONFIG_IRQSTACKS
416 if (likely(stack_usage <= THREAD_SIZE))
417 goto check_kernel_stack; /* found kernel stack */
418
419 /* check irq stack usage */
420 stack_start = (unsigned long) &per_cpu(irq_stack_union, cpu).stack;
421 stack_usage = sp - stack_start;
422
423 last_usage = &per_cpu(irq_stat.irq_stack_usage, cpu);
424 if (unlikely(stack_usage > *last_usage))
425 *last_usage = stack_usage;
426
427 if (likely(stack_usage < (IRQ_STACK_SIZE - STACK_MARGIN)))
428 return;
429
430 pr_emerg("stackcheck: %s will most likely overflow irq stack "
431 "(sp:%lx, stk bottom-top:%lx-%lx)\n",
432 current->comm, sp, stack_start, stack_start + IRQ_STACK_SIZE);
433 goto panic_check;
434
435 check_kernel_stack:
436 #endif
437
438 /* check kernel stack usage */
439 last_usage = &per_cpu(irq_stat.kernel_stack_usage, cpu);
440
441 if (unlikely(stack_usage > *last_usage))
442 *last_usage = stack_usage;
443
444 if (likely(stack_usage < (THREAD_SIZE - STACK_MARGIN)))
445 return;
446
447 pr_emerg("stackcheck: %s will most likely overflow kernel stack "
448 "(sp:%lx, stk bottom-top:%lx-%lx)\n",
449 current->comm, sp, stack_start, stack_start + THREAD_SIZE);
450
451 #ifdef CONFIG_IRQSTACKS
452 panic_check:
453 #endif
454 if (sysctl_panic_on_stackoverflow) {
455 sysctl_panic_on_stackoverflow = -1; /* disable further checks */
456 panic("low stack detected by irq handler - check messages\n");
457 }
458 #endif
459 }
460
461 #ifdef CONFIG_IRQSTACKS
462 /* in entry.S: */
463 void call_on_stack(unsigned long p1, void *func, unsigned long new_stack);
464
465 static void execute_on_irq_stack(void *func, unsigned long param1)
466 {
467 union irq_stack_union *union_ptr;
468 unsigned long irq_stack;
469 volatile unsigned int *irq_stack_in_use;
470
471 union_ptr = &per_cpu(irq_stack_union, smp_processor_id());
472 irq_stack = (unsigned long) &union_ptr->stack;
473 irq_stack = ALIGN(irq_stack + sizeof(irq_stack_union.slock),
474 64); /* align for stack frame usage */
475
476 /* We may be called recursive. If we are already using the irq stack,
477 * just continue to use it. Use spinlocks to serialize
478 * the irq stack usage.
479 */
480 irq_stack_in_use = (volatile unsigned int *)__ldcw_align(union_ptr);
481 if (!__ldcw(irq_stack_in_use)) {
482 void (*direct_call)(unsigned long p1) = func;
483
484 /* We are using the IRQ stack already.
485 * Do direct call on current stack. */
486 direct_call(param1);
487 return;
488 }
489
490 /* This is where we switch to the IRQ stack. */
491 call_on_stack(param1, func, irq_stack);
492
493 /* free up irq stack usage. */
494 *irq_stack_in_use = 1;
495 }
496
497 void do_softirq_own_stack(void)
498 {
499 execute_on_irq_stack(__do_softirq, 0);
500 }
501 #endif /* CONFIG_IRQSTACKS */
502
503 /* ONLY called from entry.S:intr_extint() */
504 void do_cpu_irq_mask(struct pt_regs *regs)
505 {
506 struct pt_regs *old_regs;
507 unsigned long eirr_val;
508 int irq, cpu = smp_processor_id();
509 struct irq_data *irq_data;
510 #ifdef CONFIG_SMP
511 cpumask_t dest;
512 #endif
513
514 old_regs = set_irq_regs(regs);
515 local_irq_disable();
516 irq_enter();
517
518 eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu);
519 if (!eirr_val)
520 goto set_out;
521 irq = eirr_to_irq(eirr_val);
522
523 irq_data = irq_get_irq_data(irq);
524
525 /* Filter out spurious interrupts, mostly from serial port at bootup */
526 if (unlikely(!irq_desc_has_action(irq_data_to_desc(irq_data))))
527 goto set_out;
528
529 #ifdef CONFIG_SMP
530 cpumask_copy(&dest, irq_data_get_affinity_mask(irq_data));
531 if (irqd_is_per_cpu(irq_data) &&
532 !cpumask_test_cpu(smp_processor_id(), &dest)) {
533 int cpu = cpumask_first(&dest);
534
535 printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
536 irq, smp_processor_id(), cpu);
537 gsc_writel(irq + CPU_IRQ_BASE,
538 per_cpu(cpu_data, cpu).hpa);
539 goto set_out;
540 }
541 #endif
542 stack_overflow_check(regs);
543
544 #ifdef CONFIG_IRQSTACKS
545 execute_on_irq_stack(&generic_handle_irq, irq);
546 #else
547 generic_handle_irq(irq);
548 #endif /* CONFIG_IRQSTACKS */
549
550 out:
551 irq_exit();
552 set_irq_regs(old_regs);
553 return;
554
555 set_out:
556 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
557 goto out;
558 }
559
560 static void claim_cpu_irqs(void)
561 {
562 unsigned long flags = IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL;
563 int i;
564
565 for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
566 irq_set_chip_and_handler(i, &cpu_interrupt_type,
567 handle_percpu_irq);
568 }
569
570 irq_set_handler(TIMER_IRQ, handle_percpu_irq);
571 if (request_irq(TIMER_IRQ, timer_interrupt, flags, "timer", NULL))
572 pr_err("Failed to register timer interrupt\n");
573 #ifdef CONFIG_SMP
574 irq_set_handler(IPI_IRQ, handle_percpu_irq);
575 if (request_irq(IPI_IRQ, ipi_interrupt, IRQF_PERCPU, "IPI", NULL))
576 pr_err("Failed to register IPI interrupt\n");
577 #endif
578 }
579
580 void __init init_IRQ(void)
581 {
582 local_irq_disable(); /* PARANOID - should already be disabled */
583 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
584 #ifdef CONFIG_SMP
585 if (!cpu_eiem) {
586 claim_cpu_irqs();
587 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
588 }
589 #else
590 claim_cpu_irqs();
591 cpu_eiem = EIEM_MASK(TIMER_IRQ);
592 #endif
593 set_eiem(cpu_eiem); /* EIEM : enable all external intr */
594 }