arch/parisc/kernel/time.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  linux/arch/parisc/kernel/time.c
   4  *
   5  *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
   6  *  Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King
   7  *  Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org)
   8  *
   9  * 1994-07-02  Alan Modra
  10  *             fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
  11  * 1998-12-20  Updated NTP code according to technical memorandum Jan '96
  12  *             "A Kernel Model for Precision Timekeeping" by Dave Mills
  13  */
  14 #include <linux/errno.h>
  15 #include <linux/module.h>
  16 #include <linux/rtc.h>
  17 #include <linux/sched.h>
  18 #include <linux/sched/clock.h>
  19 #include <linux/sched_clock.h>
  20 #include <linux/kernel.h>
  21 #include <linux/param.h>
  22 #include <linux/string.h>
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/time.h>
  26 #include <linux/init.h>
  27 #include <linux/smp.h>
  28 #include <linux/profile.h>
  29 #include <linux/clocksource.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/ftrace.h>
  32
  33 #include <linux/uaccess.h>
  34 #include <asm/io.h>
  35 #include <asm/irq.h>
  36 #include <asm/page.h>
  37 #include <asm/param.h>
  38 #include <asm/pdc.h>
  39 #include <asm/led.h>
  40
  41 #include <linux/timex.h>
  42
  43 static unsigned long clocktick __read_mostly;   /* timer cycles per tick */
  44
  45 /*
  46  * We keep time on PA-RISC Linux by using the Interval Timer which is
  47  * a pair of registers; one is read-only and one is write-only; both
  48  * accessed through CR16.  The read-only register is 32 or 64 bits wide,
  49  * and increments by 1 every CPU clock tick.  The architecture only
  50  * guarantees us a rate between 0.5 and 2, but all implementations use a
  51  * rate of 1.  The write-only register is 32-bits wide.  When the lowest
  52  * 32 bits of the read-only register compare equal to the write-only
  53  * register, it raises a maskable external interrupt.  Each processor has
  54  * an Interval Timer of its own and they are not synchronised.
  55  *
  56  * We want to generate an interrupt every 1/HZ seconds.  So we program
  57  * CR16 to interrupt every @clocktick cycles.  The it_value in cpu_data
  58  * is programmed with the intended time of the next tick.  We can be
  59  * held off for an arbitrarily long period of time by interrupts being
  60  * disabled, so we may miss one or more ticks.
  61  */
  62 irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id)
  63 {
  64         unsigned long now;
  65         unsigned long next_tick;
  66         unsigned long ticks_elapsed = 0;
  67         unsigned int cpu = smp_processor_id();
  68         struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu);
  69
  70         /* gcc can optimize for "read-only" case with a local clocktick */
  71         unsigned long cpt = clocktick;
  72
  73         profile_tick(CPU_PROFILING);
  74
  75         /* Initialize next_tick to the old expected tick time. */
  76         next_tick = cpuinfo->it_value;
  77
  78         /* Calculate how many ticks have elapsed. */
  79         do {
  80                 ++ticks_elapsed;
  81                 next_tick += cpt;
  82                 now = mfctl(16);
  83         } while (next_tick - now > cpt);
  84
  85         /* Store (in CR16 cycles) up to when we are accounting right now. */
  86         cpuinfo->it_value = next_tick;
  87
  88         /* Go do system house keeping. */
  89         if (cpu == 0)
  90                 xtime_update(ticks_elapsed);
  91
  92         update_process_times(user_mode(get_irq_regs()));
  93
  94         /* Skip clockticks on purpose if we know we would miss those.
  95          * The new CR16 must be "later" than current CR16 otherwise
  96          * itimer would not fire until CR16 wrapped - e.g 4 seconds
  97          * later on a 1Ghz processor. We'll account for the missed
  98          * ticks on the next timer interrupt.
  99          * We want IT to fire modulo clocktick even if we miss/skip some.
 100          * But those interrupts don't in fact get delivered that regularly.
 101          *
 102          * "next_tick - now" will always give the difference regardless
 103          * if one or the other wrapped. If "now" is "bigger" we'll end up
 104          * with a very large unsigned number.
 105          */
 106         while (next_tick - mfctl(16) > cpt)
 107                 next_tick += cpt;
 108
 109         /* Program the IT when to deliver the next interrupt.
 110          * Only bottom 32-bits of next_tick are writable in CR16!
 111          * Timer interrupt will be delivered at least a few hundred cycles
 112          * after the IT fires, so if we are too close (<= 500 cycles) to the
 113          * next cycle, simply skip it.
 114          */
 115         if (next_tick - mfctl(16) <= 500)
 116                 next_tick += cpt;
 117         mtctl(next_tick, 16);
 118
 119         return IRQ_HANDLED;
 120 }
 121
 122
 123 unsigned long profile_pc(struct pt_regs *regs)
 124 {
 125         unsigned long pc = instruction_pointer(regs);
 126
 127         if (regs->gr[0] & PSW_N)
 128                 pc -= 4;
 129
 130 #ifdef CONFIG_SMP
 131         if (in_lock_functions(pc))
 132                 pc = regs->gr[2];
 133 #endif
 134
 135         return pc;
 136 }
 137 EXPORT_SYMBOL(profile_pc);
 138
 139
 140 /* clock source code */
 141
 142 static u64 notrace read_cr16(struct clocksource *cs)
 143 {
 144         return get_cycles();
 145 }
 146
 147 static struct clocksource clocksource_cr16 = {
 148         .name                   = "cr16",
 149         .rating                 = 300,
 150         .read                   = read_cr16,
 151         .mask                   = CLOCKSOURCE_MASK(BITS_PER_LONG),
 152         .flags                  = CLOCK_SOURCE_IS_CONTINUOUS,
 153 };
 154
 155 void __init start_cpu_itimer(void)
 156 {
 157         unsigned int cpu = smp_processor_id();
 158         unsigned long next_tick = mfctl(16) + clocktick;
 159
 160         mtctl(next_tick, 16);           /* kick off Interval Timer (CR16) */
 161
 162         per_cpu(cpu_data, cpu).it_value = next_tick;
 163 }
 164
 165 #if IS_ENABLED(CONFIG_RTC_DRV_GENERIC)
 166 static int rtc_generic_get_time(struct device *dev, struct rtc_time *tm)
 167 {
 168         struct pdc_tod tod_data;
 169
 170         memset(tm, 0, sizeof(*tm));
 171         if (pdc_tod_read(&tod_data) < 0)
 172                 return -EOPNOTSUPP;
 173
 174         /* we treat tod_sec as unsigned, so this can work until year 2106 */
 175         rtc_time64_to_tm(tod_data.tod_sec, tm);
 176         return rtc_valid_tm(tm);
 177 }
 178
 179 static int rtc_generic_set_time(struct device *dev, struct rtc_time *tm)
 180 {
 181         time64_t secs = rtc_tm_to_time64(tm);
 182
 183         if (pdc_tod_set(secs, 0) < 0)
 184                 return -EOPNOTSUPP;
 185
 186         return 0;
 187 }
 188
 189 static const struct rtc_class_ops rtc_generic_ops = {
 190         .read_time = rtc_generic_get_time,
 191         .set_time = rtc_generic_set_time,
 192 };
 193
 194 static int __init rtc_init(void)
 195 {
 196         struct platform_device *pdev;
 197
 198         pdev = platform_device_register_data(NULL, "rtc-generic", -1,
 199                                              &rtc_generic_ops,
 200                                              sizeof(rtc_generic_ops));
 201
 202         return PTR_ERR_OR_ZERO(pdev);
 203 }
 204 device_initcall(rtc_init);
 205 #endif
 206
 207 void read_persistent_clock(struct timespec *ts)
 208 {
 209         static struct pdc_tod tod_data;
 210         if (pdc_tod_read(&tod_data) == 0) {
 211                 ts->tv_sec = tod_data.tod_sec;
 212                 ts->tv_nsec = tod_data.tod_usec * 1000;
 213         } else {
 214                 printk(KERN_ERR "Error reading tod clock\n");
 215                 ts->tv_sec = 0;
 216                 ts->tv_nsec = 0;
 217         }
 218 }
 219
 220
 221 static u64 notrace read_cr16_sched_clock(void)
 222 {
 223         return get_cycles();
 224 }
 225
 226
 227 /*
 228  * timer interrupt and sched_clock() initialization
 229  */
 230
 231 void __init time_init(void)
 232 {
 233         unsigned long cr16_hz;
 234
 235         clocktick = (100 * PAGE0->mem_10msec) / HZ;
 236         start_cpu_itimer();     /* get CPU 0 started */
 237
 238         cr16_hz = 100 * PAGE0->mem_10msec;  /* Hz */
 239
 240         /* register as sched_clock source */
 241         sched_clock_register(read_cr16_sched_clock, BITS_PER_LONG, cr16_hz);
 242 }
 243
 244 static int __init init_cr16_clocksource(void)
 245 {
 246         /*
 247          * The cr16 interval timers are not syncronized across CPUs on
 248          * different sockets, so mark them unstable and lower rating on
 249          * multi-socket SMP systems.
 250          */
 251         if (num_online_cpus() > 1) {
 252                 int cpu;
 253                 unsigned long cpu0_loc;
 254                 cpu0_loc = per_cpu(cpu_data, 0).cpu_loc;
 255
 256                 for_each_online_cpu(cpu) {
 257                         if (cpu == 0)
 258                                 continue;
 259                         if ((cpu0_loc != 0) &&
 260                             (cpu0_loc == per_cpu(cpu_data, cpu).cpu_loc))
 261                                 continue;
 262
 263                         clocksource_cr16.name = "cr16_unstable";
 264                         clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
 265                         clocksource_cr16.rating = 0;
 266                         break;
 267                 }
 268         }
 269
 270         /* XXX: We may want to mark sched_clock stable here if cr16 clocks are
 271          *      in sync:
 272          *      (clocksource_cr16.flags == CLOCK_SOURCE_IS_CONTINUOUS) */
 273
 274         /* register at clocksource framework */
 275         clocksource_register_hz(&clocksource_cr16,
 276                 100 * PAGE0->mem_10msec);
 277
 278         return 0;
 279 }
 280
 281 device_initcall(init_cr16_clocksource);