arch/parisc/kernel/time.c

   1 /*
   2  *  linux/arch/parisc/kernel/time.c
   3  *
   4  *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
   5  *  Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King
   6  *  Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org)
   7  *
   8  * 1994-07-02  Alan Modra
   9  *             fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
  10  * 1998-12-20  Updated NTP code according to technical memorandum Jan '96
  11  *             "A Kernel Model for Precision Timekeeping" by Dave Mills
  12  */
  13 #include <linux/errno.h>
  14 #include <linux/module.h>
  15 #include <linux/rtc.h>
  16 #include <linux/sched.h>
  17 #include <linux/sched/clock.h>
  18 #include <linux/sched_clock.h>
  19 #include <linux/kernel.h>
  20 #include <linux/param.h>
  21 #include <linux/string.h>
  22 #include <linux/mm.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/time.h>
  25 #include <linux/init.h>
  26 #include <linux/smp.h>
  27 #include <linux/profile.h>
  28 #include <linux/clocksource.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/ftrace.h>
  31
  32 #include <linux/uaccess.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35 #include <asm/page.h>
  36 #include <asm/param.h>
  37 #include <asm/pdc.h>
  38 #include <asm/led.h>
  39
  40 #include <linux/timex.h>
  41
  42 static unsigned long clocktick __read_mostly;   /* timer cycles per tick */
  43
  44 /*
  45  * We keep time on PA-RISC Linux by using the Interval Timer which is
  46  * a pair of registers; one is read-only and one is write-only; both
  47  * accessed through CR16.  The read-only register is 32 or 64 bits wide,
  48  * and increments by 1 every CPU clock tick.  The architecture only
  49  * guarantees us a rate between 0.5 and 2, but all implementations use a
  50  * rate of 1.  The write-only register is 32-bits wide.  When the lowest
  51  * 32 bits of the read-only register compare equal to the write-only
  52  * register, it raises a maskable external interrupt.  Each processor has
  53  * an Interval Timer of its own and they are not synchronised.
  54  *
  55  * We want to generate an interrupt every 1/HZ seconds.  So we program
  56  * CR16 to interrupt every @clocktick cycles.  The it_value in cpu_data
  57  * is programmed with the intended time of the next tick.  We can be
  58  * held off for an arbitrarily long period of time by interrupts being
  59  * disabled, so we may miss one or more ticks.
  60  */
  61 irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id)
  62 {
  63         unsigned long now;
  64         unsigned long next_tick;
  65         unsigned long ticks_elapsed = 0;
  66         unsigned int cpu = smp_processor_id();
  67         struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu);
  68
  69         /* gcc can optimize for "read-only" case with a local clocktick */
  70         unsigned long cpt = clocktick;
  71
  72         profile_tick(CPU_PROFILING);
  73
  74         /* Initialize next_tick to the old expected tick time. */
  75         next_tick = cpuinfo->it_value;
  76
  77         /* Calculate how many ticks have elapsed. */
  78         do {
  79                 ++ticks_elapsed;
  80                 next_tick += cpt;
  81                 now = mfctl(16);
  82         } while (next_tick - now > cpt);
  83
  84         /* Store (in CR16 cycles) up to when we are accounting right now. */
  85         cpuinfo->it_value = next_tick;
  86
  87         /* Go do system house keeping. */
  88         if (cpu == 0)
  89                 xtime_update(ticks_elapsed);
  90
  91         update_process_times(user_mode(get_irq_regs()));
  92
  93         /* Skip clockticks on purpose if we know we would miss those.
  94          * The new CR16 must be "later" than current CR16 otherwise
  95          * itimer would not fire until CR16 wrapped - e.g 4 seconds
  96          * later on a 1Ghz processor. We'll account for the missed
  97          * ticks on the next timer interrupt.
  98          * We want IT to fire modulo clocktick even if we miss/skip some.
  99          * But those interrupts don't in fact get delivered that regularly.
 100          *
 101          * "next_tick - now" will always give the difference regardless
 102          * if one or the other wrapped. If "now" is "bigger" we'll end up
 103          * with a very large unsigned number.
 104          */
 105         while (next_tick - mfctl(16) > cpt)
 106                 next_tick += cpt;
 107
 108         /* Program the IT when to deliver the next interrupt.
 109          * Only bottom 32-bits of next_tick are writable in CR16!
 110          * Timer interrupt will be delivered at least a few hundred cycles
 111          * after the IT fires, so if we are too close (<= 500 cycles) to the
 112          * next cycle, simply skip it.
 113          */
 114         if (next_tick - mfctl(16) <= 500)
 115                 next_tick += cpt;
 116         mtctl(next_tick, 16);
 117
 118         return IRQ_HANDLED;
 119 }
 120
 121
 122 unsigned long profile_pc(struct pt_regs *regs)
 123 {
 124         unsigned long pc = instruction_pointer(regs);
 125
 126         if (regs->gr[0] & PSW_N)
 127                 pc -= 4;
 128
 129 #ifdef CONFIG_SMP
 130         if (in_lock_functions(pc))
 131                 pc = regs->gr[2];
 132 #endif
 133
 134         return pc;
 135 }
 136 EXPORT_SYMBOL(profile_pc);
 137
 138
 139 /* clock source code */
 140
 141 static u64 notrace read_cr16(struct clocksource *cs)
 142 {
 143         return get_cycles();
 144 }
 145
 146 static struct clocksource clocksource_cr16 = {
 147         .name                   = "cr16",
 148         .rating                 = 300,
 149         .read                   = read_cr16,
 150         .mask                   = CLOCKSOURCE_MASK(BITS_PER_LONG),
 151         .flags                  = CLOCK_SOURCE_IS_CONTINUOUS,
 152 };
 153
 154 void __init start_cpu_itimer(void)
 155 {
 156         unsigned int cpu = smp_processor_id();
 157         unsigned long next_tick = mfctl(16) + clocktick;
 158
 159         mtctl(next_tick, 16);           /* kick off Interval Timer (CR16) */
 160
 161         per_cpu(cpu_data, cpu).it_value = next_tick;
 162 }
 163
 164 #if IS_ENABLED(CONFIG_RTC_DRV_GENERIC)
 165 static int rtc_generic_get_time(struct device *dev, struct rtc_time *tm)
 166 {
 167         struct pdc_tod tod_data;
 168
 169         memset(tm, 0, sizeof(*tm));
 170         if (pdc_tod_read(&tod_data) < 0)
 171                 return -EOPNOTSUPP;
 172
 173         /* we treat tod_sec as unsigned, so this can work until year 2106 */
 174         rtc_time64_to_tm(tod_data.tod_sec, tm);
 175         return rtc_valid_tm(tm);
 176 }
 177
 178 static int rtc_generic_set_time(struct device *dev, struct rtc_time *tm)
 179 {
 180         time64_t secs = rtc_tm_to_time64(tm);
 181
 182         if (pdc_tod_set(secs, 0) < 0)
 183                 return -EOPNOTSUPP;
 184
 185         return 0;
 186 }
 187
 188 static const struct rtc_class_ops rtc_generic_ops = {
 189         .read_time = rtc_generic_get_time,
 190         .set_time = rtc_generic_set_time,
 191 };
 192
 193 static int __init rtc_init(void)
 194 {
 195         struct platform_device *pdev;
 196
 197         pdev = platform_device_register_data(NULL, "rtc-generic", -1,
 198                                              &rtc_generic_ops,
 199                                              sizeof(rtc_generic_ops));
 200
 201         return PTR_ERR_OR_ZERO(pdev);
 202 }
 203 device_initcall(rtc_init);
 204 #endif
 205
 206 void read_persistent_clock(struct timespec *ts)
 207 {
 208         static struct pdc_tod tod_data;
 209         if (pdc_tod_read(&tod_data) == 0) {
 210                 ts->tv_sec = tod_data.tod_sec;
 211                 ts->tv_nsec = tod_data.tod_usec * 1000;
 212         } else {
 213                 printk(KERN_ERR "Error reading tod clock\n");
 214                 ts->tv_sec = 0;
 215                 ts->tv_nsec = 0;
 216         }
 217 }
 218
 219
 220 static u64 notrace read_cr16_sched_clock(void)
 221 {
 222         return get_cycles();
 223 }
 224
 225
 226 /*
 227  * timer interrupt and sched_clock() initialization
 228  */
 229
 230 void __init time_init(void)
 231 {
 232         unsigned long cr16_hz;
 233
 234         clocktick = (100 * PAGE0->mem_10msec) / HZ;
 235         start_cpu_itimer();     /* get CPU 0 started */
 236
 237         cr16_hz = 100 * PAGE0->mem_10msec;  /* Hz */
 238
 239         /* register as sched_clock source */
 240         sched_clock_register(read_cr16_sched_clock, BITS_PER_LONG, cr16_hz);
 241 }
 242
 243 static int __init init_cr16_clocksource(void)
 244 {
 245         /*
 246          * The cr16 interval timers are not syncronized across CPUs, so mark
 247          * them unstable and lower rating on SMP systems.
 248          */
 249         if (num_online_cpus() > 1) {
 250                 clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
 251                 clocksource_cr16.rating = 0;
 252         }
 253
 254         /* register at clocksource framework */
 255         clocksource_register_hz(&clocksource_cr16,
 256                 100 * PAGE0->mem_10msec);
 257
 258         return 0;
 259 }
 260
 261 device_initcall(init_cr16_clocksource);