1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Unaligned memory access handler
5 * Copyright (C) 2001 Randolph Chung <tausq@debian.org>
6 * Significantly tweaked by LaMont Jones <lamont@debian.org>
9 #include <linux/jiffies.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/sched/signal.h>
13 #include <linux/sched/debug.h>
14 #include <linux/signal.h>
15 #include <linux/ratelimit.h>
16 #include <linux/uaccess.h>
17 #include <asm/hardirq.h>
18 #include <asm/traps.h>
20 /* #define DEBUG_UNALIGNED 1 */
22 #ifdef DEBUG_UNALIGNED
23 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
25 #define DPRINTF(fmt, args...)
34 #define FIXUP_BRANCH(lbl) \
35 "\tldil L%%" #lbl ", %%r1\n" \
36 "\tldo R%%" #lbl "(%%r1), %%r1\n" \
38 /* If you use FIXUP_BRANCH, then you must list this clobber */
39 #define FIXUP_BRANCH_CLOBBER "r1"
41 /* 1111 1100 0000 0000 0001 0011 1100 0000 */
42 #define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6)
43 #define OPCODE2(a,b) ((a)<<26|(b)<<1)
44 #define OPCODE3(a,b) ((a)<<26|(b)<<2)
45 #define OPCODE4(a) ((a)<<26)
46 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
47 #define OPCODE2_MASK OPCODE2(0x3f,1)
48 #define OPCODE3_MASK OPCODE3(0x3f,1)
49 #define OPCODE4_MASK OPCODE4(0x3f)
51 /* skip LDB - never unaligned (index) */
52 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
53 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
54 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
55 #define OPCODE_LDDA_I OPCODE1(0x03,0,0x4)
56 #define OPCODE_LDCD_I OPCODE1(0x03,0,0x5)
57 #define OPCODE_LDWA_I OPCODE1(0x03,0,0x6)
58 #define OPCODE_LDCW_I OPCODE1(0x03,0,0x7)
59 /* skip LDB - never unaligned (short) */
60 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
61 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
62 #define OPCODE_LDD_S OPCODE1(0x03,1,0x3)
63 #define OPCODE_LDDA_S OPCODE1(0x03,1,0x4)
64 #define OPCODE_LDCD_S OPCODE1(0x03,1,0x5)
65 #define OPCODE_LDWA_S OPCODE1(0x03,1,0x6)
66 #define OPCODE_LDCW_S OPCODE1(0x03,1,0x7)
67 /* skip STB - never unaligned */
68 #define OPCODE_STH OPCODE1(0x03,1,0x9)
69 #define OPCODE_STW OPCODE1(0x03,1,0xa)
70 #define OPCODE_STD OPCODE1(0x03,1,0xb)
71 /* skip STBY - never unaligned */
72 /* skip STDBY - never unaligned */
73 #define OPCODE_STWA OPCODE1(0x03,1,0xe)
74 #define OPCODE_STDA OPCODE1(0x03,1,0xf)
76 #define OPCODE_FLDWX OPCODE1(0x09,0,0x0)
77 #define OPCODE_FLDWXR OPCODE1(0x09,0,0x1)
78 #define OPCODE_FSTWX OPCODE1(0x09,0,0x8)
79 #define OPCODE_FSTWXR OPCODE1(0x09,0,0x9)
80 #define OPCODE_FLDWS OPCODE1(0x09,1,0x0)
81 #define OPCODE_FLDWSR OPCODE1(0x09,1,0x1)
82 #define OPCODE_FSTWS OPCODE1(0x09,1,0x8)
83 #define OPCODE_FSTWSR OPCODE1(0x09,1,0x9)
84 #define OPCODE_FLDDX OPCODE1(0x0b,0,0x0)
85 #define OPCODE_FSTDX OPCODE1(0x0b,0,0x8)
86 #define OPCODE_FLDDS OPCODE1(0x0b,1,0x0)
87 #define OPCODE_FSTDS OPCODE1(0x0b,1,0x8)
89 #define OPCODE_LDD_L OPCODE2(0x14,0)
90 #define OPCODE_FLDD_L OPCODE2(0x14,1)
91 #define OPCODE_STD_L OPCODE2(0x1c,0)
92 #define OPCODE_FSTD_L OPCODE2(0x1c,1)
94 #define OPCODE_LDW_M OPCODE3(0x17,1)
95 #define OPCODE_FLDW_L OPCODE3(0x17,0)
96 #define OPCODE_FSTW_L OPCODE3(0x1f,0)
97 #define OPCODE_STW_M OPCODE3(0x1f,1)
99 #define OPCODE_LDH_L OPCODE4(0x11)
100 #define OPCODE_LDW_L OPCODE4(0x12)
101 #define OPCODE_LDWM OPCODE4(0x13)
102 #define OPCODE_STH_L OPCODE4(0x19)
103 #define OPCODE_STW_L OPCODE4(0x1A)
104 #define OPCODE_STWM OPCODE4(0x1B)
106 #define MAJOR_OP(i) (((i)>>26)&0x3f)
107 #define R1(i) (((i)>>21)&0x1f)
108 #define R2(i) (((i)>>16)&0x1f)
109 #define R3(i) ((i)&0x1f)
110 #define FR3(i) ((((i)<<1)&0x1f)|(((i)>>6)&1))
111 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
112 #define IM5_2(i) IM((i)>>16,5)
113 #define IM5_3(i) IM((i),5)
114 #define IM14(i) IM((i),14)
116 #define ERR_NOTHANDLED -1
117 #define ERR_PAGEFAULT -2
119 int unaligned_enabled __read_mostly
= 1;
121 static int emulate_ldh(struct pt_regs
*regs
, int toreg
)
123 unsigned long saddr
= regs
->ior
;
124 unsigned long val
= 0;
127 DPRINTF("load " RFMT
":" RFMT
" to r%d for 2 bytes\n",
128 regs
->isr
, regs
->ior
, toreg
);
130 __asm__
__volatile__ (
132 "1: ldbs 0(%%sr1,%3), %%r20\n"
133 "2: ldbs 1(%%sr1,%3), %0\n"
134 " depw %%r20, 23, 24, %0\n"
137 " .section .fixup,\"ax\"\n"
141 ASM_EXCEPTIONTABLE_ENTRY(1b
, 4b
)
142 ASM_EXCEPTIONTABLE_ENTRY(2b
, 4b
)
143 : "=r" (val
), "=r" (ret
)
144 : "0" (val
), "r" (saddr
), "r" (regs
->isr
)
145 : "r20", FIXUP_BRANCH_CLOBBER
);
147 DPRINTF("val = 0x" RFMT
"\n", val
);
150 regs
->gr
[toreg
] = val
;
155 static int emulate_ldw(struct pt_regs
*regs
, int toreg
, int flop
)
157 unsigned long saddr
= regs
->ior
;
158 unsigned long val
= 0;
161 DPRINTF("load " RFMT
":" RFMT
" to r%d for 4 bytes\n",
162 regs
->isr
, regs
->ior
, toreg
);
164 __asm__
__volatile__ (
165 " zdep %3,28,2,%%r19\n" /* r19=(ofs&3)*8 */
167 " depw %%r0,31,2,%3\n"
168 "1: ldw 0(%%sr1,%3),%0\n"
169 "2: ldw 4(%%sr1,%3),%%r20\n"
170 " subi 32,%%r19,%%r19\n"
172 " vshd %0,%%r20,%0\n"
175 " .section .fixup,\"ax\"\n"
179 ASM_EXCEPTIONTABLE_ENTRY(1b
, 4b
)
180 ASM_EXCEPTIONTABLE_ENTRY(2b
, 4b
)
181 : "=r" (val
), "=r" (ret
)
182 : "0" (val
), "r" (saddr
), "r" (regs
->isr
)
183 : "r19", "r20", FIXUP_BRANCH_CLOBBER
);
185 DPRINTF("val = 0x" RFMT
"\n", val
);
188 ((__u32
*)(regs
->fr
))[toreg
] = val
;
190 regs
->gr
[toreg
] = val
;
194 static int emulate_ldd(struct pt_regs
*regs
, int toreg
, int flop
)
196 unsigned long saddr
= regs
->ior
;
200 DPRINTF("load " RFMT
":" RFMT
" to r%d for 8 bytes\n",
201 regs
->isr
, regs
->ior
, toreg
);
208 __asm__
__volatile__ (
209 " depd,z %3,60,3,%%r19\n" /* r19=(ofs&7)*8 */
211 " depd %%r0,63,3,%3\n"
212 "1: ldd 0(%%sr1,%3),%0\n"
213 "2: ldd 8(%%sr1,%3),%%r20\n"
214 " subi 64,%%r19,%%r19\n"
216 " shrpd %0,%%r20,%%sar,%0\n"
219 " .section .fixup,\"ax\"\n"
223 ASM_EXCEPTIONTABLE_ENTRY(1b
,4b
)
224 ASM_EXCEPTIONTABLE_ENTRY(2b
,4b
)
225 : "=r" (val
), "=r" (ret
)
226 : "0" (val
), "r" (saddr
), "r" (regs
->isr
)
227 : "r19", "r20", FIXUP_BRANCH_CLOBBER
);
230 unsigned long valh
=0,vall
=0;
231 __asm__
__volatile__ (
232 " zdep %5,29,2,%%r19\n" /* r19=(ofs&3)*8 */
234 " dep %%r0,31,2,%5\n"
235 "1: ldw 0(%%sr1,%5),%0\n"
236 "2: ldw 4(%%sr1,%5),%1\n"
237 "3: ldw 8(%%sr1,%5),%%r20\n"
238 " subi 32,%%r19,%%r19\n"
241 " vshd %1,%%r20,%1\n"
244 " .section .fixup,\"ax\"\n"
248 ASM_EXCEPTIONTABLE_ENTRY(1b
,5b
)
249 ASM_EXCEPTIONTABLE_ENTRY(2b
,5b
)
250 ASM_EXCEPTIONTABLE_ENTRY(3b
,5b
)
251 : "=r" (valh
), "=r" (vall
), "=r" (ret
)
252 : "0" (valh
), "1" (vall
), "r" (saddr
), "r" (regs
->isr
)
253 : "r19", "r20", FIXUP_BRANCH_CLOBBER
);
254 val
=((__u64
)valh
<<32)|(__u64
)vall
;
258 DPRINTF("val = 0x%llx\n", val
);
261 regs
->fr
[toreg
] = val
;
263 regs
->gr
[toreg
] = val
;
268 static int emulate_sth(struct pt_regs
*regs
, int frreg
)
270 unsigned long val
= regs
->gr
[frreg
];
276 DPRINTF("store r%d (0x" RFMT
") to " RFMT
":" RFMT
" for 2 bytes\n", frreg
,
277 val
, regs
->isr
, regs
->ior
);
279 __asm__
__volatile__ (
281 " extrw,u %1, 23, 8, %%r19\n"
282 "1: stb %1, 1(%%sr1, %2)\n"
283 "2: stb %%r19, 0(%%sr1, %2)\n"
286 " .section .fixup,\"ax\"\n"
290 ASM_EXCEPTIONTABLE_ENTRY(1b
,4b
)
291 ASM_EXCEPTIONTABLE_ENTRY(2b
,4b
)
293 : "r" (val
), "r" (regs
->ior
), "r" (regs
->isr
)
294 : "r19", FIXUP_BRANCH_CLOBBER
);
299 static int emulate_stw(struct pt_regs
*regs
, int frreg
, int flop
)
305 val
= ((__u32
*)(regs
->fr
))[frreg
];
307 val
= regs
->gr
[frreg
];
311 DPRINTF("store r%d (0x" RFMT
") to " RFMT
":" RFMT
" for 4 bytes\n", frreg
,
312 val
, regs
->isr
, regs
->ior
);
315 __asm__
__volatile__ (
317 " zdep %2, 28, 2, %%r19\n"
318 " dep %%r0, 31, 2, %2\n"
320 " depwi,z -2, %%sar, 32, %%r19\n"
321 "1: ldw 0(%%sr1,%2),%%r20\n"
322 "2: ldw 4(%%sr1,%2),%%r21\n"
323 " vshd %%r0, %1, %%r22\n"
324 " vshd %1, %%r0, %%r1\n"
325 " and %%r20, %%r19, %%r20\n"
326 " andcm %%r21, %%r19, %%r21\n"
327 " or %%r22, %%r20, %%r20\n"
328 " or %%r1, %%r21, %%r21\n"
329 " stw %%r20,0(%%sr1,%2)\n"
330 " stw %%r21,4(%%sr1,%2)\n"
333 " .section .fixup,\"ax\"\n"
337 ASM_EXCEPTIONTABLE_ENTRY(1b
,4b
)
338 ASM_EXCEPTIONTABLE_ENTRY(2b
,4b
)
340 : "r" (val
), "r" (regs
->ior
), "r" (regs
->isr
)
341 : "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER
);
345 static int emulate_std(struct pt_regs
*regs
, int frreg
, int flop
)
351 val
= regs
->fr
[frreg
];
353 val
= regs
->gr
[frreg
];
357 DPRINTF("store r%d (0x%016llx) to " RFMT
":" RFMT
" for 8 bytes\n", frreg
,
358 val
, regs
->isr
, regs
->ior
);
365 __asm__
__volatile__ (
367 " depd,z %2, 60, 3, %%r19\n"
368 " depd %%r0, 63, 3, %2\n"
370 " depdi,z -2, %%sar, 64, %%r19\n"
371 "1: ldd 0(%%sr1,%2),%%r20\n"
372 "2: ldd 8(%%sr1,%2),%%r21\n"
373 " shrpd %%r0, %1, %%sar, %%r22\n"
374 " shrpd %1, %%r0, %%sar, %%r1\n"
375 " and %%r20, %%r19, %%r20\n"
376 " andcm %%r21, %%r19, %%r21\n"
377 " or %%r22, %%r20, %%r20\n"
378 " or %%r1, %%r21, %%r21\n"
379 "3: std %%r20,0(%%sr1,%2)\n"
380 "4: std %%r21,8(%%sr1,%2)\n"
383 " .section .fixup,\"ax\"\n"
387 ASM_EXCEPTIONTABLE_ENTRY(1b
,6b
)
388 ASM_EXCEPTIONTABLE_ENTRY(2b
,6b
)
389 ASM_EXCEPTIONTABLE_ENTRY(3b
,6b
)
390 ASM_EXCEPTIONTABLE_ENTRY(4b
,6b
)
392 : "r" (val
), "r" (regs
->ior
), "r" (regs
->isr
)
393 : "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER
);
396 unsigned long valh
=(val
>>32),vall
=(val
&0xffffffffl
);
397 __asm__
__volatile__ (
399 " zdep %2, 29, 2, %%r19\n"
400 " dep %%r0, 31, 2, %2\n"
402 " zvdepi -2, 32, %%r19\n"
403 "1: ldw 0(%%sr1,%3),%%r20\n"
404 "2: ldw 8(%%sr1,%3),%%r21\n"
405 " vshd %1, %2, %%r1\n"
406 " vshd %%r0, %1, %1\n"
407 " vshd %2, %%r0, %2\n"
408 " and %%r20, %%r19, %%r20\n"
409 " andcm %%r21, %%r19, %%r21\n"
410 " or %1, %%r20, %1\n"
411 " or %2, %%r21, %2\n"
412 "3: stw %1,0(%%sr1,%1)\n"
413 "4: stw %%r1,4(%%sr1,%3)\n"
414 "5: stw %2,8(%%sr1,%3)\n"
417 " .section .fixup,\"ax\"\n"
421 ASM_EXCEPTIONTABLE_ENTRY(1b
,7b
)
422 ASM_EXCEPTIONTABLE_ENTRY(2b
,7b
)
423 ASM_EXCEPTIONTABLE_ENTRY(3b
,7b
)
424 ASM_EXCEPTIONTABLE_ENTRY(4b
,7b
)
425 ASM_EXCEPTIONTABLE_ENTRY(5b
,7b
)
427 : "r" (valh
), "r" (vall
), "r" (regs
->ior
), "r" (regs
->isr
)
428 : "r19", "r20", "r21", "r1", FIXUP_BRANCH_CLOBBER
);
435 void handle_unaligned(struct pt_regs
*regs
)
437 static DEFINE_RATELIMIT_STATE(ratelimit
, 5 * HZ
, 5);
438 unsigned long newbase
= R1(regs
->iir
)?regs
->gr
[R1(regs
->iir
)]:0;
440 int ret
= ERR_NOTHANDLED
;
441 register int flop
=0; /* true if this is a flop */
443 __inc_irq_stat(irq_unaligned_count
);
445 /* log a message with pacing */
446 if (user_mode(regs
)) {
447 if (current
->thread
.flags
& PARISC_UAC_SIGBUS
) {
451 if (!(current
->thread
.flags
& PARISC_UAC_NOPRINT
) &&
452 __ratelimit(&ratelimit
)) {
454 sprintf(buf
, "%s(%d): unaligned access to 0x" RFMT
" at ip=0x" RFMT
"\n",
455 current
->comm
, task_pid_nr(current
), regs
->ior
, regs
->iaoq
[0]);
456 printk(KERN_WARNING
"%s", buf
);
457 #ifdef DEBUG_UNALIGNED
462 if (!unaligned_enabled
)
466 /* handle modification - OK, it's ugly, see the instruction manual */
467 switch (MAJOR_OP(regs
->iir
))
475 if (regs
->iir
&0x1000) /* short loads */
477 newbase
+= IM5_3(regs
->iir
);
479 newbase
+= IM5_2(regs
->iir
);
480 else if (regs
->iir
&0x2000) /* scaled indexed */
483 switch (regs
->iir
& OPCODE1_MASK
)
493 newbase
+= (R2(regs
->iir
)?regs
->gr
[R2(regs
->iir
)]:0)<<shift
;
494 } else /* simple indexed */
495 newbase
+= (R2(regs
->iir
)?regs
->gr
[R2(regs
->iir
)]:0);
501 newbase
+= IM14(regs
->iir
);
508 newbase
+= IM14(regs
->iir
&~0xe);
514 newbase
+= IM14(regs
->iir
&6);
521 newbase
+= IM14(regs
->iir
&~4);
526 /* TODO: make this cleaner... */
527 switch (regs
->iir
& OPCODE1_MASK
)
531 ret
= emulate_ldh(regs
, R3(regs
->iir
));
538 ret
= emulate_ldw(regs
, R3(regs
->iir
),0);
542 ret
= emulate_sth(regs
, R2(regs
->iir
));
547 ret
= emulate_stw(regs
, R2(regs
->iir
),0);
555 ret
= emulate_ldd(regs
, R3(regs
->iir
),0);
560 ret
= emulate_std(regs
, R2(regs
->iir
),0);
569 ret
= emulate_ldw(regs
,FR3(regs
->iir
),1);
575 ret
= emulate_ldd(regs
,R3(regs
->iir
),1);
583 ret
= emulate_stw(regs
,FR3(regs
->iir
),1);
589 ret
= emulate_std(regs
,R3(regs
->iir
),1);
596 ret
= ERR_NOTHANDLED
; /* "undefined", but lets kill them. */
600 switch (regs
->iir
& OPCODE2_MASK
)
604 ret
= emulate_ldd(regs
,R2(regs
->iir
),1);
608 ret
= emulate_std(regs
, R2(regs
->iir
),1);
611 ret
= emulate_ldd(regs
, R2(regs
->iir
),0);
614 ret
= emulate_std(regs
, R2(regs
->iir
),0);
618 switch (regs
->iir
& OPCODE3_MASK
)
622 ret
= emulate_ldw(regs
, R2(regs
->iir
),0);
625 ret
= emulate_ldw(regs
, R2(regs
->iir
),1);
630 ret
= emulate_stw(regs
, R2(regs
->iir
),1);
633 ret
= emulate_stw(regs
, R2(regs
->iir
),0);
636 switch (regs
->iir
& OPCODE4_MASK
)
639 ret
= emulate_ldh(regs
, R2(regs
->iir
));
643 ret
= emulate_ldw(regs
, R2(regs
->iir
),0);
646 ret
= emulate_sth(regs
, R2(regs
->iir
));
650 ret
= emulate_stw(regs
, R2(regs
->iir
),0);
654 if (ret
== 0 && modify
&& R1(regs
->iir
))
655 regs
->gr
[R1(regs
->iir
)] = newbase
;
658 if (ret
== ERR_NOTHANDLED
)
659 printk(KERN_CRIT
"Not-handled unaligned insn 0x%08lx\n", regs
->iir
);
661 DPRINTF("ret = %d\n", ret
);
666 * The unaligned handler failed.
667 * If we were called by __get_user() or __put_user() jump
668 * to it's exception fixup handler instead of crashing.
670 if (!user_mode(regs
) && fixup_exception(regs
))
673 printk(KERN_CRIT
"Unaligned handler failed, ret = %d\n", ret
);
674 die_if_kernel("Unaligned data reference", regs
, 28);
676 if (ret
== ERR_PAGEFAULT
)
678 force_sig_fault(SIGSEGV
, SEGV_MAPERR
,
679 (void __user
*)regs
->ior
);
684 /* couldn't handle it ... */
685 force_sig_fault(SIGBUS
, BUS_ADRALN
,
686 (void __user
*)regs
->ior
);
692 /* else we handled it, let life go on. */
697 * NB: check_unaligned() is only used for PCXS processors right
698 * now, so we only check for PA1.1 encodings at this point.
702 check_unaligned(struct pt_regs
*regs
)
704 unsigned long align_mask
;
706 /* Get alignment mask */
709 switch (regs
->iir
& OPCODE1_MASK
) {
727 switch (regs
->iir
& OPCODE4_MASK
) {
742 return (int)(regs
->ior
& align_mask
);