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1 /* Kernel link layout for various "sections"
2 *
3 * Copyright (C) 1999-2003 Matthew Wilcox <willy at parisc-linux.org>
4 * Copyright (C) 2000-2003 Paul Bame <bame at parisc-linux.org>
5 * Copyright (C) 2000 John Marvin <jsm at parisc-linux.org>
6 * Copyright (C) 2000 Michael Ang <mang with subcarrier.org>
7 * Copyright (C) 2002 Randolph Chung <tausq with parisc-linux.org>
8 * Copyright (C) 2003 James Bottomley <jejb with parisc-linux.org>
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25 #include <linux/config.h>
26 #include <asm-generic/vmlinux.lds.h>
27 /* needed for the processor specific cache alignment size */
28 #include <asm/cache.h>
29 #include <asm/page.h>
30
31 /* ld script to make hppa Linux kernel */
32 #ifndef CONFIG_64BIT
33 OUTPUT_FORMAT("elf32-hppa-linux")
34 OUTPUT_ARCH(hppa)
35 #else
36 OUTPUT_FORMAT("elf64-hppa-linux")
37 OUTPUT_ARCH(hppa:hppa2.0w)
38 #endif
39
40 ENTRY(_stext)
41 #ifndef CONFIG_64BIT
42 jiffies = jiffies_64 + 4;
43 #else
44 jiffies = jiffies_64;
45 #endif
46 SECTIONS
47 {
48
49 . = KERNEL_BINARY_TEXT_START;
50
51 _text = .; /* Text and read-only data */
52 .text ALIGN(16) : {
53 *(.text)
54 SCHED_TEXT
55 LOCK_TEXT
56 *(.text.do_softirq)
57 *(.text.sys_exit)
58 *(.text.do_sigaltstack)
59 *(.text.do_fork)
60 *(.text.*)
61 *(.fixup)
62 *(.lock.text) /* out-of-line lock text */
63 *(.gnu.warning)
64 } = 0
65
66 _etext = .; /* End of text section */
67
68 RODATA
69
70 /* writeable */
71 . = ALIGN(4096); /* Make sure this is paged aligned so
72 that we can properly leave these
73 as writable */
74 data_start = .;
75
76 . = ALIGN(16); /* Exception table */
77 __start___ex_table = .;
78 __ex_table : { *(__ex_table) }
79 __stop___ex_table = .;
80
81 __start___unwind = .; /* unwind info */
82 .PARISC.unwind : { *(.PARISC.unwind) }
83 __stop___unwind = .;
84
85 .data : { /* Data */
86 *(.data)
87 *(.data.vm0.pmd)
88 *(.data.vm0.pgd)
89 *(.data.vm0.pte)
90 CONSTRUCTORS
91 }
92
93 . = ALIGN(4096);
94 /* nosave data is really only used for software suspend...it's here
95 * just in case we ever implement it */
96 __nosave_begin = .;
97 .data_nosave : { *(.data.nosave) }
98 . = ALIGN(4096);
99 __nosave_end = .;
100
101 . = ALIGN(L1_CACHE_BYTES);
102 .data.cacheline_aligned : { *(.data.cacheline_aligned) }
103
104 /* PA-RISC locks requires 16-byte alignment */
105 . = ALIGN(16);
106 .data.lock_aligned : { *(.data.lock_aligned) }
107
108 _edata = .; /* End of data section */
109
110 . = ALIGN(16384); /* init_task */
111 .data.init_task : { *(.data.init_task) }
112
113 /* The interrupt stack is currently partially coded, but not yet
114 * implemented */
115 . = ALIGN(16384);
116 init_istack : { *(init_istack) }
117
118 #ifdef CONFIG_64BIT
119 . = ALIGN(16); /* Linkage tables */
120 .opd : { *(.opd) } PROVIDE (__gp = .);
121 .plt : { *(.plt) }
122 .dlt : { *(.dlt) }
123 #endif
124
125 . = ALIGN(16384);
126 __init_begin = .;
127 .init.text : {
128 _sinittext = .;
129 *(.init.text)
130 _einittext = .;
131 }
132 .init.data : { *(.init.data) }
133 . = ALIGN(16);
134 __setup_start = .;
135 .init.setup : { *(.init.setup) }
136 __setup_end = .;
137 __initcall_start = .;
138 .initcall.init : {
139 *(.initcall1.init)
140 *(.initcall2.init)
141 *(.initcall3.init)
142 *(.initcall4.init)
143 *(.initcall5.init)
144 *(.initcall6.init)
145 *(.initcall7.init)
146 }
147 __initcall_end = .;
148 __con_initcall_start = .;
149 .con_initcall.init : { *(.con_initcall.init) }
150 __con_initcall_end = .;
151 SECURITY_INIT
152 /* alternate instruction replacement. This is a mechanism x86 uses
153 * to detect the CPU type and replace generic instruction sequences
154 * with CPU specific ones. We don't currently do this in PA, but
155 * it seems like a good idea... */
156 . = ALIGN(4);
157 __alt_instructions = .;
158 .altinstructions : { *(.altinstructions) }
159 __alt_instructions_end = .;
160 .altinstr_replacement : { *(.altinstr_replacement) }
161 /* .exit.text is discard at runtime, not link time, to deal with references
162 from .altinstructions and .eh_frame */
163 .exit.text : { *(.exit.text) }
164 .exit.data : { *(.exit.data) }
165 . = ALIGN(4096);
166 __initramfs_start = .;
167 .init.ramfs : { *(.init.ramfs) }
168 __initramfs_end = .;
169 . = ALIGN(32);
170 __per_cpu_start = .;
171 .data.percpu : { *(.data.percpu) }
172 __per_cpu_end = .;
173 . = ALIGN(4096);
174 __init_end = .;
175 /* freed after init ends here */
176
177 __bss_start = .; /* BSS */
178 .bss : { *(.bss) *(COMMON) }
179 __bss_stop = .;
180
181 _end = . ;
182
183 /* Sections to be discarded */
184 /DISCARD/ : {
185 *(.exitcall.exit)
186 #ifdef CONFIG_64BIT
187 /* temporary hack until binutils is fixed to not emit these
188 for static binaries */
189 *(.interp)
190 *(.dynsym)
191 *(.dynstr)
192 *(.dynamic)
193 *(.hash)
194 #endif
195 }
196
197 /* Stabs debugging sections. */
198 .stab 0 : { *(.stab) }
199 .stabstr 0 : { *(.stabstr) }
200 .stab.excl 0 : { *(.stab.excl) }
201 .stab.exclstr 0 : { *(.stab.exclstr) }
202 .stab.index 0 : { *(.stab.index) }
203 .stab.indexstr 0 : { *(.stab.indexstr) }
204 .comment 0 : { *(.comment) }
205 .note 0 : { *(.note) }
206
207 }