arch/powerpc/boot/dts/fsl/p5020si-post.dtsi

   1 /*
   2  * P5020/5010 Silicon/SoC Device Tree Source (post include)
   3  *
   4  * Copyright 2011 - 2014 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 &bman_fbpr {
  36         compatible = "fsl,bman-fbpr";
  37         alloc-ranges = <0 0 0x10000 0>;
  38 };
  39
  40 &lbc {
  41         compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
  42         interrupts = <25 2 0 0>;
  43         #address-cells = <2>;
  44         #size-cells = <1>;
  45 };
  46
  47 /* controller at 0x200000 */
  48 &pci0 {
  49         compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
  50         device_type = "pci";
  51         #size-cells = <2>;
  52         #address-cells = <3>;
  53         bus-range = <0x0 0xff>;
  54         clock-frequency = <33333333>;
  55         interrupts = <16 2 1 15>;
  56         fsl,iommu-parent = <&pamu0>;
  57         fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
  58         pcie@0 {
  59                 reg = <0 0 0 0 0>;
  60                 #interrupt-cells = <1>;
  61                 #size-cells = <2>;
  62                 #address-cells = <3>;
  63                 device_type = "pci";
  64                 interrupts = <16 2 1 15>;
  65                 interrupt-map-mask = <0xf800 0 0 7>;
  66                 interrupt-map = <
  67                         /* IDSEL 0x0 */
  68                         0000 0 0 1 &mpic 40 1 0 0
  69                         0000 0 0 2 &mpic 1 1 0 0
  70                         0000 0 0 3 &mpic 2 1 0 0
  71                         0000 0 0 4 &mpic 3 1 0 0
  72                         >;
  73         };
  74 };
  75
  76 /* controller at 0x201000 */
  77 &pci1 {
  78         compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
  79         device_type = "pci";
  80         #size-cells = <2>;
  81         #address-cells = <3>;
  82         bus-range = <0 0xff>;
  83         clock-frequency = <33333333>;
  84         interrupts = <16 2 1 14>;
  85         fsl,iommu-parent = <&pamu0>;
  86         fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
  87         pcie@0 {
  88                 reg = <0 0 0 0 0>;
  89                 #interrupt-cells = <1>;
  90                 #size-cells = <2>;
  91                 #address-cells = <3>;
  92                 device_type = "pci";
  93                 interrupts = <16 2 1 14>;
  94                 interrupt-map-mask = <0xf800 0 0 7>;
  95                 interrupt-map = <
  96                         /* IDSEL 0x0 */
  97                         0000 0 0 1 &mpic 41 1 0 0
  98                         0000 0 0 2 &mpic 5 1 0 0
  99                         0000 0 0 3 &mpic 6 1 0 0
 100                         0000 0 0 4 &mpic 7 1 0 0
 101                         >;
 102         };
 103 };
 104
 105 /* controller at 0x202000 */
 106 &pci2 {
 107         compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
 108         device_type = "pci";
 109         #size-cells = <2>;
 110         #address-cells = <3>;
 111         bus-range = <0x0 0xff>;
 112         clock-frequency = <33333333>;
 113         interrupts = <16 2 1 13>;
 114         fsl,iommu-parent = <&pamu0>;
 115         fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
 116         pcie@0 {
 117                 reg = <0 0 0 0 0>;
 118                 #interrupt-cells = <1>;
 119                 #size-cells = <2>;
 120                 #address-cells = <3>;
 121                 device_type = "pci";
 122                 interrupts = <16 2 1 13>;
 123                 interrupt-map-mask = <0xf800 0 0 7>;
 124                 interrupt-map = <
 125                         /* IDSEL 0x0 */
 126                         0000 0 0 1 &mpic 42 1 0 0
 127                         0000 0 0 2 &mpic 9 1 0 0
 128                         0000 0 0 3 &mpic 10 1 0 0
 129                         0000 0 0 4 &mpic 11 1 0 0
 130                         >;
 131         };
 132 };
 133
 134 /* controller at 0x203000 */
 135 &pci3 {
 136         compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
 137         device_type = "pci";
 138         #size-cells = <2>;
 139         #address-cells = <3>;
 140         bus-range = <0x0 0xff>;
 141         clock-frequency = <33333333>;
 142         interrupts = <16 2 1 12>;
 143         fsl,iommu-parent = <&pamu0>;
 144         fsl,liodn-reg = <&guts 0x50c>; /* PEX4LIODNR */
 145         pcie@0 {
 146                 reg = <0 0 0 0 0>;
 147                 #interrupt-cells = <1>;
 148                 #size-cells = <2>;
 149                 #address-cells = <3>;
 150                 device_type = "pci";
 151                 interrupts = <16 2 1 12>;
 152                 interrupt-map-mask = <0xf800 0 0 7>;
 153                 interrupt-map = <
 154                         /* IDSEL 0x0 */
 155                         0000 0 0 1 &mpic 43 1 0 0
 156                         0000 0 0 2 &mpic 0 1 0 0
 157                         0000 0 0 3 &mpic 4 1 0 0
 158                         0000 0 0 4 &mpic 8 1 0 0
 159                         >;
 160         };
 161 };
 162
 163 &rio {
 164         compatible = "fsl,srio";
 165         interrupts = <16 2 1 11>;
 166         #address-cells = <2>;
 167         #size-cells = <2>;
 168         fsl,iommu-parent = <&pamu0>;
 169         ranges;
 170
 171         port1 {
 172                 #address-cells = <2>;
 173                 #size-cells = <2>;
 174                 cell-index = <1>;
 175                 fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
 176         };
 177
 178         port2 {
 179                 #address-cells = <2>;
 180                 #size-cells = <2>;
 181                 cell-index = <2>;
 182                 fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
 183         };
 184 };
 185
 186 &dcsr {
 187         #address-cells = <1>;
 188         #size-cells = <1>;
 189         compatible = "fsl,dcsr", "simple-bus";
 190
 191         dcsr-epu@0 {
 192                 compatible = "fsl,p5020-dcsr-epu", "fsl,dcsr-epu";
 193                 interrupts = <52 2 0 0
 194                               84 2 0 0
 195                               85 2 0 0>;
 196                 reg = <0x0 0x1000>;
 197         };
 198         dcsr-npc {
 199                 compatible = "fsl,dcsr-npc";
 200                 reg = <0x1000 0x1000 0x1000000 0x8000>;
 201         };
 202         dcsr-nxc@2000 {
 203                 compatible = "fsl,dcsr-nxc";
 204                 reg = <0x2000 0x1000>;
 205         };
 206         dcsr-corenet {
 207                 compatible = "fsl,dcsr-corenet";
 208                 reg = <0x8000 0x1000 0xB0000 0x1000>;
 209         };
 210         dcsr-dpaa@9000 {
 211                 compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
 212                 reg = <0x9000 0x1000>;
 213         };
 214         dcsr-ocn@11000 {
 215                 compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
 216                 reg = <0x11000 0x1000>;
 217         };
 218         dcsr-ddr@12000 {
 219                 compatible = "fsl,dcsr-ddr";
 220                 dev-handle = <&ddr1>;
 221                 reg = <0x12000 0x1000>;
 222         };
 223         dcsr-ddr@13000 {
 224                 compatible = "fsl,dcsr-ddr";
 225                 dev-handle = <&ddr2>;
 226                 reg = <0x13000 0x1000>;
 227         };
 228         dcsr-nal@18000 {
 229                 compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
 230                 reg = <0x18000 0x1000>;
 231         };
 232         dcsr-rcpm@22000 {
 233                 compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
 234                 reg = <0x22000 0x1000>;
 235         };
 236         dcsr-cpu-sb-proxy@40000 {
 237                 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 238                 cpu-handle = <&cpu0>;
 239                 reg = <0x40000 0x1000>;
 240         };
 241         dcsr-cpu-sb-proxy@41000 {
 242                 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 243                 cpu-handle = <&cpu1>;
 244                 reg = <0x41000 0x1000>;
 245         };
 246 };
 247
 248 /include/ "qoriq-bman1-portals.dtsi"
 249
 250 &soc {
 251         #address-cells = <1>;
 252         #size-cells = <1>;
 253         device_type = "soc";
 254         compatible = "simple-bus";
 255
 256         soc-sram-error {
 257                 compatible = "fsl,soc-sram-error";
 258                 interrupts = <16 2 1 29>;
 259         };
 260
 261         corenet-law@0 {
 262                 compatible = "fsl,corenet-law";
 263                 reg = <0x0 0x1000>;
 264                 fsl,num-laws = <32>;
 265         };
 266
 267         ddr1: memory-controller@8000 {
 268                 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
 269                 reg = <0x8000 0x1000>;
 270                 interrupts = <16 2 1 23>;
 271         };
 272
 273         ddr2: memory-controller@9000 {
 274                 compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
 275                 reg = <0x9000 0x1000>;
 276                 interrupts = <16 2 1 22>;
 277         };
 278
 279         cpc: l3-cache-controller@10000 {
 280                 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
 281                 reg = <0x10000 0x1000
 282                        0x11000 0x1000>;
 283                 interrupts = <16 2 1 27
 284                               16 2 1 26>;
 285         };
 286
 287         corenet-cf@18000 {
 288                 compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
 289                 reg = <0x18000 0x1000>;
 290                 interrupts = <16 2 1 31>;
 291                 fsl,ccf-num-csdids = <32>;
 292                 fsl,ccf-num-snoopids = <32>;
 293         };
 294
 295         iommu@20000 {
 296                 compatible = "fsl,pamu-v1.0", "fsl,pamu";
 297                 reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */
 298                 ranges = <0 0x20000 0x4000>;
 299                 #address-cells = <1>;
 300                 #size-cells = <1>;
 301                 interrupts = <
 302                         24 2 0 0
 303                         16 2 1 30>;
 304                 fsl,portid-mapping = <0x3c000000>;
 305
 306                 pamu0: pamu@0 {
 307                         reg = <0 0x1000>;
 308                         fsl,primary-cache-geometry = <32 1>;
 309                         fsl,secondary-cache-geometry = <128 2>;
 310                 };
 311
 312                 pamu1: pamu@1000 {
 313                         reg = <0x1000 0x1000>;
 314                         fsl,primary-cache-geometry = <32 1>;
 315                         fsl,secondary-cache-geometry = <128 2>;
 316                 };
 317
 318                 pamu2: pamu@2000 {
 319                         reg = <0x2000 0x1000>;
 320                         fsl,primary-cache-geometry = <32 1>;
 321                         fsl,secondary-cache-geometry = <128 2>;
 322                 };
 323
 324                 pamu3: pamu@3000 {
 325                         reg = <0x3000 0x1000>;
 326                         fsl,primary-cache-geometry = <32 1>;
 327                         fsl,secondary-cache-geometry = <128 2>;
 328                 };
 329         };
 330
 331 /include/ "qoriq-mpic.dtsi"
 332
 333         guts: global-utilities@e0000 {
 334                 compatible = "fsl,qoriq-device-config-1.0";
 335                 reg = <0xe0000 0xe00>;
 336                 fsl,has-rstcr;
 337                 #sleep-cells = <1>;
 338                 fsl,liodn-bits = <12>;
 339         };
 340
 341         pins: global-utilities@e0e00 {
 342                 compatible = "fsl,qoriq-pin-control-1.0";
 343                 reg = <0xe0e00 0x200>;
 344                 #sleep-cells = <2>;
 345         };
 346
 347 /include/ "qoriq-clockgen1.dtsi"
 348         global-utilities@e1000 {
 349                 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
 350         };
 351
 352         rcpm: global-utilities@e2000 {
 353                 compatible = "fsl,qoriq-rcpm-1.0";
 354                 reg = <0xe2000 0x1000>;
 355                 #sleep-cells = <1>;
 356         };
 357
 358         sfp: sfp@e8000 {
 359                 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
 360                 reg        = <0xe8000 0x1000>;
 361         };
 362
 363         serdes: serdes@ea000 {
 364                 compatible = "fsl,p5020-serdes";
 365                 reg        = <0xea000 0x1000>;
 366         };
 367
 368 /include/ "qoriq-dma-0.dtsi"
 369         dma@100300 {
 370                 fsl,iommu-parent = <&pamu0>;
 371                 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
 372         };
 373
 374 /include/ "qoriq-dma-1.dtsi"
 375         dma@101300 {
 376                 fsl,iommu-parent = <&pamu0>;
 377                 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
 378         };
 379
 380 /include/ "qoriq-espi-0.dtsi"
 381         spi@110000 {
 382                 fsl,espi-num-chipselects = <4>;
 383         };
 384
 385 /include/ "qoriq-esdhc-0.dtsi"
 386         sdhc@114000 {
 387                 fsl,iommu-parent = <&pamu1>;
 388                 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
 389                 sdhci,auto-cmd12;
 390         };
 391
 392 /include/ "qoriq-i2c-0.dtsi"
 393 /include/ "qoriq-i2c-1.dtsi"
 394 /include/ "qoriq-duart-0.dtsi"
 395 /include/ "qoriq-duart-1.dtsi"
 396 /include/ "qoriq-gpio-0.dtsi"
 397 /include/ "qoriq-usb2-mph-0.dtsi"
 398         usb0: usb@210000 {
 399                 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
 400                 fsl,iommu-parent = <&pamu1>;
 401                 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
 402                 phy_type = "utmi";
 403                 port0;
 404         };
 405
 406 /include/ "qoriq-usb2-dr-0.dtsi"
 407         usb1: usb@211000 {
 408                 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
 409                 fsl,iommu-parent = <&pamu1>;
 410                 fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
 411                 dr_mode = "host";
 412                 phy_type = "utmi";
 413         };
 414
 415 /include/ "qoriq-sata2-0.dtsi"
 416         sata@220000 {
 417                 fsl,iommu-parent = <&pamu1>;
 418                 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
 419         };
 420
 421 /include/ "qoriq-sata2-1.dtsi"
 422         sata@221000 {
 423                 fsl,iommu-parent = <&pamu1>;
 424                 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
 425         };
 426 /include/ "qoriq-sec4.2-0.dtsi"
 427         crypto@300000 {
 428                 fsl,iommu-parent = <&pamu1>;
 429         };
 430
 431 /include/ "qoriq-bman1.dtsi"
 432
 433 /include/ "qoriq-raid1.0-0.dtsi"
 434         raideng@320000 {
 435                 fsl,iommu-parent = <&pamu1>;
 436         };
 437 };