arch/powerpc/boot/dts/lite5200.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Lite5200 board Device Tree Source
   4  *
   5  * Copyright 2006-2007 Secret Lab Technologies Ltd.
   6  * Grant Likely <grant.likely@secretlab.ca>
   7  */
   8
   9 /dts-v1/;
  10
  11 / {
  12         model = "fsl,lite5200";
  13         compatible = "fsl,lite5200";
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16         interrupt-parent = <&mpc5200_pic>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 PowerPC,5200@0 {
  23                         device_type = "cpu";
  24                         reg = <0>;
  25                         d-cache-line-size = <32>;
  26                         i-cache-line-size = <32>;
  27                         d-cache-size = <0x4000>;        // L1, 16K
  28                         i-cache-size = <0x4000>;        // L1, 16K
  29                         timebase-frequency = <0>;       // from bootloader
  30                         bus-frequency = <0>;            // from bootloader
  31                         clock-frequency = <0>;          // from bootloader
  32                 };
  33         };
  34
  35         memory {
  36                 device_type = "memory";
  37                 reg = <0x00000000 0x04000000>;  // 64MB
  38         };
  39
  40         soc5200@f0000000 {
  41                 #address-cells = <1>;
  42                 #size-cells = <1>;
  43                 compatible = "fsl,mpc5200-immr";
  44                 ranges = <0 0xf0000000 0x0000c000>;
  45                 reg = <0xf0000000 0x00000100>;
  46                 bus-frequency = <0>;            // from bootloader
  47                 system-frequency = <0>;         // from bootloader
  48
  49                 cdm@200 {
  50                         compatible = "fsl,mpc5200-cdm";
  51                         reg = <0x200 0x38>;
  52                 };
  53
  54                 mpc5200_pic: interrupt-controller@500 {
  55                         // 5200 interrupts are encoded into two levels;
  56                         interrupt-controller;
  57                         #interrupt-cells = <3>;
  58                         compatible = "fsl,mpc5200-pic";
  59                         reg = <0x500 0x80>;
  60                 };
  61
  62                 timer@600 {     // General Purpose Timer
  63                         compatible = "fsl,mpc5200-gpt";
  64                         reg = <0x600 0x10>;
  65                         interrupts = <1 9 0>;
  66                         fsl,has-wdt;
  67                 };
  68
  69                 timer@610 {     // General Purpose Timer
  70                         compatible = "fsl,mpc5200-gpt";
  71                         reg = <0x610 0x10>;
  72                         interrupts = <1 10 0>;
  73                 };
  74
  75                 timer@620 {     // General Purpose Timer
  76                         compatible = "fsl,mpc5200-gpt";
  77                         reg = <0x620 0x10>;
  78                         interrupts = <1 11 0>;
  79                 };
  80
  81                 timer@630 {     // General Purpose Timer
  82                         compatible = "fsl,mpc5200-gpt";
  83                         reg = <0x630 0x10>;
  84                         interrupts = <1 12 0>;
  85                 };
  86
  87                 timer@640 {     // General Purpose Timer
  88                         compatible = "fsl,mpc5200-gpt";
  89                         reg = <0x640 0x10>;
  90                         interrupts = <1 13 0>;
  91                 };
  92
  93                 timer@650 {     // General Purpose Timer
  94                         compatible = "fsl,mpc5200-gpt";
  95                         reg = <0x650 0x10>;
  96                         interrupts = <1 14 0>;
  97                 };
  98
  99                 timer@660 {     // General Purpose Timer
 100                         compatible = "fsl,mpc5200-gpt";
 101                         reg = <0x660 0x10>;
 102                         interrupts = <1 15 0>;
 103                 };
 104
 105                 timer@670 {     // General Purpose Timer
 106                         compatible = "fsl,mpc5200-gpt";
 107                         reg = <0x670 0x10>;
 108                         interrupts = <1 16 0>;
 109                 };
 110
 111                 rtc@800 {       // Real time clock
 112                         compatible = "fsl,mpc5200-rtc";
 113                         reg = <0x800 0x100>;
 114                         interrupts = <1 5 0 1 6 0>;
 115                 };
 116
 117                 can@900 {
 118                         compatible = "fsl,mpc5200-mscan";
 119                         interrupts = <2 17 0>;
 120                         reg = <0x900 0x80>;
 121                 };
 122
 123                 can@980 {
 124                         compatible = "fsl,mpc5200-mscan";
 125                         interrupts = <2 18 0>;
 126                         reg = <0x980 0x80>;
 127                 };
 128
 129                 gpio@b00 {
 130                         compatible = "fsl,mpc5200-gpio";
 131                         reg = <0xb00 0x40>;
 132                         interrupts = <1 7 0>;
 133                         gpio-controller;
 134                         #gpio-cells = <2>;
 135                 };
 136
 137                 gpio@c00 {
 138                         compatible = "fsl,mpc5200-gpio-wkup";
 139                         reg = <0xc00 0x40>;
 140                         interrupts = <1 8 0 0 3 0>;
 141                         gpio-controller;
 142                         #gpio-cells = <2>;
 143                 };
 144
 145                 spi@f00 {
 146                         compatible = "fsl,mpc5200-spi";
 147                         reg = <0xf00 0x20>;
 148                         interrupts = <2 13 0 2 14 0>;
 149                 };
 150
 151                 usb@1000 {
 152                         compatible = "fsl,mpc5200-ohci","ohci-be";
 153                         reg = <0x1000 0xff>;
 154                         interrupts = <2 6 0>;
 155                 };
 156
 157                 dma-controller@1200 {
 158                         compatible = "fsl,mpc5200-bestcomm";
 159                         reg = <0x1200 0x80>;
 160                         interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
 161                                       3 4 0  3 5 0  3 6 0  3 7 0
 162                                       3 8 0  3 9 0  3 10 0  3 11 0
 163                                       3 12 0  3 13 0  3 14 0  3 15 0>;
 164                 };
 165
 166                 xlb@1f00 {
 167                         compatible = "fsl,mpc5200-xlb";
 168                         reg = <0x1f00 0x100>;
 169                 };
 170
 171                 serial@2000 {           // PSC1
 172                         compatible = "fsl,mpc5200-psc-uart";
 173                         cell-index = <0>;
 174                         reg = <0x2000 0x100>;
 175                         interrupts = <2 1 0>;
 176                 };
 177
 178                 // PSC2 in ac97 mode example
 179                 //ac97@2200 {           // PSC2
 180                 //      compatible = "fsl,mpc5200-psc-ac97";
 181                 //      cell-index = <1>;
 182                 //      reg = <0x2200 0x100>;
 183                 //      interrupts = <2 2 0>;
 184                 //};
 185
 186                 // PSC3 in CODEC mode example
 187                 //i2s@2400 {            // PSC3
 188                 //      compatible = "fsl,mpc5200-psc-i2s";
 189                 //      cell-index = <2>;
 190                 //      reg = <0x2400 0x100>;
 191                 //      interrupts = <2 3 0>;
 192                 //};
 193
 194                 // PSC4 in uart mode example
 195                 //serial@2600 {         // PSC4
 196                 //      compatible = "fsl,mpc5200-psc-uart";
 197                 //      cell-index = <3>;
 198                 //      reg = <0x2600 0x100>;
 199                 //      interrupts = <2 11 0>;
 200                 //};
 201
 202                 // PSC5 in uart mode example
 203                 //serial@2800 {         // PSC5
 204                 //      compatible = "fsl,mpc5200-psc-uart";
 205                 //      cell-index = <4>;
 206                 //      reg = <0x2800 0x100>;
 207                 //      interrupts = <2 12 0>;
 208                 //};
 209
 210                 // PSC6 in spi mode example
 211                 //spi@2c00 {            // PSC6
 212                 //      compatible = "fsl,mpc5200-psc-spi";
 213                 //      cell-index = <5>;
 214                 //      reg = <0x2c00 0x100>;
 215                 //      interrupts = <2 4 0>;
 216                 //};
 217
 218                 ethernet@3000 {
 219                         compatible = "fsl,mpc5200-fec";
 220                         reg = <0x3000 0x400>;
 221                         local-mac-address = [ 00 00 00 00 00 00 ];
 222                         interrupts = <2 5 0>;
 223                         phy-handle = <&phy0>;
 224                 };
 225
 226                 mdio@3000 {
 227                         #address-cells = <1>;
 228                         #size-cells = <0>;
 229                         compatible = "fsl,mpc5200-mdio";
 230                         reg = <0x3000 0x400>;   // fec range, since we need to setup fec interrupts
 231                         interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
 232
 233                         phy0: ethernet-phy@0 {
 234                                 reg = <0>;
 235                         };
 236                 };
 237
 238                 ata@3a00 {
 239                         compatible = "fsl,mpc5200-ata";
 240                         reg = <0x3a00 0x100>;
 241                         interrupts = <2 7 0>;
 242                 };
 243
 244                 i2c@3d00 {
 245                         #address-cells = <1>;
 246                         #size-cells = <0>;
 247                         compatible = "fsl,mpc5200-i2c","fsl-i2c";
 248                         reg = <0x3d00 0x40>;
 249                         interrupts = <2 15 0>;
 250                 };
 251
 252                 i2c@3d40 {
 253                         #address-cells = <1>;
 254                         #size-cells = <0>;
 255                         compatible = "fsl,mpc5200-i2c","fsl-i2c";
 256                         reg = <0x3d40 0x40>;
 257                         interrupts = <2 16 0>;
 258
 259                         eeprom@50 {
 260                                 compatible = "atmel,24c02";
 261                                 reg = <0x50>;
 262                         };
 263                 };
 264
 265                 sram@8000 {
 266                         compatible = "fsl,mpc5200-sram";
 267                         reg = <0x8000 0x4000>;
 268                 };
 269         };
 270
 271         pci@f0000d00 {
 272                 #interrupt-cells = <1>;
 273                 #size-cells = <2>;
 274                 #address-cells = <3>;
 275                 device_type = "pci";
 276                 compatible = "fsl,mpc5200-pci";
 277                 reg = <0xf0000d00 0x100>;
 278                 interrupt-map-mask = <0xf800 0 0 7>;
 279                 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
 280                                  0xc000 0 0 2 &mpc5200_pic 0 0 3
 281                                  0xc000 0 0 3 &mpc5200_pic 0 0 3
 282                                  0xc000 0 0 4 &mpc5200_pic 0 0 3>;
 283                 clock-frequency = <0>; // From boot loader
 284                 interrupts = <2 8 0 2 9 0 2 10 0>;
 285                 bus-range = <0 0>;
 286                 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
 287                           0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
 288                           0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
 289         };
 290
 291         localbus {
 292                 compatible = "fsl,mpc5200-lpb","simple-bus";
 293                 #address-cells = <2>;
 294                 #size-cells = <1>;
 295
 296                 ranges = <0 0 0xff000000 0x01000000>;
 297
 298                 flash@0,0 {
 299                         compatible = "amd,am29lv652d", "cfi-flash";
 300                         reg = <0 0 0x01000000>;
 301                         bank-width = <1>;
 302                 };
 303         };
 304 };