arch/powerpc/boot/dts/lite5200.dts

   1 /*
   2  * Lite5200 board Device Tree Source
   3  *
   4  * Copyright 2006-2007 Secret Lab Technologies Ltd.
   5  * Grant Likely <grant.likely@secretlab.ca>
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  */
  12
  13 /*
  14  * WARNING: Do not depend on this tree layout remaining static just yet.
  15  * The MPC5200 device tree conventions are still in flux
  16  * Keep an eye on the linuxppc-dev mailing list for more details
  17  */
  18
  19 / {
  20         model = "fsl,lite5200";
  21         // revision = "1.0";
  22         compatible = "fsl,lite5200\0generic-mpc5200";
  23         #address-cells = <1>;
  24         #size-cells = <1>;
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 PowerPC,5200@0 {
  31                         device_type = "cpu";
  32                         reg = <0>;
  33                         d-cache-line-size = <20>;
  34                         i-cache-line-size = <20>;
  35                         d-cache-size = <4000>;          // L1, 16K
  36                         i-cache-size = <4000>;          // L1, 16K
  37                         timebase-frequency = <0>;       // from bootloader
  38                         bus-frequency = <0>;            // from bootloader
  39                         clock-frequency = <0>;          // from bootloader
  40                         32-bit;
  41                 };
  42         };
  43
  44         memory {
  45                 device_type = "memory";
  46                 reg = <00000000 04000000>;      // 64MB
  47         };
  48
  49         soc5200@f0000000 {
  50                 model = "fsl,mpc5200";
  51                 compatible = "mpc5200";
  52                 revision = "";                  // from bootloader
  53                 #interrupt-cells = <3>;
  54                 device_type = "soc";
  55                 ranges = <0 f0000000 f0010000>;
  56                 reg = <f0000000 00010000>;
  57                 bus-frequency = <0>;            // from bootloader
  58                 system-frequency = <0>;         // from bootloader
  59
  60                 cdm@200 {
  61                         compatible = "mpc5200-cdm";
  62                         reg = <200 38>;
  63                 };
  64
  65                 mpc5200_pic: pic@500 {
  66                         // 5200 interrupts are encoded into two levels;
  67                         interrupt-controller;
  68                         #interrupt-cells = <3>;
  69                         device_type = "interrupt-controller";
  70                         compatible = "mpc5200-pic";
  71                         reg = <500 80>;
  72                         built-in;
  73                 };
  74
  75                 gpt@600 {       // General Purpose Timer
  76                         compatible = "mpc5200-gpt";
  77                         device_type = "gpt";
  78                         cell-index = <0>;
  79                         reg = <600 10>;
  80                         interrupts = <1 9 0>;
  81                         interrupt-parent = <&mpc5200_pic>;
  82                         has-wdt;
  83                 };
  84
  85                 gpt@610 {       // General Purpose Timer
  86                         compatible = "mpc5200-gpt";
  87                         device_type = "gpt";
  88                         cell-index = <1>;
  89                         reg = <610 10>;
  90                         interrupts = <1 a 0>;
  91                         interrupt-parent = <&mpc5200_pic>;
  92                 };
  93
  94                 gpt@620 {       // General Purpose Timer
  95                         compatible = "mpc5200-gpt";
  96                         device_type = "gpt";
  97                         cell-index = <2>;
  98                         reg = <620 10>;
  99                         interrupts = <1 b 0>;
 100                         interrupt-parent = <&mpc5200_pic>;
 101                 };
 102
 103                 gpt@630 {       // General Purpose Timer
 104                         compatible = "mpc5200-gpt";
 105                         device_type = "gpt";
 106                         cell-index = <3>;
 107                         reg = <630 10>;
 108                         interrupts = <1 c 0>;
 109                         interrupt-parent = <&mpc5200_pic>;
 110                 };
 111
 112                 gpt@640 {       // General Purpose Timer
 113                         compatible = "mpc5200-gpt";
 114                         device_type = "gpt";
 115                         cell-index = <4>;
 116                         reg = <640 10>;
 117                         interrupts = <1 d 0>;
 118                         interrupt-parent = <&mpc5200_pic>;
 119                 };
 120
 121                 gpt@650 {       // General Purpose Timer
 122                         compatible = "mpc5200-gpt";
 123                         device_type = "gpt";
 124                         cell-index = <5>;
 125                         reg = <650 10>;
 126                         interrupts = <1 e 0>;
 127                         interrupt-parent = <&mpc5200_pic>;
 128                 };
 129
 130                 gpt@660 {       // General Purpose Timer
 131                         compatible = "mpc5200-gpt";
 132                         device_type = "gpt";
 133                         cell-index = <6>;
 134                         reg = <660 10>;
 135                         interrupts = <1 f 0>;
 136                         interrupt-parent = <&mpc5200_pic>;
 137                 };
 138
 139                 gpt@670 {       // General Purpose Timer
 140                         compatible = "mpc5200-gpt";
 141                         device_type = "gpt";
 142                         cell-index = <7>;
 143                         reg = <670 10>;
 144                         interrupts = <1 10 0>;
 145                         interrupt-parent = <&mpc5200_pic>;
 146                 };
 147
 148                 rtc@800 {       // Real time clock
 149                         compatible = "mpc5200-rtc";
 150                         device_type = "rtc";
 151                         reg = <800 100>;
 152                         interrupts = <1 5 0 1 6 0>;
 153                         interrupt-parent = <&mpc5200_pic>;
 154                 };
 155
 156                 mscan@900 {
 157                         device_type = "mscan";
 158                         compatible = "mpc5200-mscan";
 159                         cell-index = <0>;
 160                         interrupts = <2 11 0>;
 161                         interrupt-parent = <&mpc5200_pic>;
 162                         reg = <900 80>;
 163                 };
 164
 165                 mscan@980 {
 166                         device_type = "mscan";
 167                         compatible = "mpc5200-mscan";
 168                         cell-index = <1>;
 169                         interrupts = <2 12 0>;
 170                         interrupt-parent = <&mpc5200_pic>;
 171                         reg = <980 80>;
 172                 };
 173
 174                 gpio@b00 {
 175                         compatible = "mpc5200-gpio";
 176                         reg = <b00 40>;
 177                         interrupts = <1 7 0>;
 178                         interrupt-parent = <&mpc5200_pic>;
 179                 };
 180
 181                 gpio-wkup@c00 {
 182                         compatible = "mpc5200-gpio-wkup";
 183                         reg = <c00 40>;
 184                         interrupts = <1 8 0 0 3 0>;
 185                         interrupt-parent = <&mpc5200_pic>;
 186                 };
 187
 188                 pci@0d00 {
 189                         #interrupt-cells = <1>;
 190                         #size-cells = <2>;
 191                         #address-cells = <3>;
 192                         device_type = "pci";
 193                         compatible = "mpc5200-pci";
 194                         reg = <d00 100>;
 195                         interrupt-map-mask = <f800 0 0 7>;
 196                         interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
 197                                          c000 0 0 2 &mpc5200_pic 0 0 3
 198                                          c000 0 0 3 &mpc5200_pic 0 0 3
 199                                          c000 0 0 4 &mpc5200_pic 0 0 3>;
 200                         clock-frequency = <0>; // From boot loader
 201                         interrupts = <2 8 0 2 9 0 2 a 0>;
 202                         interrupt-parent = <&mpc5200_pic>;
 203                         bus-range = <0 0>;
 204                         ranges = <42000000 0 80000000 80000000 0 20000000
 205                                   02000000 0 a0000000 a0000000 0 10000000
 206                                   01000000 0 00000000 b0000000 0 01000000>;
 207                 };
 208
 209                 spi@f00 {
 210                         device_type = "spi";
 211                         compatible = "mpc5200-spi";
 212                         reg = <f00 20>;
 213                         interrupts = <2 d 0 2 e 0>;
 214                         interrupt-parent = <&mpc5200_pic>;
 215                 };
 216
 217                 usb@1000 {
 218                         device_type = "usb-ohci-be";
 219                         compatible = "mpc5200-ohci\0ohci-be";
 220                         reg = <1000 ff>;
 221                         interrupts = <2 6 0>;
 222                         interrupt-parent = <&mpc5200_pic>;
 223                 };
 224
 225                 bestcomm@1200 {
 226                         device_type = "dma-controller";
 227                         compatible = "mpc5200-bestcomm";
 228                         reg = <1200 80>;
 229                         interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
 230                                       3 4 0  3 5 0  3 6 0  3 7 0
 231                                       3 8 0  3 9 0  3 a 0  3 b 0
 232                                       3 c 0  3 d 0  3 e 0  3 f 0>;
 233                         interrupt-parent = <&mpc5200_pic>;
 234                 };
 235
 236                 xlb@1f00 {
 237                         compatible = "mpc5200-xlb";
 238                         reg = <1f00 100>;
 239                 };
 240
 241                 serial@2000 {           // PSC1
 242                         device_type = "serial";
 243                         compatible = "mpc5200-psc-uart";
 244                         port-number = <0>;  // Logical port assignment
 245                         cell-index = <0>;
 246                         reg = <2000 100>;
 247                         interrupts = <2 1 0>;
 248                         interrupt-parent = <&mpc5200_pic>;
 249                 };
 250
 251                 // PSC2 in ac97 mode example
 252                 //ac97@2200 {           // PSC2
 253                 //      device_type = "sound";
 254                 //      compatible = "mpc5200-psc-ac97";
 255                 //      cell-index = <1>;
 256                 //      reg = <2200 100>;
 257                 //      interrupts = <2 2 0>;
 258                 //      interrupt-parent = <&mpc5200_pic>;
 259                 //};
 260
 261                 // PSC3 in CODEC mode example
 262                 //i2s@2400 {            // PSC3
 263                 //      device_type = "sound";
 264                 //      compatible = "mpc5200-psc-i2s";
 265                 //      cell-index = <2>;
 266                 //      reg = <2400 100>;
 267                 //      interrupts = <2 3 0>;
 268                 //      interrupt-parent = <&mpc5200_pic>;
 269                 //};
 270
 271                 // PSC4 in uart mode example
 272                 //serial@2600 {         // PSC4
 273                 //      device_type = "serial";
 274                 //      compatible = "mpc5200-psc-uart";
 275                 //      cell-index = <3>;
 276                 //      reg = <2600 100>;
 277                 //      interrupts = <2 b 0>;
 278                 //      interrupt-parent = <&mpc5200_pic>;
 279                 //};
 280
 281                 // PSC5 in uart mode example
 282                 //serial@2800 {         // PSC5
 283                 //      device_type = "serial";
 284                 //      compatible = "mpc5200-psc-uart";
 285                 //      cell-index = <4>;
 286                 //      reg = <2800 100>;
 287                 //      interrupts = <2 c 0>;
 288                 //      interrupt-parent = <&mpc5200_pic>;
 289                 //};
 290
 291                 // PSC6 in spi mode example
 292                 //spi@2c00 {            // PSC6
 293                 //      device_type = "spi";
 294                 //      compatible = "mpc5200-psc-spi";
 295                 //      cell-index = <5>;
 296                 //      reg = <2c00 100>;
 297                 //      interrupts = <2 4 0>;
 298                 //      interrupt-parent = <&mpc5200_pic>;
 299                 //};
 300
 301                 ethernet@3000 {
 302                         device_type = "network";
 303                         compatible = "mpc5200-fec";
 304                         reg = <3000 800>;
 305                         mac-address = [ 02 03 04 05 06 07 ]; // Bad!
 306                         interrupts = <2 5 0>;
 307                         interrupt-parent = <&mpc5200_pic>;
 308                 };
 309
 310                 ata@3a00 {
 311                         device_type = "ata";
 312                         compatible = "mpc5200-ata";
 313                         reg = <3a00 100>;
 314                         interrupts = <2 7 0>;
 315                         interrupt-parent = <&mpc5200_pic>;
 316                 };
 317
 318                 i2c@3d00 {
 319                         device_type = "i2c";
 320                         compatible = "mpc5200-i2c\0fsl-i2c";
 321                         cell-index = <0>;
 322                         reg = <3d00 40>;
 323                         interrupts = <2 f 0>;
 324                         interrupt-parent = <&mpc5200_pic>;
 325                         fsl5200-clocking;
 326                 };
 327
 328                 i2c@3d40 {
 329                         device_type = "i2c";
 330                         compatible = "mpc5200-i2c\0fsl-i2c";
 331                         cell-index = <1>;
 332                         reg = <3d40 40>;
 333                         interrupts = <2 10 0>;
 334                         interrupt-parent = <&mpc5200_pic>;
 335                         fsl5200-clocking;
 336                 };
 337                 sram@8000 {
 338                         device_type = "sram";
 339                         compatible = "mpc5200-sram\0sram";
 340                         reg = <8000 4000>;
 341                 };
 342         };
 343 };