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1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_4K_H
3 #define _ASM_POWERPC_BOOK3S_64_HASH_4K_H
5 * Entries per page directory level. The PTE level must use a 64b record
6 * for each page table entry. The PMD and PGD level use a 32b record for
7 * each entry by assuming that each entry is page aligned.
9 #define H_PTE_INDEX_SIZE 9
10 #define H_PMD_INDEX_SIZE 7
11 #define H_PUD_INDEX_SIZE 9
12 #define H_PGD_INDEX_SIZE 9
15 * Each context is 512TB. But on 4k we restrict our max TASK size to 64TB
16 * Hence also limit max EA bits to 64TB.
18 #define MAX_EA_BITS_PER_CONTEXT 46
21 #define H_PTE_TABLE_SIZE (sizeof(pte_t) << H_PTE_INDEX_SIZE)
22 #define H_PMD_TABLE_SIZE (sizeof(pmd_t) << H_PMD_INDEX_SIZE)
23 #define H_PUD_TABLE_SIZE (sizeof(pud_t) << H_PUD_INDEX_SIZE)
24 #define H_PGD_TABLE_SIZE (sizeof(pgd_t) << H_PGD_INDEX_SIZE)
26 #define H_PAGE_F_GIX_SHIFT 53
27 #define H_PAGE_F_SECOND _RPAGE_RPN44 /* HPTE is in 2ndary HPTEG */
28 #define H_PAGE_F_GIX (_RPAGE_RPN43 | _RPAGE_RPN42 | _RPAGE_RPN41)
29 #define H_PAGE_BUSY _RPAGE_RSV1 /* software: PTE & hash are busy */
30 #define H_PAGE_HASHPTE _RPAGE_RSV2 /* software: PTE & hash are busy */
32 /* PTE flags to conserve for HPTE identification */
33 #define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | \
34 H_PAGE_F_SECOND | H_PAGE_F_GIX)
36 * Not supported by 4k linux page size
38 #define H_PAGE_4K_PFN 0x0
39 #define H_PAGE_THP_HUGE 0x0
40 #define H_PAGE_COMBO 0x0
41 #define H_PTE_FRAG_NR 0
42 #define H_PTE_FRAG_SIZE_SHIFT 0
44 /* memory key bits, only 8 keys supported */
45 #define H_PTE_PKEY_BIT0 0
46 #define H_PTE_PKEY_BIT1 0
47 #define H_PTE_PKEY_BIT2 _RPAGE_RSV3
48 #define H_PTE_PKEY_BIT3 _RPAGE_RSV4
49 #define H_PTE_PKEY_BIT4 _RPAGE_RSV5
52 * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range()
54 #define remap_4k_pfn(vma, addr, pfn, prot) \
55 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
57 #ifdef CONFIG_HUGETLB_PAGE
58 static inline int hash__hugepd_ok(hugepd_t hpd
)
60 unsigned long hpdval
= hpd_val(hpd
);
62 * if it is not a pte and have hugepd shift mask
63 * set, then it is a hugepd directory pointer
65 if (!(hpdval
& _PAGE_PTE
) &&
66 ((hpdval
& HUGEPD_SHIFT_MASK
) != 0))
73 * 4K PTE format is different from 64K PTE format. Saving the hash_slot is just
74 * a matter of returning the PTE bits that need to be modified. On 64K PTE,
75 * things are a little more involved and hence needs many more parameters to
76 * accomplish the same. However we want to abstract this out from the caller by
77 * keeping the prototype consistent across the two formats.
79 static inline unsigned long pte_set_hidx(pte_t
*ptep
, real_pte_t rpte
,
80 unsigned int subpg_index
, unsigned long hidx
,
83 return (hidx
<< H_PAGE_F_GIX_SHIFT
) &
84 (H_PAGE_F_SECOND
| H_PAGE_F_GIX
);
87 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
89 static inline char *get_hpte_slot_array(pmd_t
*pmdp
)
95 static inline unsigned int hpte_valid(unsigned char *hpte_slot_array
, int index
)
101 static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array
,
108 static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array
,
109 unsigned int index
, unsigned int hidx
)
114 static inline int hash__pmd_trans_huge(pmd_t pmd
)
119 static inline int hash__pmd_same(pmd_t pmd_a
, pmd_t pmd_b
)
125 static inline pmd_t
hash__pmd_mkhuge(pmd_t pmd
)
131 extern unsigned long hash__pmd_hugepage_update(struct mm_struct
*mm
,
132 unsigned long addr
, pmd_t
*pmdp
,
133 unsigned long clr
, unsigned long set
);
134 extern pmd_t
hash__pmdp_collapse_flush(struct vm_area_struct
*vma
,
135 unsigned long address
, pmd_t
*pmdp
);
136 extern void hash__pgtable_trans_huge_deposit(struct mm_struct
*mm
, pmd_t
*pmdp
,
138 extern pgtable_t
hash__pgtable_trans_huge_withdraw(struct mm_struct
*mm
, pmd_t
*pmdp
);
139 extern pmd_t
hash__pmdp_huge_get_and_clear(struct mm_struct
*mm
,
140 unsigned long addr
, pmd_t
*pmdp
);
141 extern int hash__has_transparent_hugepage(void);
144 #endif /* !__ASSEMBLY__ */
146 #endif /* _ASM_POWERPC_BOOK3S_64_HASH_4K_H */