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1 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_H
2 #define _ASM_POWERPC_BOOK3S_64_HASH_H
6 * Common bits between 4K and 64K pages in a linux-style PTE.
7 * Additional bits may be defined in pgtable-hash64-*.h
9 * Note: We only support user read/write permissions. Supervisor always
10 * have full read/write to pages above PAGE_OFFSET (pages below that
11 * always use the user access permissions).
13 * We could create separate kernel read-only if we used the 3 PP bits
14 * combinations that newer processors provide but we currently don't.
16 #define _PAGE_BIT_SWAP_TYPE 0
18 #define _PAGE_EXEC 0x00001 /* execute permission */
19 #define _PAGE_RW 0x00002 /* read & write access allowed */
20 #define _PAGE_READ 0x00004 /* read access allowed */
21 #define _PAGE_USER 0x00008 /* page may be accessed by userspace */
22 #define _PAGE_GUARDED 0x00010 /* G: guarded (side-effect) page */
23 /* M (memory coherence) is always set in the HPTE, so we don't need it here */
24 #define _PAGE_COHERENT 0x0
25 #define _PAGE_NO_CACHE 0x00020 /* I: cache inhibit */
26 #define _PAGE_WRITETHRU 0x00040 /* W: cache write-through */
27 #define _PAGE_DIRTY 0x00080 /* C: page changed */
28 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */
29 #define _PAGE_SPECIAL 0x00400 /* software: special page */
30 #define _PAGE_BUSY 0x00800 /* software: PTE & hash are busy */
32 #ifdef CONFIG_MEM_SOFT_DIRTY
33 #define _PAGE_SOFT_DIRTY 0x200 /* software: software dirty tracking */
35 #define _PAGE_SOFT_DIRTY 0x000
38 #define _PAGE_F_GIX_SHIFT 57
39 #define _PAGE_F_GIX (7ul << 57) /* HPTE index within HPTEG */
40 #define _PAGE_F_SECOND (1ul << 60) /* HPTE is in 2ndary HPTEG */
41 #define _PAGE_HASHPTE (1ul << 61) /* PTE has associated HPTE */
42 #define _PAGE_PTE (1ul << 62) /* distinguishes PTEs from pointers */
43 #define _PAGE_PRESENT (1ul << 63) /* pte contains a translation */
46 * We need to differentiate between explicit huge page and THP huge
47 * page, since THP huge page also need to track real subpage details
49 #define _PAGE_THP_HUGE _PAGE_4K_PFN
52 * set of bits not changed in pmd_modify.
54 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
55 _PAGE_ACCESSED | _PAGE_THP_HUGE | _PAGE_PTE | \
59 #ifdef CONFIG_PPC_64K_PAGES
60 #include <asm/book3s/64/hash-64k.h>
62 #include <asm/book3s/64/hash-4k.h>
66 * Size of EA range mapped by our pagetables.
68 #define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
69 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
70 #define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
72 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
73 #define PMD_CACHE_INDEX (PMD_INDEX_SIZE + 1)
75 #define PMD_CACHE_INDEX PMD_INDEX_SIZE
78 * Define the address range of the kernel non-linear virtual area
80 #define KERN_VIRT_START ASM_CONST(0xD000000000000000)
81 #define KERN_VIRT_SIZE ASM_CONST(0x0000100000000000)
84 * The vmalloc space starts at the beginning of that region, and
85 * occupies half of it on hash CPUs and a quarter of it on Book3E
86 * (we keep a quarter for the virtual memmap)
88 #define VMALLOC_START KERN_VIRT_START
89 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1)
90 #define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
95 #define REGION_SHIFT 60UL
96 #define REGION_MASK (0xfUL << REGION_SHIFT)
97 #define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT)
99 #define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START))
100 #define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET))
101 #define VMEMMAP_REGION_ID (0xfUL) /* Server only */
102 #define USER_REGION_ID (0UL)
105 * Defines the address of the vmemap area, in its own region on
108 #define VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT)
110 #ifdef CONFIG_PPC_MM_SLICES
111 #define HAVE_ARCH_UNMAPPED_AREA
112 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
113 #endif /* CONFIG_PPC_MM_SLICES */
115 /* No separate kernel read-only */
116 #define _PAGE_KERNEL_RW (_PAGE_RW | _PAGE_DIRTY) /* user access blocked by key */
117 #define _PAGE_KERNEL_RO _PAGE_KERNEL_RW
118 #define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
120 /* Strong Access Ordering */
121 #define _PAGE_SAO (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT)
123 /* No page size encoding in the linux PTE */
124 #define _PAGE_PSIZE 0
127 #define _PTEIDX_SECONDARY 0x8
128 #define _PTEIDX_GROUP_IX 0x7
130 #define _PTE_NONE_MASK _PAGE_HPTEFLAGS
132 * The mask convered by the RPN must be a ULL on 32-bit platforms with
135 #define PTE_RPN_MASK (((1UL << PTE_RPN_SIZE) - 1) << PTE_RPN_SHIFT)
137 * _PAGE_CHG_MASK masks of bits that are to be preserved across
140 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
141 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
144 * Mask of bits returned by pte_pgprot()
146 #define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
147 _PAGE_WRITETHRU | _PAGE_4K_PFN | \
148 _PAGE_USER | _PAGE_ACCESSED | \
149 _PAGE_RW | _PAGE_DIRTY | _PAGE_EXEC | \
152 * We define 2 sets of base prot bits, one for basic pages (ie,
153 * cacheable kernel and user pages) and one for non cacheable
154 * pages. We always set _PAGE_COHERENT when SMP is enabled or
155 * the processor might need it for DMA coherency.
157 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
158 #define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT)
160 /* Permission masks used to generate the __P and __S table,
162 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
164 * Write permissions imply read permissions for now (we could make write-only
165 * pages on BookE but we don't bother for now). Execute permission control is
166 * possible on platforms that define _PAGE_EXEC
168 * Note due to the way vm flags are laid out, the bits are XWR
170 #define PAGE_NONE __pgprot(_PAGE_BASE)
171 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
172 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | \
174 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER )
175 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
176 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER )
177 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
179 #define __P000 PAGE_NONE
180 #define __P001 PAGE_READONLY
181 #define __P010 PAGE_COPY
182 #define __P011 PAGE_COPY
183 #define __P100 PAGE_READONLY_X
184 #define __P101 PAGE_READONLY_X
185 #define __P110 PAGE_COPY_X
186 #define __P111 PAGE_COPY_X
188 #define __S000 PAGE_NONE
189 #define __S001 PAGE_READONLY
190 #define __S010 PAGE_SHARED
191 #define __S011 PAGE_SHARED
192 #define __S100 PAGE_READONLY_X
193 #define __S101 PAGE_READONLY_X
194 #define __S110 PAGE_SHARED_X
195 #define __S111 PAGE_SHARED_X
197 /* Permission masks used for kernel mappings */
198 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
199 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
201 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
202 _PAGE_NO_CACHE | _PAGE_GUARDED)
203 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
204 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
205 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
207 /* Protection used for kernel text. We want the debuggers to be able to
208 * set breakpoints anywhere, so don't write protect the kernel text
209 * on platforms where such control is possible.
211 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
212 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
213 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X
215 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
218 /* Make modules code happy. We don't set RO yet */
219 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X
220 #define PAGE_AGP (PAGE_KERNEL_NC)
222 #define PMD_BAD_BITS (PTE_TABLE_SIZE-1)
223 #define PUD_BAD_BITS (PMD_TABLE_SIZE-1)
226 #define pmd_bad(pmd) (pmd_val(pmd) & PMD_BAD_BITS)
227 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
229 #define pud_bad(pud) (pud_val(pud) & PUD_BAD_BITS)
230 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
232 /* Pointers in the page table tree are physical addresses */
233 #define __pgtable_ptr_val(ptr) __pa(ptr)
235 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
236 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
237 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
238 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
240 extern void hpte_need_flush(struct mm_struct
*mm
, unsigned long addr
,
241 pte_t
*ptep
, unsigned long pte
, int huge
);
242 extern unsigned long htab_convert_pte_flags(unsigned long pteflags
);
243 /* Atomic PTE updates */
244 static inline unsigned long pte_update(struct mm_struct
*mm
,
246 pte_t
*ptep
, unsigned long clr
,
250 __be64 old_be
, tmp_be
;
253 __asm__
__volatile__(
254 "1: ldarx %0,0,%3 # pte_update\n\
261 : "=&r" (old_be
), "=&r" (tmp_be
), "=m" (*ptep
)
262 : "r" (ptep
), "r" (cpu_to_be64(clr
)), "m" (*ptep
),
263 "r" (cpu_to_be64(_PAGE_BUSY
)), "r" (cpu_to_be64(set
))
265 /* huge pages use the old page table lock */
267 assert_pte_locked(mm
, addr
);
269 old
= be64_to_cpu(old_be
);
270 if (old
& _PAGE_HASHPTE
)
271 hpte_need_flush(mm
, addr
, ptep
, old
, huge
);
276 static inline int __ptep_test_and_clear_young(struct mm_struct
*mm
,
277 unsigned long addr
, pte_t
*ptep
)
281 if ((pte_val(*ptep
) & (_PAGE_ACCESSED
| _PAGE_HASHPTE
)) == 0)
283 old
= pte_update(mm
, addr
, ptep
, _PAGE_ACCESSED
, 0, 0);
284 return (old
& _PAGE_ACCESSED
) != 0;
286 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
287 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
290 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
294 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
295 static inline void ptep_set_wrprotect(struct mm_struct
*mm
, unsigned long addr
,
299 if ((pte_val(*ptep
) & _PAGE_RW
) == 0)
302 pte_update(mm
, addr
, ptep
, _PAGE_RW
, 0, 0);
305 static inline void huge_ptep_set_wrprotect(struct mm_struct
*mm
,
306 unsigned long addr
, pte_t
*ptep
)
308 if ((pte_val(*ptep
) & _PAGE_RW
) == 0)
311 pte_update(mm
, addr
, ptep
, _PAGE_RW
, 0, 1);
315 * We currently remove entries from the hashtable regardless of whether
316 * the entry was young or dirty. The generic routines only flush if the
317 * entry was young or dirty which is not good enough.
319 * We should be more intelligent about this but for the moment we override
320 * these functions and force a tlb flush unconditionally
322 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
323 #define ptep_clear_flush_young(__vma, __address, __ptep) \
325 int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
330 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
331 static inline pte_t
ptep_get_and_clear(struct mm_struct
*mm
,
332 unsigned long addr
, pte_t
*ptep
)
334 unsigned long old
= pte_update(mm
, addr
, ptep
, ~0UL, 0, 0);
338 static inline void pte_clear(struct mm_struct
*mm
, unsigned long addr
,
341 pte_update(mm
, addr
, ptep
, ~0UL, 0, 0);
345 /* Set the dirty and/or accessed bits atomically in a linux PTE, this
346 * function doesn't need to flush the hash entry
348 static inline void __ptep_set_access_flags(pte_t
*ptep
, pte_t entry
)
350 __be64 old
, tmp
, val
, mask
;
352 mask
= cpu_to_be64(_PAGE_DIRTY
| _PAGE_ACCESSED
| _PAGE_RW
|
353 _PAGE_EXEC
| _PAGE_SOFT_DIRTY
);
355 val
= pte_raw(entry
) & mask
;
357 __asm__
__volatile__(
364 :"=&r" (old
), "=&r" (tmp
), "=m" (*ptep
)
365 :"r" (val
), "r" (ptep
), "m" (*ptep
), "r" (cpu_to_be64(_PAGE_BUSY
))
369 static inline int pgd_bad(pgd_t pgd
)
371 return (pgd_val(pgd
) == 0);
374 #define __HAVE_ARCH_PTE_SAME
375 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
376 static inline unsigned long pgd_page_vaddr(pgd_t pgd
)
378 return (unsigned long)__va(pgd_val(pgd
) & ~PGD_MASKED_BITS
);
382 /* Generic accessors to PTE bits */
383 static inline int pte_write(pte_t pte
) { return !!(pte_val(pte
) & _PAGE_RW
);}
384 static inline int pte_dirty(pte_t pte
) { return !!(pte_val(pte
) & _PAGE_DIRTY
); }
385 static inline int pte_young(pte_t pte
) { return !!(pte_val(pte
) & _PAGE_ACCESSED
); }
386 static inline int pte_special(pte_t pte
) { return !!(pte_val(pte
) & _PAGE_SPECIAL
); }
387 static inline int pte_none(pte_t pte
) { return (pte_val(pte
) & ~_PTE_NONE_MASK
) == 0; }
388 static inline pgprot_t
pte_pgprot(pte_t pte
) { return __pgprot(pte_val(pte
) & PAGE_PROT_BITS
); }
390 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
391 static inline bool pte_soft_dirty(pte_t pte
)
393 return !!(pte_val(pte
) & _PAGE_SOFT_DIRTY
);
395 static inline pte_t
pte_mksoft_dirty(pte_t pte
)
397 return __pte(pte_val(pte
) | _PAGE_SOFT_DIRTY
);
400 static inline pte_t
pte_clear_soft_dirty(pte_t pte
)
402 return __pte(pte_val(pte
) & ~_PAGE_SOFT_DIRTY
);
404 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
406 #ifdef CONFIG_NUMA_BALANCING
408 * These work without NUMA balancing but the kernel does not care. See the
409 * comment in include/asm-generic/pgtable.h . On powerpc, this will only
410 * work for user pages and always return true for kernel pages.
412 static inline int pte_protnone(pte_t pte
)
414 return (pte_val(pte
) &
415 (_PAGE_PRESENT
| _PAGE_USER
)) == _PAGE_PRESENT
;
417 #endif /* CONFIG_NUMA_BALANCING */
419 static inline int pte_present(pte_t pte
)
421 return !!(pte_val(pte
) & _PAGE_PRESENT
);
424 /* Conversion functions: convert a page and protection to a page entry,
425 * and a page entry and page directory to the page they refer to.
427 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
430 static inline pte_t
pfn_pte(unsigned long pfn
, pgprot_t pgprot
)
432 return __pte((((pte_basic_t
)(pfn
) << PTE_RPN_SHIFT
) & PTE_RPN_MASK
) |
436 static inline unsigned long pte_pfn(pte_t pte
)
438 return (pte_val(pte
) & PTE_RPN_MASK
) >> PTE_RPN_SHIFT
;
441 /* Generic modifiers for PTE bits */
442 static inline pte_t
pte_wrprotect(pte_t pte
)
444 return __pte(pte_val(pte
) & ~_PAGE_RW
);
447 static inline pte_t
pte_mkclean(pte_t pte
)
449 return __pte(pte_val(pte
) & ~_PAGE_DIRTY
);
452 static inline pte_t
pte_mkold(pte_t pte
)
454 return __pte(pte_val(pte
) & ~_PAGE_ACCESSED
);
457 static inline pte_t
pte_mkwrite(pte_t pte
)
459 return __pte(pte_val(pte
) | _PAGE_RW
);
462 static inline pte_t
pte_mkdirty(pte_t pte
)
464 return __pte(pte_val(pte
) | _PAGE_DIRTY
| _PAGE_SOFT_DIRTY
);
467 static inline pte_t
pte_mkyoung(pte_t pte
)
469 return __pte(pte_val(pte
) | _PAGE_ACCESSED
);
472 static inline pte_t
pte_mkspecial(pte_t pte
)
474 return __pte(pte_val(pte
) | _PAGE_SPECIAL
);
477 static inline pte_t
pte_mkhuge(pte_t pte
)
482 static inline pte_t
pte_modify(pte_t pte
, pgprot_t newprot
)
484 return __pte((pte_val(pte
) & _PAGE_CHG_MASK
) | pgprot_val(newprot
));
487 /* This low level function performs the actual PTE insertion
488 * Setting the PTE depends on the MMU type and other factors. It's
489 * an horrible mess that I'm not going to try to clean up now but
490 * I'm keeping it in one place rather than spread around
492 static inline void __set_pte_at(struct mm_struct
*mm
, unsigned long addr
,
493 pte_t
*ptep
, pte_t pte
, int percpu
)
496 * Anything else just stores the PTE normally. That covers all 64-bit
497 * cases, and 32-bit non-hash with 32-bit PTEs.
503 * Macro to mark a page protection value as "uncacheable".
506 #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
509 #define pgprot_noncached pgprot_noncached
510 static inline pgprot_t
pgprot_noncached(pgprot_t prot
)
512 return __pgprot((pgprot_val(prot
) & ~_PAGE_CACHE_CTL
) |
513 _PAGE_NO_CACHE
| _PAGE_GUARDED
);
516 #define pgprot_noncached_wc pgprot_noncached_wc
517 static inline pgprot_t
pgprot_noncached_wc(pgprot_t prot
)
519 return __pgprot((pgprot_val(prot
) & ~_PAGE_CACHE_CTL
) |
523 #define pgprot_cached pgprot_cached
524 static inline pgprot_t
pgprot_cached(pgprot_t prot
)
526 return __pgprot((pgprot_val(prot
) & ~_PAGE_CACHE_CTL
) |
530 #define pgprot_cached_wthru pgprot_cached_wthru
531 static inline pgprot_t
pgprot_cached_wthru(pgprot_t prot
)
533 return __pgprot((pgprot_val(prot
) & ~_PAGE_CACHE_CTL
) |
534 _PAGE_COHERENT
| _PAGE_WRITETHRU
);
537 #define pgprot_cached_noncoherent pgprot_cached_noncoherent
538 static inline pgprot_t
pgprot_cached_noncoherent(pgprot_t prot
)
540 return __pgprot(pgprot_val(prot
) & ~_PAGE_CACHE_CTL
);
543 #define pgprot_writecombine pgprot_writecombine
544 static inline pgprot_t
pgprot_writecombine(pgprot_t prot
)
546 return pgprot_noncached_wc(prot
);
549 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
550 extern void hpte_do_hugepage_flush(struct mm_struct
*mm
, unsigned long addr
,
551 pmd_t
*pmdp
, unsigned long old_pmd
);
553 static inline void hpte_do_hugepage_flush(struct mm_struct
*mm
,
554 unsigned long addr
, pmd_t
*pmdp
,
555 unsigned long old_pmd
)
557 WARN(1, "%s called with THP disabled\n", __func__
);
559 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
561 #endif /* !__ASSEMBLY__ */
562 #endif /* __KERNEL__ */
563 #endif /* _ASM_POWERPC_BOOK3S_64_HASH_H */