arch/powerpc/include/asm/book3s/64/mmu.h

   1 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
   2 #define _ASM_POWERPC_BOOK3S_64_MMU_H_
   3
   4 #ifndef __ASSEMBLY__
   5 /*
   6  * Page size definition
   7  *
   8  *    shift : is the "PAGE_SHIFT" value for that page size
   9  *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
  10  *            directly to a slbmte "vsid" value
  11  *    penc  : is the HPTE encoding mask for the "LP" field:
  12  *
  13  */
  14 struct mmu_psize_def {
  15         unsigned int    shift;  /* number of bits */
  16         int             penc[MMU_PAGE_COUNT];   /* HPTE encoding */
  17         unsigned int    tlbiel; /* tlbiel supported for that page size */
  18         unsigned long   avpnm;  /* bits to mask out in AVPN in the HPTE */
  19         unsigned long   sllp;   /* SLB L||LP (exact mask to use in slbmte) */
  20 };
  21 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
  22
  23 #define radix_enabled() (0)
  24 #endif /* __ASSEMBLY__ */
  25
  26 /* 64-bit classic hash table MMU */
  27 #include <asm/book3s/64/mmu-hash.h>
  28
  29 #ifndef __ASSEMBLY__
  30 /*
  31  * ISA 3.0 partiton and process table entry format
  32  */
  33 struct prtb_entry {
  34         __be64 prtb0;
  35         __be64 prtb1;
  36 };
  37 extern struct prtb_entry *process_tb;
  38
  39 struct patb_entry {
  40         __be64 patb0;
  41         __be64 patb1;
  42 };
  43 extern struct patb_entry *partition_tb;
  44
  45 #define PATB_HR         (1UL << 63)
  46 #define PATB_GR         (1UL << 63)
  47 #define RPDB_MASK       0x0ffffffffffff00fUL
  48 #define RPDB_SHIFT      (1UL << 8)
  49 /*
  50  * Limit process table to PAGE_SIZE table. This
  51  * also limit the max pid we can support.
  52  * MAX_USER_CONTEXT * 16 bytes of space.
  53  */
  54 #define PRTB_SIZE_SHIFT (CONTEXT_BITS + 4)
  55 /*
  56  * Power9 currently only support 64K partition table size.
  57  */
  58 #define PATB_SIZE_SHIFT 16
  59
  60 typedef unsigned long mm_context_id_t;
  61 struct spinlock;
  62
  63 typedef struct {
  64         mm_context_id_t id;
  65         u16 user_psize;         /* page size index */
  66
  67 #ifdef CONFIG_PPC_MM_SLICES
  68         u64 low_slices_psize;   /* SLB page size encodings */
  69         unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
  70 #else
  71         u16 sllp;               /* SLB page size encoding */
  72 #endif
  73         unsigned long vdso_base;
  74 #ifdef CONFIG_PPC_SUBPAGE_PROT
  75         struct subpage_prot_table spt;
  76 #endif /* CONFIG_PPC_SUBPAGE_PROT */
  77 #ifdef CONFIG_PPC_ICSWX
  78         struct spinlock *cop_lockp; /* guard acop and cop_pid */
  79         unsigned long acop;     /* mask of enabled coprocessor types */
  80         unsigned int cop_pid;   /* pid value used with coprocessors */
  81 #endif /* CONFIG_PPC_ICSWX */
  82 #ifdef CONFIG_PPC_64K_PAGES
  83         /* for 4K PTE fragment support */
  84         void *pte_frag;
  85 #endif
  86 #ifdef CONFIG_SPAPR_TCE_IOMMU
  87         struct list_head iommu_group_mem_list;
  88 #endif
  89 } mm_context_t;
  90
  91 /*
  92  * The current system page and segment sizes
  93  */
  94 extern int mmu_linear_psize;
  95 extern int mmu_virtual_psize;
  96 extern int mmu_vmalloc_psize;
  97 extern int mmu_vmemmap_psize;
  98 extern int mmu_io_psize;
  99
 100 /* MMU initialization */
 101 extern void hash__early_init_mmu(void);
 102 static inline void early_init_mmu(void)
 103 {
 104         return hash__early_init_mmu();
 105 }
 106 extern void hash__early_init_mmu_secondary(void);
 107 static inline void early_init_mmu_secondary(void)
 108 {
 109         return hash__early_init_mmu_secondary();
 110 }
 111
 112 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 113                                          phys_addr_t first_memblock_size);
 114 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 115                                               phys_addr_t first_memblock_size)
 116 {
 117         return hash__setup_initial_memory_limit(first_memblock_base,
 118                                            first_memblock_size);
 119 }
 120 #endif /* __ASSEMBLY__ */
 121 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */