arch/powerpc/include/asm/book3s/64/mmu.h

   1 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
   2 #define _ASM_POWERPC_BOOK3S_64_MMU_H_
   3
   4 #ifndef __ASSEMBLY__
   5 /*
   6  * Page size definition
   7  *
   8  *    shift : is the "PAGE_SHIFT" value for that page size
   9  *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
  10  *            directly to a slbmte "vsid" value
  11  *    penc  : is the HPTE encoding mask for the "LP" field:
  12  *
  13  */
  14 struct mmu_psize_def {
  15         unsigned int    shift;  /* number of bits */
  16         int             penc[MMU_PAGE_COUNT];   /* HPTE encoding */
  17         unsigned int    tlbiel; /* tlbiel supported for that page size */
  18         unsigned long   avpnm;  /* bits to mask out in AVPN in the HPTE */
  19         union {
  20                 unsigned long   sllp;   /* SLB L||LP (exact mask to use in slbmte) */
  21                 unsigned long ap;       /* Ap encoding used by PowerISA 3.0 */
  22         };
  23 };
  24 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
  25
  26 #endif /* __ASSEMBLY__ */
  27
  28 /* 64-bit classic hash table MMU */
  29 #include <asm/book3s/64/mmu-hash.h>
  30
  31 #ifndef __ASSEMBLY__
  32 /*
  33  * ISA 3.0 partition and process table entry format
  34  */
  35 struct prtb_entry {
  36         __be64 prtb0;
  37         __be64 prtb1;
  38 };
  39 extern struct prtb_entry *process_tb;
  40
  41 struct patb_entry {
  42         __be64 patb0;
  43         __be64 patb1;
  44 };
  45 extern struct patb_entry *partition_tb;
  46
  47 /* Bits in patb0 field */
  48 #define PATB_HR         (1UL << 63)
  49 #define RPDB_MASK       0x0fffffffffffff00UL
  50 #define RPDB_SHIFT      (1UL << 8)
  51 #define RTS1_SHIFT      61              /* top 2 bits of radix tree size */
  52 #define RTS1_MASK       (3UL << RTS1_SHIFT)
  53 #define RTS2_SHIFT      5               /* bottom 3 bits of radix tree size */
  54 #define RTS2_MASK       (7UL << RTS2_SHIFT)
  55 #define RPDS_MASK       0x1f            /* root page dir. size field */
  56
  57 /* Bits in patb1 field */
  58 #define PATB_GR         (1UL << 63)     /* guest uses radix; must match HR */
  59 #define PRTS_MASK       0x1f            /* process table size field */
  60 #define PRTB_MASK       0x0ffffffffffff000UL
  61
  62 /* Number of supported PID bits */
  63 extern unsigned int mmu_pid_bits;
  64
  65 /* Base PID to allocate from */
  66 extern unsigned int mmu_base_pid;
  67
  68 #define PRTB_SIZE_SHIFT (mmu_pid_bits + 4)
  69 #define PRTB_ENTRIES    (1ul << mmu_pid_bits)
  70
  71 /*
  72  * Power9 currently only support 64K partition table size.
  73  */
  74 #define PATB_SIZE_SHIFT 16
  75
  76 typedef unsigned long mm_context_id_t;
  77 struct spinlock;
  78
  79 /* Maximum possible number of NPUs in a system. */
  80 #define NV_MAX_NPUS 8
  81
  82 typedef struct {
  83         mm_context_id_t id;
  84         u16 user_psize;         /* page size index */
  85
  86         /* NPU NMMU context */
  87         struct npu_context *npu_context;
  88
  89 #ifdef CONFIG_PPC_MM_SLICES
  90         u64 low_slices_psize;   /* SLB page size encodings */
  91         unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
  92         unsigned long addr_limit;
  93 #else
  94         u16 sllp;               /* SLB page size encoding */
  95 #endif
  96         unsigned long vdso_base;
  97 #ifdef CONFIG_PPC_SUBPAGE_PROT
  98         struct subpage_prot_table spt;
  99 #endif /* CONFIG_PPC_SUBPAGE_PROT */
 100 #ifdef CONFIG_PPC_ICSWX
 101         struct spinlock *cop_lockp; /* guard acop and cop_pid */
 102         unsigned long acop;     /* mask of enabled coprocessor types */
 103         unsigned int cop_pid;   /* pid value used with coprocessors */
 104 #endif /* CONFIG_PPC_ICSWX */
 105 #ifdef CONFIG_PPC_64K_PAGES
 106         /* for 4K PTE fragment support */
 107         void *pte_frag;
 108 #endif
 109 #ifdef CONFIG_SPAPR_TCE_IOMMU
 110         struct list_head iommu_group_mem_list;
 111 #endif
 112 } mm_context_t;
 113
 114 /*
 115  * The current system page and segment sizes
 116  */
 117 extern int mmu_linear_psize;
 118 extern int mmu_virtual_psize;
 119 extern int mmu_vmalloc_psize;
 120 extern int mmu_vmemmap_psize;
 121 extern int mmu_io_psize;
 122
 123 /* MMU initialization */
 124 void mmu_early_init_devtree(void);
 125 void hash__early_init_devtree(void);
 126 void radix__early_init_devtree(void);
 127 extern void radix_init_native(void);
 128 extern void hash__early_init_mmu(void);
 129 extern void radix__early_init_mmu(void);
 130 static inline void early_init_mmu(void)
 131 {
 132         if (radix_enabled())
 133                 return radix__early_init_mmu();
 134         return hash__early_init_mmu();
 135 }
 136 extern void hash__early_init_mmu_secondary(void);
 137 extern void radix__early_init_mmu_secondary(void);
 138 static inline void early_init_mmu_secondary(void)
 139 {
 140         if (radix_enabled())
 141                 return radix__early_init_mmu_secondary();
 142         return hash__early_init_mmu_secondary();
 143 }
 144
 145 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 146                                          phys_addr_t first_memblock_size);
 147 extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 148                                          phys_addr_t first_memblock_size);
 149 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 150                                               phys_addr_t first_memblock_size)
 151 {
 152         if (early_radix_enabled())
 153                 return radix__setup_initial_memory_limit(first_memblock_base,
 154                                                    first_memblock_size);
 155         return hash__setup_initial_memory_limit(first_memblock_base,
 156                                            first_memblock_size);
 157 }
 158
 159 extern int (*register_process_table)(unsigned long base, unsigned long page_size,
 160                                      unsigned long tbl_size);
 161
 162 #ifdef CONFIG_PPC_PSERIES
 163 extern void radix_init_pseries(void);
 164 #else
 165 static inline void radix_init_pseries(void) { };
 166 #endif
 167
 168 #endif /* __ASSEMBLY__ */
 169 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */