arch/powerpc/include/asm/book3s/64/mmu.h

   1 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
   2 #define _ASM_POWERPC_BOOK3S_64_MMU_H_
   3
   4 #ifndef __ASSEMBLY__
   5 /*
   6  * Page size definition
   7  *
   8  *    shift : is the "PAGE_SHIFT" value for that page size
   9  *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
  10  *            directly to a slbmte "vsid" value
  11  *    penc  : is the HPTE encoding mask for the "LP" field:
  12  *
  13  */
  14 struct mmu_psize_def {
  15         unsigned int    shift;  /* number of bits */
  16         int             penc[MMU_PAGE_COUNT];   /* HPTE encoding */
  17         unsigned int    tlbiel; /* tlbiel supported for that page size */
  18         unsigned long   avpnm;  /* bits to mask out in AVPN in the HPTE */
  19         union {
  20                 unsigned long   sllp;   /* SLB L||LP (exact mask to use in slbmte) */
  21                 unsigned long ap;       /* Ap encoding used by PowerISA 3.0 */
  22         };
  23 };
  24 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
  25
  26 #endif /* __ASSEMBLY__ */
  27
  28 /* 64-bit classic hash table MMU */
  29 #include <asm/book3s/64/mmu-hash.h>
  30
  31 #ifndef __ASSEMBLY__
  32 /*
  33  * ISA 3.0 partition and process table entry format
  34  */
  35 struct prtb_entry {
  36         __be64 prtb0;
  37         __be64 prtb1;
  38 };
  39 extern struct prtb_entry *process_tb;
  40
  41 struct patb_entry {
  42         __be64 patb0;
  43         __be64 patb1;
  44 };
  45 extern struct patb_entry *partition_tb;
  46
  47 /* Bits in patb0 field */
  48 #define PATB_HR         (1UL << 63)
  49 #define RPDB_MASK       0x0fffffffffffff00UL
  50 #define RPDB_SHIFT      (1UL << 8)
  51 #define RTS1_SHIFT      61              /* top 2 bits of radix tree size */
  52 #define RTS1_MASK       (3UL << RTS1_SHIFT)
  53 #define RTS2_SHIFT      5               /* bottom 3 bits of radix tree size */
  54 #define RTS2_MASK       (7UL << RTS2_SHIFT)
  55 #define RPDS_MASK       0x1f            /* root page dir. size field */
  56
  57 /* Bits in patb1 field */
  58 #define PATB_GR         (1UL << 63)     /* guest uses radix; must match HR */
  59 #define PRTS_MASK       0x1f            /* process table size field */
  60 #define PRTB_MASK       0x0ffffffffffff000UL
  61
  62 /*
  63  * Limit process table to PAGE_SIZE table. This
  64  * also limit the max pid we can support.
  65  * MAX_USER_CONTEXT * 16 bytes of space.
  66  */
  67 #define PRTB_SIZE_SHIFT (CONTEXT_BITS + 4)
  68 #define PRTB_ENTRIES    (1ul << CONTEXT_BITS)
  69
  70 /*
  71  * Power9 currently only support 64K partition table size.
  72  */
  73 #define PATB_SIZE_SHIFT 16
  74
  75 typedef unsigned long mm_context_id_t;
  76 struct spinlock;
  77
  78 /* Maximum possible number of NPUs in a system. */
  79 #define NV_MAX_NPUS 8
  80
  81 typedef struct {
  82         mm_context_id_t id;
  83         u16 user_psize;         /* page size index */
  84
  85         /* NPU NMMU context */
  86         struct npu_context *npu_context;
  87
  88 #ifdef CONFIG_PPC_MM_SLICES
  89         u64 low_slices_psize;   /* SLB page size encodings */
  90         unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
  91         unsigned long addr_limit;
  92 #else
  93         u16 sllp;               /* SLB page size encoding */
  94 #endif
  95         unsigned long vdso_base;
  96 #ifdef CONFIG_PPC_SUBPAGE_PROT
  97         struct subpage_prot_table spt;
  98 #endif /* CONFIG_PPC_SUBPAGE_PROT */
  99 #ifdef CONFIG_PPC_ICSWX
 100         struct spinlock *cop_lockp; /* guard acop and cop_pid */
 101         unsigned long acop;     /* mask of enabled coprocessor types */
 102         unsigned int cop_pid;   /* pid value used with coprocessors */
 103 #endif /* CONFIG_PPC_ICSWX */
 104 #ifdef CONFIG_PPC_64K_PAGES
 105         /* for 4K PTE fragment support */
 106         void *pte_frag;
 107 #endif
 108 #ifdef CONFIG_SPAPR_TCE_IOMMU
 109         struct list_head iommu_group_mem_list;
 110 #endif
 111 } mm_context_t;
 112
 113 /*
 114  * The current system page and segment sizes
 115  */
 116 extern int mmu_linear_psize;
 117 extern int mmu_virtual_psize;
 118 extern int mmu_vmalloc_psize;
 119 extern int mmu_vmemmap_psize;
 120 extern int mmu_io_psize;
 121
 122 /* MMU initialization */
 123 void mmu_early_init_devtree(void);
 124 void hash__early_init_devtree(void);
 125 void radix__early_init_devtree(void);
 126 extern void radix_init_native(void);
 127 extern void hash__early_init_mmu(void);
 128 extern void radix__early_init_mmu(void);
 129 static inline void early_init_mmu(void)
 130 {
 131         if (radix_enabled())
 132                 return radix__early_init_mmu();
 133         return hash__early_init_mmu();
 134 }
 135 extern void hash__early_init_mmu_secondary(void);
 136 extern void radix__early_init_mmu_secondary(void);
 137 static inline void early_init_mmu_secondary(void)
 138 {
 139         if (radix_enabled())
 140                 return radix__early_init_mmu_secondary();
 141         return hash__early_init_mmu_secondary();
 142 }
 143
 144 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 145                                          phys_addr_t first_memblock_size);
 146 extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 147                                          phys_addr_t first_memblock_size);
 148 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 149                                               phys_addr_t first_memblock_size)
 150 {
 151         if (early_radix_enabled())
 152                 return radix__setup_initial_memory_limit(first_memblock_base,
 153                                                    first_memblock_size);
 154         return hash__setup_initial_memory_limit(first_memblock_base,
 155                                            first_memblock_size);
 156 }
 157
 158 extern int (*register_process_table)(unsigned long base, unsigned long page_size,
 159                                      unsigned long tbl_size);
 160
 161 #ifdef CONFIG_PPC_PSERIES
 162 extern void radix_init_pseries(void);
 163 #else
 164 static inline void radix_init_pseries(void) { };
 165 #endif
 166
 167 #endif /* __ASSEMBLY__ */
 168 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */