arch/powerpc/include/asm/book3s/64/mmu.h

   1 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
   2 #define _ASM_POWERPC_BOOK3S_64_MMU_H_
   3
   4 #ifndef __ASSEMBLY__
   5 /*
   6  * Page size definition
   7  *
   8  *    shift : is the "PAGE_SHIFT" value for that page size
   9  *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
  10  *            directly to a slbmte "vsid" value
  11  *    penc  : is the HPTE encoding mask for the "LP" field:
  12  *
  13  */
  14 struct mmu_psize_def {
  15         unsigned int    shift;  /* number of bits */
  16         int             penc[MMU_PAGE_COUNT];   /* HPTE encoding */
  17         unsigned int    tlbiel; /* tlbiel supported for that page size */
  18         unsigned long   avpnm;  /* bits to mask out in AVPN in the HPTE */
  19         union {
  20                 unsigned long   sllp;   /* SLB L||LP (exact mask to use in slbmte) */
  21                 unsigned long ap;       /* Ap encoding used by PowerISA 3.0 */
  22         };
  23 };
  24 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
  25
  26 #endif /* __ASSEMBLY__ */
  27
  28 /* 64-bit classic hash table MMU */
  29 #include <asm/book3s/64/mmu-hash.h>
  30
  31 #ifndef __ASSEMBLY__
  32 /*
  33  * ISA 3.0 partition and process table entry format
  34  */
  35 struct prtb_entry {
  36         __be64 prtb0;
  37         __be64 prtb1;
  38 };
  39 extern struct prtb_entry *process_tb;
  40
  41 struct patb_entry {
  42         __be64 patb0;
  43         __be64 patb1;
  44 };
  45 extern struct patb_entry *partition_tb;
  46
  47 /* Bits in patb0 field */
  48 #define PATB_HR         (1UL << 63)
  49 #define RPDB_MASK       0x0fffffffffffff00UL
  50 #define RPDB_SHIFT      (1UL << 8)
  51 #define RTS1_SHIFT      61              /* top 2 bits of radix tree size */
  52 #define RTS1_MASK       (3UL << RTS1_SHIFT)
  53 #define RTS2_SHIFT      5               /* bottom 3 bits of radix tree size */
  54 #define RTS2_MASK       (7UL << RTS2_SHIFT)
  55 #define RPDS_MASK       0x1f            /* root page dir. size field */
  56
  57 /* Bits in patb1 field */
  58 #define PATB_GR         (1UL << 63)     /* guest uses radix; must match HR */
  59 #define PRTS_MASK       0x1f            /* process table size field */
  60 #define PRTB_MASK       0x0ffffffffffff000UL
  61
  62 /*
  63  * Limit process table to PAGE_SIZE table. This
  64  * also limit the max pid we can support.
  65  * MAX_USER_CONTEXT * 16 bytes of space.
  66  */
  67 #define PRTB_SIZE_SHIFT (CONTEXT_BITS + 4)
  68 /*
  69  * Power9 currently only support 64K partition table size.
  70  */
  71 #define PATB_SIZE_SHIFT 16
  72
  73 typedef unsigned long mm_context_id_t;
  74 struct spinlock;
  75
  76 typedef struct {
  77         mm_context_id_t id;
  78         u16 user_psize;         /* page size index */
  79
  80 #ifdef CONFIG_PPC_MM_SLICES
  81         u64 low_slices_psize;   /* SLB page size encodings */
  82         unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
  83 #else
  84         u16 sllp;               /* SLB page size encoding */
  85 #endif
  86         unsigned long vdso_base;
  87 #ifdef CONFIG_PPC_SUBPAGE_PROT
  88         struct subpage_prot_table spt;
  89 #endif /* CONFIG_PPC_SUBPAGE_PROT */
  90 #ifdef CONFIG_PPC_ICSWX
  91         struct spinlock *cop_lockp; /* guard acop and cop_pid */
  92         unsigned long acop;     /* mask of enabled coprocessor types */
  93         unsigned int cop_pid;   /* pid value used with coprocessors */
  94 #endif /* CONFIG_PPC_ICSWX */
  95 #ifdef CONFIG_PPC_64K_PAGES
  96         /* for 4K PTE fragment support */
  97         void *pte_frag;
  98 #endif
  99 #ifdef CONFIG_SPAPR_TCE_IOMMU
 100         struct list_head iommu_group_mem_list;
 101 #endif
 102 } mm_context_t;
 103
 104 /*
 105  * The current system page and segment sizes
 106  */
 107 extern int mmu_linear_psize;
 108 extern int mmu_virtual_psize;
 109 extern int mmu_vmalloc_psize;
 110 extern int mmu_vmemmap_psize;
 111 extern int mmu_io_psize;
 112
 113 /* MMU initialization */
 114 void mmu_early_init_devtree(void);
 115 void hash__early_init_devtree(void);
 116 void radix__early_init_devtree(void);
 117 extern void radix_init_native(void);
 118 extern void hash__early_init_mmu(void);
 119 extern void radix__early_init_mmu(void);
 120 static inline void early_init_mmu(void)
 121 {
 122         if (radix_enabled())
 123                 return radix__early_init_mmu();
 124         return hash__early_init_mmu();
 125 }
 126 extern void hash__early_init_mmu_secondary(void);
 127 extern void radix__early_init_mmu_secondary(void);
 128 static inline void early_init_mmu_secondary(void)
 129 {
 130         if (radix_enabled())
 131                 return radix__early_init_mmu_secondary();
 132         return hash__early_init_mmu_secondary();
 133 }
 134
 135 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 136                                          phys_addr_t first_memblock_size);
 137 extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 138                                          phys_addr_t first_memblock_size);
 139 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 140                                               phys_addr_t first_memblock_size)
 141 {
 142         if (early_radix_enabled())
 143                 return radix__setup_initial_memory_limit(first_memblock_base,
 144                                                    first_memblock_size);
 145         return hash__setup_initial_memory_limit(first_memblock_base,
 146                                            first_memblock_size);
 147 }
 148
 149 extern int (*register_process_table)(unsigned long base, unsigned long page_size,
 150                                      unsigned long tbl_size);
 151
 152 #ifdef CONFIG_PPC_PSERIES
 153 extern void radix_init_pseries(void);
 154 #else
 155 static inline void radix_init_pseries(void) { };
 156 #endif
 157
 158 #endif /* __ASSEMBLY__ */
 159 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */