arch/powerpc/include/asm/book3s/64/radix.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_POWERPC_PGTABLE_RADIX_H
   3 #define _ASM_POWERPC_PGTABLE_RADIX_H
   4
   5 #ifndef __ASSEMBLY__
   6 #include <asm/cmpxchg.h>
   7 #endif
   8
   9 #ifdef CONFIG_PPC_64K_PAGES
  10 #include <asm/book3s/64/radix-64k.h>
  11 #else
  12 #include <asm/book3s/64/radix-4k.h>
  13 #endif
  14
  15 /*
  16  * For P9 DD1 only, we need to track whether the pte's huge.
  17  */
  18 #define R_PAGE_LARGE    _RPAGE_RSV1
  19
  20
  21 #ifndef __ASSEMBLY__
  22 #include <asm/book3s/64/tlbflush-radix.h>
  23 #include <asm/cpu_has_feature.h>
  24 #endif
  25
  26 /* An empty PTE can still have a R or C writeback */
  27 #define RADIX_PTE_NONE_MASK             (_PAGE_DIRTY | _PAGE_ACCESSED)
  28
  29 /* Bits to set in a RPMD/RPUD/RPGD */
  30 #define RADIX_PMD_VAL_BITS              (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE)
  31 #define RADIX_PUD_VAL_BITS              (0x8000000000000000UL | RADIX_PMD_INDEX_SIZE)
  32 #define RADIX_PGD_VAL_BITS              (0x8000000000000000UL | RADIX_PUD_INDEX_SIZE)
  33
  34 /* Don't have anything in the reserved bits and leaf bits */
  35 #define RADIX_PMD_BAD_BITS              0x60000000000000e0UL
  36 #define RADIX_PUD_BAD_BITS              0x60000000000000e0UL
  37 #define RADIX_PGD_BAD_BITS              0x60000000000000e0UL
  38
  39 /*
  40  * Size of EA range mapped by our pagetables.
  41  */
  42 #define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE + \
  43                               RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT)
  44 #define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE)
  45
  46 /*
  47  * We support 52 bit address space, Use top bit for kernel
  48  * virtual mapping. Also make sure kernel fit in the top
  49  * quadrant.
  50  *
  51  *           +------------------+
  52  *           +------------------+  Kernel virtual map (0xc008000000000000)
  53  *           |                  |
  54  *           |                  |
  55  *           |                  |
  56  * 0b11......+------------------+  Kernel linear map (0xc....)
  57  *           |                  |
  58  *           |     2 quadrant   |
  59  *           |                  |
  60  * 0b10......+------------------+
  61  *           |                  |
  62  *           |    1 quadrant    |
  63  *           |                  |
  64  * 0b01......+------------------+
  65  *           |                  |
  66  *           |    0 quadrant    |
  67  *           |                  |
  68  * 0b00......+------------------+
  69  *
  70  *
  71  * 3rd quadrant expanded:
  72  * +------------------------------+
  73  * |                              |
  74  * |                              |
  75  * |                              |
  76  * +------------------------------+  Kernel IO map end (0xc010000000000000)
  77  * |                              |
  78  * |                              |
  79  * |      1/2 of virtual map      |
  80  * |                              |
  81  * |                              |
  82  * +------------------------------+  Kernel IO map start
  83  * |                              |
  84  * |      1/4 of virtual map      |
  85  * |                              |
  86  * +------------------------------+  Kernel vmemap start
  87  * |                              |
  88  * |     1/4 of virtual map       |
  89  * |                              |
  90  * +------------------------------+  Kernel virt start (0xc008000000000000)
  91  * |                              |
  92  * |                              |
  93  * |                              |
  94  * +------------------------------+  Kernel linear (0xc.....)
  95  */
  96
  97 #define RADIX_KERN_VIRT_START ASM_CONST(0xc008000000000000)
  98 #define RADIX_KERN_VIRT_SIZE  ASM_CONST(0x0008000000000000)
  99
 100 /*
 101  * The vmalloc space starts at the beginning of that region, and
 102  * occupies a quarter of it on radix config.
 103  * (we keep a quarter for the virtual memmap)
 104  */
 105 #define RADIX_VMALLOC_START     RADIX_KERN_VIRT_START
 106 #define RADIX_VMALLOC_SIZE      (RADIX_KERN_VIRT_SIZE >> 2)
 107 #define RADIX_VMALLOC_END       (RADIX_VMALLOC_START + RADIX_VMALLOC_SIZE)
 108 /*
 109  * Defines the address of the vmemap area, in its own region on
 110  * hash table CPUs.
 111  */
 112 #define RADIX_VMEMMAP_BASE              (RADIX_VMALLOC_END)
 113
 114 #define RADIX_KERN_IO_START     (RADIX_KERN_VIRT_START + (RADIX_KERN_VIRT_SIZE >> 1))
 115
 116 #ifndef __ASSEMBLY__
 117 #define RADIX_PTE_TABLE_SIZE    (sizeof(pte_t) << RADIX_PTE_INDEX_SIZE)
 118 #define RADIX_PMD_TABLE_SIZE    (sizeof(pmd_t) << RADIX_PMD_INDEX_SIZE)
 119 #define RADIX_PUD_TABLE_SIZE    (sizeof(pud_t) << RADIX_PUD_INDEX_SIZE)
 120 #define RADIX_PGD_TABLE_SIZE    (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
 121
 122 #ifdef CONFIG_STRICT_KERNEL_RWX
 123 extern void radix__mark_rodata_ro(void);
 124 extern void radix__mark_initmem_nx(void);
 125 #endif
 126
 127 static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr,
 128                                                unsigned long set)
 129 {
 130         pte_t pte;
 131         unsigned long old_pte, new_pte;
 132
 133         do {
 134                 pte = READ_ONCE(*ptep);
 135                 old_pte = pte_val(pte);
 136                 new_pte = (old_pte | set) & ~clr;
 137
 138         } while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
 139
 140         return old_pte;
 141 }
 142
 143
 144 static inline unsigned long radix__pte_update(struct mm_struct *mm,
 145                                         unsigned long addr,
 146                                         pte_t *ptep, unsigned long clr,
 147                                         unsigned long set,
 148                                         int huge)
 149 {
 150         unsigned long old_pte;
 151
 152         if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
 153
 154                 unsigned long new_pte;
 155
 156                 old_pte = __radix_pte_update(ptep, ~0ul, 0);
 157                 /*
 158                  * new value of pte
 159                  */
 160                 new_pte = (old_pte | set) & ~clr;
 161                 radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr);
 162                 if (new_pte)
 163                         __radix_pte_update(ptep, 0, new_pte);
 164         } else
 165                 old_pte = __radix_pte_update(ptep, clr, set);
 166         if (!huge)
 167                 assert_pte_locked(mm, addr);
 168
 169         return old_pte;
 170 }
 171
 172 static inline pte_t radix__ptep_get_and_clear_full(struct mm_struct *mm,
 173                                                    unsigned long addr,
 174                                                    pte_t *ptep, int full)
 175 {
 176         unsigned long old_pte;
 177
 178         if (full) {
 179                 /*
 180                  * If we are trying to clear the pte, we can skip
 181                  * the DD1 pte update sequence and batch the tlb flush. The
 182                  * tlb flush batching is done by mmu gather code. We
 183                  * still keep the cmp_xchg update to make sure we get
 184                  * correct R/C bit which might be updated via Nest MMU.
 185                  */
 186                 old_pte = __radix_pte_update(ptep, ~0ul, 0);
 187         } else
 188                 old_pte = radix__pte_update(mm, addr, ptep, ~0ul, 0, 0);
 189
 190         return __pte(old_pte);
 191 }
 192
 193 /*
 194  * Set the dirty and/or accessed bits atomically in a linux PTE, this
 195  * function doesn't need to invalidate tlb.
 196  */
 197 static inline void radix__ptep_set_access_flags(struct mm_struct *mm,
 198                                                 pte_t *ptep, pte_t entry,
 199                                                 unsigned long address)
 200 {
 201
 202         unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED |
 203                                               _PAGE_RW | _PAGE_EXEC);
 204
 205         if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
 206
 207                 unsigned long old_pte, new_pte;
 208
 209                 old_pte = __radix_pte_update(ptep, ~0, 0);
 210                 /*
 211                  * new value of pte
 212                  */
 213                 new_pte = old_pte | set;
 214                 radix__flush_tlb_pte_p9_dd1(old_pte, mm, address);
 215                 __radix_pte_update(ptep, 0, new_pte);
 216         } else
 217                 __radix_pte_update(ptep, 0, set);
 218         asm volatile("ptesync" : : : "memory");
 219 }
 220
 221 static inline int radix__pte_same(pte_t pte_a, pte_t pte_b)
 222 {
 223         return ((pte_raw(pte_a) ^ pte_raw(pte_b)) == 0);
 224 }
 225
 226 static inline int radix__pte_none(pte_t pte)
 227 {
 228         return (pte_val(pte) & ~RADIX_PTE_NONE_MASK) == 0;
 229 }
 230
 231 static inline void radix__set_pte_at(struct mm_struct *mm, unsigned long addr,
 232                                  pte_t *ptep, pte_t pte, int percpu)
 233 {
 234         *ptep = pte;
 235         asm volatile("ptesync" : : : "memory");
 236 }
 237
 238 static inline int radix__pmd_bad(pmd_t pmd)
 239 {
 240         return !!(pmd_val(pmd) & RADIX_PMD_BAD_BITS);
 241 }
 242
 243 static inline int radix__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
 244 {
 245         return ((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) == 0);
 246 }
 247
 248 static inline int radix__pud_bad(pud_t pud)
 249 {
 250         return !!(pud_val(pud) & RADIX_PUD_BAD_BITS);
 251 }
 252
 253
 254 static inline int radix__pgd_bad(pgd_t pgd)
 255 {
 256         return !!(pgd_val(pgd) & RADIX_PGD_BAD_BITS);
 257 }
 258
 259 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 260
 261 static inline int radix__pmd_trans_huge(pmd_t pmd)
 262 {
 263         return (pmd_val(pmd) & (_PAGE_PTE | _PAGE_DEVMAP)) == _PAGE_PTE;
 264 }
 265
 266 static inline pmd_t radix__pmd_mkhuge(pmd_t pmd)
 267 {
 268         if (cpu_has_feature(CPU_FTR_POWER9_DD1))
 269                 return __pmd(pmd_val(pmd) | _PAGE_PTE | R_PAGE_LARGE);
 270         return __pmd(pmd_val(pmd) | _PAGE_PTE);
 271 }
 272 static inline void radix__pmdp_huge_split_prepare(struct vm_area_struct *vma,
 273                                             unsigned long address, pmd_t *pmdp)
 274 {
 275         /* Nothing to do for radix. */
 276         return;
 277 }
 278
 279 extern unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
 280                                           pmd_t *pmdp, unsigned long clr,
 281                                           unsigned long set);
 282 extern pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma,
 283                                   unsigned long address, pmd_t *pmdp);
 284 extern void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
 285                                         pgtable_t pgtable);
 286 extern pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
 287 extern pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
 288                                       unsigned long addr, pmd_t *pmdp);
 289 extern int radix__has_transparent_hugepage(void);
 290 #endif
 291
 292 extern int __meminit radix__vmemmap_create_mapping(unsigned long start,
 293                                              unsigned long page_size,
 294                                              unsigned long phys);
 295 extern void radix__vmemmap_remove_mapping(unsigned long start,
 296                                     unsigned long page_size);
 297
 298 extern int radix__map_kernel_page(unsigned long ea, unsigned long pa,
 299                                  pgprot_t flags, unsigned int psz);
 300
 301 static inline unsigned long radix__get_tree_size(void)
 302 {
 303         unsigned long rts_field;
 304         /*
 305          * We support 52 bits, hence:
 306          *  DD1    52-28 = 24, 0b11000
 307          *  Others 52-31 = 21, 0b10101
 308          * RTS encoding details
 309          * bits 0 - 3 of rts -> bits 6 - 8 unsigned long
 310          * bits 4 - 5 of rts -> bits 62 - 63 of unsigned long
 311          */
 312         if (cpu_has_feature(CPU_FTR_POWER9_DD1))
 313                 rts_field = (0x3UL << 61);
 314         else {
 315                 rts_field = (0x5UL << 5); /* 6 - 8 bits */
 316                 rts_field |= (0x2UL << 61);
 317         }
 318         return rts_field;
 319 }
 320
 321 #ifdef CONFIG_MEMORY_HOTPLUG
 322 int radix__create_section_mapping(unsigned long start, unsigned long end);
 323 int radix__remove_section_mapping(unsigned long start, unsigned long end);
 324 #endif /* CONFIG_MEMORY_HOTPLUG */
 325 #endif /* __ASSEMBLY__ */
 326 #endif