arch/powerpc/include/asm/book3s/64/radix.h

   1 #ifndef _ASM_POWERPC_PGTABLE_RADIX_H
   2 #define _ASM_POWERPC_PGTABLE_RADIX_H
   3
   4 #ifndef __ASSEMBLY__
   5 #include <asm/cmpxchg.h>
   6 #endif
   7
   8 #ifdef CONFIG_PPC_64K_PAGES
   9 #include <asm/book3s/64/radix-64k.h>
  10 #else
  11 #include <asm/book3s/64/radix-4k.h>
  12 #endif
  13
  14 /*
  15  * For P9 DD1 only, we need to track whether the pte's huge.
  16  */
  17 #define R_PAGE_LARGE    _RPAGE_RSV1
  18
  19
  20 #ifndef __ASSEMBLY__
  21 #include <asm/book3s/64/tlbflush-radix.h>
  22 #include <asm/cpu_has_feature.h>
  23 #endif
  24
  25 /* An empty PTE can still have a R or C writeback */
  26 #define RADIX_PTE_NONE_MASK             (_PAGE_DIRTY | _PAGE_ACCESSED)
  27
  28 /* Bits to set in a RPMD/RPUD/RPGD */
  29 #define RADIX_PMD_VAL_BITS              (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE)
  30 #define RADIX_PUD_VAL_BITS              (0x8000000000000000UL | RADIX_PMD_INDEX_SIZE)
  31 #define RADIX_PGD_VAL_BITS              (0x8000000000000000UL | RADIX_PUD_INDEX_SIZE)
  32
  33 /* Don't have anything in the reserved bits and leaf bits */
  34 #define RADIX_PMD_BAD_BITS              0x60000000000000e0UL
  35 #define RADIX_PUD_BAD_BITS              0x60000000000000e0UL
  36 #define RADIX_PGD_BAD_BITS              0x60000000000000e0UL
  37
  38 /*
  39  * Size of EA range mapped by our pagetables.
  40  */
  41 #define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE + \
  42                               RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT)
  43 #define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE)
  44
  45 /*
  46  * We support 52 bit address space, Use top bit for kernel
  47  * virtual mapping. Also make sure kernel fit in the top
  48  * quadrant.
  49  *
  50  *           +------------------+
  51  *           +------------------+  Kernel virtual map (0xc008000000000000)
  52  *           |                  |
  53  *           |                  |
  54  *           |                  |
  55  * 0b11......+------------------+  Kernel linear map (0xc....)
  56  *           |                  |
  57  *           |     2 quadrant   |
  58  *           |                  |
  59  * 0b10......+------------------+
  60  *           |                  |
  61  *           |    1 quadrant    |
  62  *           |                  |
  63  * 0b01......+------------------+
  64  *           |                  |
  65  *           |    0 quadrant    |
  66  *           |                  |
  67  * 0b00......+------------------+
  68  *
  69  *
  70  * 3rd quadrant expanded:
  71  * +------------------------------+
  72  * |                              |
  73  * |                              |
  74  * |                              |
  75  * +------------------------------+  Kernel IO map end (0xc010000000000000)
  76  * |                              |
  77  * |                              |
  78  * |      1/2 of virtual map      |
  79  * |                              |
  80  * |                              |
  81  * +------------------------------+  Kernel IO map start
  82  * |                              |
  83  * |      1/4 of virtual map      |
  84  * |                              |
  85  * +------------------------------+  Kernel vmemap start
  86  * |                              |
  87  * |     1/4 of virtual map       |
  88  * |                              |
  89  * +------------------------------+  Kernel virt start (0xc008000000000000)
  90  * |                              |
  91  * |                              |
  92  * |                              |
  93  * +------------------------------+  Kernel linear (0xc.....)
  94  */
  95
  96 #define RADIX_KERN_VIRT_START ASM_CONST(0xc008000000000000)
  97 #define RADIX_KERN_VIRT_SIZE  ASM_CONST(0x0008000000000000)
  98
  99 /*
 100  * The vmalloc space starts at the beginning of that region, and
 101  * occupies a quarter of it on radix config.
 102  * (we keep a quarter for the virtual memmap)
 103  */
 104 #define RADIX_VMALLOC_START     RADIX_KERN_VIRT_START
 105 #define RADIX_VMALLOC_SIZE      (RADIX_KERN_VIRT_SIZE >> 2)
 106 #define RADIX_VMALLOC_END       (RADIX_VMALLOC_START + RADIX_VMALLOC_SIZE)
 107 /*
 108  * Defines the address of the vmemap area, in its own region on
 109  * hash table CPUs.
 110  */
 111 #define RADIX_VMEMMAP_BASE              (RADIX_VMALLOC_END)
 112
 113 #ifndef __ASSEMBLY__
 114 #define RADIX_PTE_TABLE_SIZE    (sizeof(pte_t) << RADIX_PTE_INDEX_SIZE)
 115 #define RADIX_PMD_TABLE_SIZE    (sizeof(pmd_t) << RADIX_PMD_INDEX_SIZE)
 116 #define RADIX_PUD_TABLE_SIZE    (sizeof(pud_t) << RADIX_PUD_INDEX_SIZE)
 117 #define RADIX_PGD_TABLE_SIZE    (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
 118
 119 #ifdef CONFIG_STRICT_KERNEL_RWX
 120 extern void radix__mark_rodata_ro(void);
 121 #endif
 122
 123 static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr,
 124                                                unsigned long set)
 125 {
 126         pte_t pte;
 127         unsigned long old_pte, new_pte;
 128
 129         do {
 130                 pte = READ_ONCE(*ptep);
 131                 old_pte = pte_val(pte);
 132                 new_pte = (old_pte | set) & ~clr;
 133
 134         } while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
 135
 136         return old_pte;
 137 }
 138
 139
 140 static inline unsigned long radix__pte_update(struct mm_struct *mm,
 141                                         unsigned long addr,
 142                                         pte_t *ptep, unsigned long clr,
 143                                         unsigned long set,
 144                                         int huge)
 145 {
 146         unsigned long old_pte;
 147
 148         if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
 149
 150                 unsigned long new_pte;
 151
 152                 old_pte = __radix_pte_update(ptep, ~0ul, 0);
 153                 /*
 154                  * new value of pte
 155                  */
 156                 new_pte = (old_pte | set) & ~clr;
 157                 radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr);
 158                 if (new_pte)
 159                         __radix_pte_update(ptep, 0, new_pte);
 160         } else
 161                 old_pte = __radix_pte_update(ptep, clr, set);
 162         if (!huge)
 163                 assert_pte_locked(mm, addr);
 164
 165         return old_pte;
 166 }
 167
 168 static inline pte_t radix__ptep_get_and_clear_full(struct mm_struct *mm,
 169                                                    unsigned long addr,
 170                                                    pte_t *ptep, int full)
 171 {
 172         unsigned long old_pte;
 173
 174         if (full) {
 175                 /*
 176                  * If we are trying to clear the pte, we can skip
 177                  * the DD1 pte update sequence and batch the tlb flush. The
 178                  * tlb flush batching is done by mmu gather code. We
 179                  * still keep the cmp_xchg update to make sure we get
 180                  * correct R/C bit which might be updated via Nest MMU.
 181                  */
 182                 old_pte = __radix_pte_update(ptep, ~0ul, 0);
 183         } else
 184                 old_pte = radix__pte_update(mm, addr, ptep, ~0ul, 0, 0);
 185
 186         return __pte(old_pte);
 187 }
 188
 189 /*
 190  * Set the dirty and/or accessed bits atomically in a linux PTE, this
 191  * function doesn't need to invalidate tlb.
 192  */
 193 static inline void radix__ptep_set_access_flags(struct mm_struct *mm,
 194                                                 pte_t *ptep, pte_t entry,
 195                                                 unsigned long address)
 196 {
 197
 198         unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED |
 199                                               _PAGE_RW | _PAGE_EXEC);
 200
 201         if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
 202
 203                 unsigned long old_pte, new_pte;
 204
 205                 old_pte = __radix_pte_update(ptep, ~0, 0);
 206                 /*
 207                  * new value of pte
 208                  */
 209                 new_pte = old_pte | set;
 210                 radix__flush_tlb_pte_p9_dd1(old_pte, mm, address);
 211                 __radix_pte_update(ptep, 0, new_pte);
 212         } else
 213                 __radix_pte_update(ptep, 0, set);
 214         asm volatile("ptesync" : : : "memory");
 215 }
 216
 217 static inline int radix__pte_same(pte_t pte_a, pte_t pte_b)
 218 {
 219         return ((pte_raw(pte_a) ^ pte_raw(pte_b)) == 0);
 220 }
 221
 222 static inline int radix__pte_none(pte_t pte)
 223 {
 224         return (pte_val(pte) & ~RADIX_PTE_NONE_MASK) == 0;
 225 }
 226
 227 static inline void radix__set_pte_at(struct mm_struct *mm, unsigned long addr,
 228                                  pte_t *ptep, pte_t pte, int percpu)
 229 {
 230         *ptep = pte;
 231         asm volatile("ptesync" : : : "memory");
 232 }
 233
 234 static inline int radix__pmd_bad(pmd_t pmd)
 235 {
 236         return !!(pmd_val(pmd) & RADIX_PMD_BAD_BITS);
 237 }
 238
 239 static inline int radix__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
 240 {
 241         return ((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) == 0);
 242 }
 243
 244 static inline int radix__pud_bad(pud_t pud)
 245 {
 246         return !!(pud_val(pud) & RADIX_PUD_BAD_BITS);
 247 }
 248
 249
 250 static inline int radix__pgd_bad(pgd_t pgd)
 251 {
 252         return !!(pgd_val(pgd) & RADIX_PGD_BAD_BITS);
 253 }
 254
 255 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 256
 257 static inline int radix__pmd_trans_huge(pmd_t pmd)
 258 {
 259         return (pmd_val(pmd) & (_PAGE_PTE | _PAGE_DEVMAP)) == _PAGE_PTE;
 260 }
 261
 262 static inline pmd_t radix__pmd_mkhuge(pmd_t pmd)
 263 {
 264         if (cpu_has_feature(CPU_FTR_POWER9_DD1))
 265                 return __pmd(pmd_val(pmd) | _PAGE_PTE | R_PAGE_LARGE);
 266         return __pmd(pmd_val(pmd) | _PAGE_PTE);
 267 }
 268 static inline void radix__pmdp_huge_split_prepare(struct vm_area_struct *vma,
 269                                             unsigned long address, pmd_t *pmdp)
 270 {
 271         /* Nothing to do for radix. */
 272         return;
 273 }
 274
 275 extern unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
 276                                           pmd_t *pmdp, unsigned long clr,
 277                                           unsigned long set);
 278 extern pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma,
 279                                   unsigned long address, pmd_t *pmdp);
 280 extern void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
 281                                         pgtable_t pgtable);
 282 extern pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
 283 extern pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
 284                                       unsigned long addr, pmd_t *pmdp);
 285 extern int radix__has_transparent_hugepage(void);
 286 #endif
 287
 288 extern int __meminit radix__vmemmap_create_mapping(unsigned long start,
 289                                              unsigned long page_size,
 290                                              unsigned long phys);
 291 extern void radix__vmemmap_remove_mapping(unsigned long start,
 292                                     unsigned long page_size);
 293
 294 extern int radix__map_kernel_page(unsigned long ea, unsigned long pa,
 295                                  pgprot_t flags, unsigned int psz);
 296
 297 static inline unsigned long radix__get_tree_size(void)
 298 {
 299         unsigned long rts_field;
 300         /*
 301          * We support 52 bits, hence:
 302          *  DD1    52-28 = 24, 0b11000
 303          *  Others 52-31 = 21, 0b10101
 304          * RTS encoding details
 305          * bits 0 - 3 of rts -> bits 6 - 8 unsigned long
 306          * bits 4 - 5 of rts -> bits 62 - 63 of unsigned long
 307          */
 308         if (cpu_has_feature(CPU_FTR_POWER9_DD1))
 309                 rts_field = (0x3UL << 61);
 310         else {
 311                 rts_field = (0x5UL << 5); /* 6 - 8 bits */
 312                 rts_field |= (0x2UL << 61);
 313         }
 314         return rts_field;
 315 }
 316
 317 #ifdef CONFIG_MEMORY_HOTPLUG
 318 int radix__create_section_mapping(unsigned long start, unsigned long end);
 319 int radix__remove_section_mapping(unsigned long start, unsigned long end);
 320 #endif /* CONFIG_MEMORY_HOTPLUG */
 321 #endif /* __ASSEMBLY__ */
 322 #endif