1 #ifndef __ASM_POWERPC_CPUTABLE_H
2 #define __ASM_POWERPC_CPUTABLE_H
5 #include <linux/types.h>
6 #include <asm/asm-compat.h>
7 #include <asm/feature-fixups.h>
8 #include <uapi/asm/cputable.h>
12 /* This structure can grow, it's real size is used by head.S code
13 * via the mkdefs mechanism.
17 typedef void (*cpu_setup_t
)(unsigned long offset
, struct cpu_spec
* spec
);
18 typedef void (*cpu_restore_t
)(void);
20 enum powerpc_oprofile_type
{
21 PPC_OPROFILE_INVALID
= 0,
22 PPC_OPROFILE_RS64
= 1,
23 PPC_OPROFILE_POWER4
= 2,
25 PPC_OPROFILE_FSL_EMB
= 4,
26 PPC_OPROFILE_CELL
= 5,
27 PPC_OPROFILE_PA6T
= 6,
30 enum powerpc_pmc_type
{
39 extern int machine_check_generic(struct pt_regs
*regs
);
40 extern int machine_check_4xx(struct pt_regs
*regs
);
41 extern int machine_check_440A(struct pt_regs
*regs
);
42 extern int machine_check_e500mc(struct pt_regs
*regs
);
43 extern int machine_check_e500(struct pt_regs
*regs
);
44 extern int machine_check_e200(struct pt_regs
*regs
);
45 extern int machine_check_47x(struct pt_regs
*regs
);
47 extern void cpu_down_flush_e500v2(void);
48 extern void cpu_down_flush_e500mc(void);
49 extern void cpu_down_flush_e5500(void);
50 extern void cpu_down_flush_e6500(void);
52 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
54 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
55 unsigned int pvr_mask
;
56 unsigned int pvr_value
;
59 unsigned long cpu_features
; /* Kernel features */
60 unsigned int cpu_user_features
; /* Userland features */
61 unsigned int cpu_user_features2
; /* Userland features v2 */
62 unsigned int mmu_features
; /* MMU features */
64 /* cache line sizes */
65 unsigned int icache_bsize
;
66 unsigned int dcache_bsize
;
68 /* flush caches inside the current cpu */
69 void (*cpu_down_flush
)(void);
71 /* number of performance monitor counters */
72 unsigned int num_pmcs
;
73 enum powerpc_pmc_type pmc_type
;
75 /* this is called to initialize various CPU bits like L1 cache,
76 * BHT, SPD, etc... from head.S before branching to identify_machine
78 cpu_setup_t cpu_setup
;
79 /* Used to restore cpu setup on secondary processors and at resume */
80 cpu_restore_t cpu_restore
;
82 /* Used by oprofile userspace to select the right counters */
83 char *oprofile_cpu_type
;
85 /* Processor specific oprofile operations */
86 enum powerpc_oprofile_type oprofile_type
;
88 /* Bit locations inside the mmcra change */
89 unsigned long oprofile_mmcra_sihv
;
90 unsigned long oprofile_mmcra_sipr
;
92 /* Bits to clear during an oprofile exception */
93 unsigned long oprofile_mmcra_clear
;
95 /* Name of processor class, for the ELF AT_PLATFORM entry */
98 /* Processor specific machine check handling. Return negative
99 * if the error is fatal, 1 if it was fully recovered and 0 to
100 * pass up (not CPU originated) */
101 int (*machine_check
)(struct pt_regs
*regs
);
104 * Processor specific early machine check handler which is
105 * called in real mode to handle SLB and TLB errors.
107 long (*machine_check_early
)(struct pt_regs
*regs
);
110 * Processor specific routine to flush tlbs.
112 void (*flush_tlb
)(unsigned int action
);
116 extern struct cpu_spec
*cur_cpu_spec
;
118 extern unsigned int __start___ftr_fixup
, __stop___ftr_fixup
;
120 extern struct cpu_spec
*identify_cpu(unsigned long offset
, unsigned int pvr
);
121 extern void do_feature_fixups(unsigned long value
, void *fixup_start
,
124 extern const char *powerpc_base_platform
;
126 /* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
128 TLB_INVAL_SCOPE_GLOBAL
= 0, /* invalidate all TLBs */
129 TLB_INVAL_SCOPE_LPID
= 1, /* invalidate TLBs for current LPID */
132 #endif /* __ASSEMBLY__ */
134 /* CPU kernel features */
136 /* Retain the 32b definitions all use bottom half of word */
137 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
138 #define CPU_FTR_L2CR ASM_CONST(0x00000002)
139 #define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
140 #define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
141 #define CPU_FTR_TAU ASM_CONST(0x00000010)
142 #define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
143 #define CPU_FTR_USE_TB ASM_CONST(0x00000040)
144 #define CPU_FTR_L2CSR ASM_CONST(0x00000080)
145 #define CPU_FTR_601 ASM_CONST(0x00000100)
146 #define CPU_FTR_DBELL ASM_CONST(0x00000200)
147 #define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
148 #define CPU_FTR_L3CR ASM_CONST(0x00000800)
149 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
150 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
151 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
152 #define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
153 #define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
154 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
155 #define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
156 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
157 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
158 #define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
159 #define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
160 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
161 #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
162 #define CPU_FTR_SPE ASM_CONST(0x02000000)
163 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
164 #define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
165 #define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
166 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
167 #define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
170 * Add the 64-bit processor unique features in the top half of the word;
171 * on 32-bit, make the names available but defined to be 0.
174 #define LONG_ASM_CONST(x) ASM_CONST(x)
176 #define LONG_ASM_CONST(x) 0
179 #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
180 #define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
181 #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
182 #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000)
183 #define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000001000000000)
184 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
185 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
186 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
187 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
188 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
189 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
190 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
191 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
192 #define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
193 #define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
194 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
195 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
196 #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
197 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
198 #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
199 #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
200 #define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
201 #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
202 #define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
203 #define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
204 #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
205 #define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
206 #define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
207 #define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000)
208 #define CPU_FTR_SUBCORE LONG_ASM_CONST(0x2000000000000000)
212 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
214 #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
216 /* We only set the altivec features if the kernel was compiled with altivec
219 #ifdef CONFIG_ALTIVEC
220 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
221 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
223 #define CPU_FTR_ALTIVEC_COMP 0
224 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
227 /* We only set the VSX features if the kernel was compiled with VSX
231 #define CPU_FTR_VSX_COMP CPU_FTR_VSX
232 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
234 #define CPU_FTR_VSX_COMP 0
235 #define PPC_FEATURE_HAS_VSX_COMP 0
238 /* We only set the spe features if the kernel was compiled with spe
242 #define CPU_FTR_SPE_COMP CPU_FTR_SPE
243 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
244 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
245 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
247 #define CPU_FTR_SPE_COMP 0
248 #define PPC_FEATURE_HAS_SPE_COMP 0
249 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
250 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
253 /* We only set the TM feature if the kernel was compiled with TM supprt */
254 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
255 #define CPU_FTR_TM_COMP CPU_FTR_TM
256 #define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
257 #define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
259 #define CPU_FTR_TM_COMP 0
260 #define PPC_FEATURE2_HTM_COMP 0
261 #define PPC_FEATURE2_HTM_NOSC_COMP 0
264 /* We need to mark all pages as being coherent if we're SMP or we have a
265 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
266 * require it for PCI "streaming/prefetch" to work properly.
267 * This is also required by 52xx family.
269 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
270 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
271 || defined(CONFIG_PPC_MPC52xx)
272 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
274 #define CPU_FTR_COMMON 0
277 /* The powersave features NAP & DOZE seems to confuse BDI when
278 debugging. So if a BDI is used, disable theses
280 #ifndef CONFIG_BDI_SWITCH
281 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
282 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
284 #define CPU_FTR_MAYBE_CAN_DOZE 0
285 #define CPU_FTR_MAYBE_CAN_NAP 0
288 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
289 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
290 #define CPU_FTRS_603 (CPU_FTR_COMMON | \
291 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
292 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
293 #define CPU_FTRS_604 (CPU_FTR_COMMON | \
294 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
295 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
296 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
297 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
298 #define CPU_FTRS_740 (CPU_FTR_COMMON | \
299 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
300 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
302 #define CPU_FTRS_750 (CPU_FTR_COMMON | \
303 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
304 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
306 #define CPU_FTRS_750CL (CPU_FTRS_750)
307 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
308 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
309 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
310 #define CPU_FTRS_750GX (CPU_FTRS_750FX)
311 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
312 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
313 CPU_FTR_ALTIVEC_COMP | \
314 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
315 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \
316 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
317 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
318 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
319 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
320 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
321 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
322 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
323 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
325 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
326 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
327 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
328 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
329 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
330 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
331 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
332 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
333 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
334 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
335 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
336 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
337 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
338 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
339 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
340 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
341 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
342 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
343 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
344 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \
346 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
347 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
348 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
349 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
351 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
352 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
353 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
354 CPU_FTR_NEED_PAIRED_STWCX)
355 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \
357 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
358 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
359 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
360 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \
362 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
363 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
364 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
365 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \
367 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
368 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
369 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
370 #define CPU_FTRS_82XX (CPU_FTR_COMMON | \
371 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
372 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
373 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
374 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
375 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
377 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
378 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
379 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
380 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
381 #define CPU_FTRS_8XX (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE)
382 #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
383 #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
384 #define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
386 #define CPU_FTRS_47X (CPU_FTRS_440x6)
387 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
388 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
389 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
390 CPU_FTR_DEBUG_LVL_EXC)
391 #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
392 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
394 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
395 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
396 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
397 #define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
398 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
399 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
401 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
402 * same workaround as CPU_FTR_CELL_TB_BUG.
404 #define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
405 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
406 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
407 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
408 #define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
409 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
410 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
411 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
412 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
413 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
416 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
417 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
418 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
419 CPU_FTR_STCX_CHECKS_ADDRESS)
420 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
421 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
422 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
423 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
424 CPU_FTR_HVMODE | CPU_FTR_DABRX)
425 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
426 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
427 CPU_FTR_MMCRA | CPU_FTR_SMT | \
428 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
429 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
430 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
431 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
432 CPU_FTR_MMCRA | CPU_FTR_SMT | \
433 CPU_FTR_COHERENT_ICACHE | \
434 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
435 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
436 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
438 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
439 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
440 CPU_FTR_MMCRA | CPU_FTR_SMT | \
441 CPU_FTR_COHERENT_ICACHE | \
442 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
443 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
444 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
445 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
446 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
447 #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
448 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
449 CPU_FTR_MMCRA | CPU_FTR_SMT | \
450 CPU_FTR_COHERENT_ICACHE | \
451 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
452 CPU_FTR_DSCR | CPU_FTR_SAO | \
453 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
454 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
455 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
456 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_SUBCORE)
457 #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
458 #define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
459 #define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
460 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
461 CPU_FTR_MMCRA | CPU_FTR_SMT | \
462 CPU_FTR_COHERENT_ICACHE | \
463 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
464 CPU_FTR_DSCR | CPU_FTR_SAO | \
465 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
466 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
467 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
468 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300)
469 #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
470 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
471 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
472 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
473 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
474 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
475 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
476 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
477 #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
480 #ifdef CONFIG_PPC_BOOK3E
481 #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
483 #define CPU_FTRS_POSSIBLE \
484 (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
485 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
486 CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \
487 CPU_FTRS_PA6T | CPU_FTR_VSX | CPU_FTRS_POWER9)
492 #ifdef CONFIG_PPC_BOOK3S_32
493 CPU_FTRS_PPC601
| CPU_FTRS_603
| CPU_FTRS_604
| CPU_FTRS_740_NOTAU
|
494 CPU_FTRS_740
| CPU_FTRS_750
| CPU_FTRS_750FX1
|
495 CPU_FTRS_750FX2
| CPU_FTRS_750FX
| CPU_FTRS_750GX
|
496 CPU_FTRS_7400_NOTAU
| CPU_FTRS_7400
| CPU_FTRS_7450_20
|
497 CPU_FTRS_7450_21
| CPU_FTRS_7450_23
| CPU_FTRS_7455_1
|
498 CPU_FTRS_7455_20
| CPU_FTRS_7455
| CPU_FTRS_7447_10
|
499 CPU_FTRS_7447
| CPU_FTRS_7447A
| CPU_FTRS_82XX
|
500 CPU_FTRS_G2_LE
| CPU_FTRS_E300
| CPU_FTRS_E300C2
|
503 CPU_FTRS_GENERIC_32
|
512 CPU_FTRS_44X
| CPU_FTRS_440x6
|
514 #ifdef CONFIG_PPC_47x
515 CPU_FTRS_47X
| CPU_FTR_476_DD2
|
521 CPU_FTRS_E500
| CPU_FTRS_E500_2
|
523 #ifdef CONFIG_PPC_E500MC
524 CPU_FTRS_E500MC
| CPU_FTRS_E5500
| CPU_FTRS_E6500
|
528 #endif /* __powerpc64__ */
531 #ifdef CONFIG_PPC_BOOK3E
532 #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
534 #define CPU_FTRS_ALWAYS \
535 (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
536 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
537 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
538 CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \
544 #ifdef CONFIG_PPC_BOOK3S_32
545 CPU_FTRS_PPC601
& CPU_FTRS_603
& CPU_FTRS_604
& CPU_FTRS_740_NOTAU
&
546 CPU_FTRS_740
& CPU_FTRS_750
& CPU_FTRS_750FX1
&
547 CPU_FTRS_750FX2
& CPU_FTRS_750FX
& CPU_FTRS_750GX
&
548 CPU_FTRS_7400_NOTAU
& CPU_FTRS_7400
& CPU_FTRS_7450_20
&
549 CPU_FTRS_7450_21
& CPU_FTRS_7450_23
& CPU_FTRS_7455_1
&
550 CPU_FTRS_7455_20
& CPU_FTRS_7455
& CPU_FTRS_7447_10
&
551 CPU_FTRS_7447
& CPU_FTRS_7447A
& CPU_FTRS_82XX
&
552 CPU_FTRS_G2_LE
& CPU_FTRS_E300
& CPU_FTRS_E300C2
&
555 CPU_FTRS_GENERIC_32
&
564 CPU_FTRS_44X
& CPU_FTRS_440x6
&
570 CPU_FTRS_E500
& CPU_FTRS_E500_2
&
572 #ifdef CONFIG_PPC_E500MC
573 CPU_FTRS_E500MC
& CPU_FTRS_E5500
& CPU_FTRS_E6500
&
575 ~CPU_FTR_EMB_HV
& /* can be removed at runtime */
578 #endif /* __powerpc64__ */
582 #endif /* !__ASSEMBLY__ */
584 #endif /* __ASM_POWERPC_CPUTABLE_H */