arch/powerpc/include/asm/exception-64e.h

   1 /*
   2  *  Definitions for use by exception code on Book3-E
   3  *
   4  *  Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  */
  11 #ifndef _ASM_POWERPC_EXCEPTION_64E_H
  12 #define _ASM_POWERPC_EXCEPTION_64E_H
  13
  14 /*
  15  * SPRGs usage an other considerations...
  16  *
  17  * Since TLB miss and other standard exceptions can be interrupted by
  18  * critical exceptions which can themselves be interrupted by machine
  19  * checks, and since the two later can themselves cause a TLB miss when
  20  * hitting the linear mapping for the kernel stacks, we need to be a bit
  21  * creative on how we use SPRGs.
  22  *
  23  * The base idea is that we have one SRPG reserved for critical and one
  24  * for machine check interrupts. Those are used to save a GPR that can
  25  * then be used to get the PACA, and store as much context as we need
  26  * to save in there. That includes saving the SPRGs used by the TLB miss
  27  * handler for linear mapping misses and the associated SRR0/1 due to
  28  * the above re-entrancy issue.
  29  *
  30  * So here's the current usage pattern. It's done regardless of which
  31  * SPRGs are user-readable though, thus we might have to change some of
  32  * this later. In order to do that more easily, we use special constants
  33  * for naming them
  34  *
  35  * WARNING: Some of these SPRGs are user readable. We need to do something
  36  * about it as some point by making sure they can't be used to leak kernel
  37  * critical data
  38  */
  39
  40 #define PACA_EXGDBELL PACA_EXGEN
  41
  42 /* We are out of SPRGs so we save some things in the PACA. The normal
  43  * exception frame is smaller than the CRIT or MC one though
  44  */
  45 #define EX_R1           (0 * 8)
  46 #define EX_CR           (1 * 8)
  47 #define EX_R10          (2 * 8)
  48 #define EX_R11          (3 * 8)
  49 #define EX_R14          (4 * 8)
  50 #define EX_R15          (5 * 8)
  51
  52 /*
  53  * The TLB miss exception uses different slots.
  54  *
  55  * The bolted variant uses only the first six fields,
  56  * which in combination with pgd and kernel_pgd fits in
  57  * one 64-byte cache line.
  58  */
  59
  60 #define EX_TLB_R10      ( 0 * 8)
  61 #define EX_TLB_R11      ( 1 * 8)
  62 #define EX_TLB_R14      ( 2 * 8)
  63 #define EX_TLB_R15      ( 3 * 8)
  64 #define EX_TLB_R16      ( 4 * 8)
  65 #define EX_TLB_CR       ( 5 * 8)
  66 #define EX_TLB_R12      ( 6 * 8)
  67 #define EX_TLB_R13      ( 7 * 8)
  68 #define EX_TLB_DEAR     ( 8 * 8) /* Level 0 and 2 only */
  69 #define EX_TLB_ESR      ( 9 * 8) /* Level 0 and 2 only */
  70 #define EX_TLB_SRR0     (10 * 8)
  71 #define EX_TLB_SRR1     (11 * 8)
  72 #ifdef CONFIG_BOOK3E_MMU_TLB_STATS
  73 #define EX_TLB_R8       (12 * 8)
  74 #define EX_TLB_R9       (13 * 8)
  75 #define EX_TLB_LR       (14 * 8)
  76 #define EX_TLB_SIZE     (15 * 8)
  77 #else
  78 #define EX_TLB_SIZE     (12 * 8)
  79 #endif
  80
  81 #define START_EXCEPTION(label)                                          \
  82         .globl exc_##label##_book3e;                                    \
  83 exc_##label##_book3e:
  84
  85 /* TLB miss exception prolog
  86  *
  87  * This prolog handles re-entrancy (up to 3 levels supported in the PACA
  88  * though we currently don't test for overflow). It provides you with a
  89  * re-entrancy safe working space of r10...r16 and CR with r12 being used
  90  * as the exception area pointer in the PACA for that level of re-entrancy
  91  * and r13 containing the PACA pointer.
  92  *
  93  * SRR0 and SRR1 are saved, but DEAR and ESR are not, since they don't apply
  94  * as-is for instruction exceptions. It's up to the actual exception code
  95  * to save them as well if required.
  96  */
  97 #define TLB_MISS_PROLOG                                                     \
  98         mtspr   SPRN_SPRG_TLB_SCRATCH,r12;                                  \
  99         mfspr   r12,SPRN_SPRG_TLB_EXFRAME;                                  \
 100         std     r10,EX_TLB_R10(r12);                                        \
 101         mfcr    r10;                                                        \
 102         std     r11,EX_TLB_R11(r12);                                        \
 103         mfspr   r11,SPRN_SPRG_TLB_SCRATCH;                                  \
 104         std     r13,EX_TLB_R13(r12);                                        \
 105         mfspr   r13,SPRN_SPRG_PACA;                                         \
 106         std     r14,EX_TLB_R14(r12);                                        \
 107         addi    r14,r12,EX_TLB_SIZE;                                        \
 108         std     r15,EX_TLB_R15(r12);                                        \
 109         mfspr   r15,SPRN_SRR1;                                              \
 110         std     r16,EX_TLB_R16(r12);                                        \
 111         mfspr   r16,SPRN_SRR0;                                              \
 112         std     r10,EX_TLB_CR(r12);                                         \
 113         std     r11,EX_TLB_R12(r12);                                        \
 114         mtspr   SPRN_SPRG_TLB_EXFRAME,r14;                                  \
 115         std     r15,EX_TLB_SRR1(r12);                                       \
 116         std     r16,EX_TLB_SRR0(r12);                                       \
 117         TLB_MISS_PROLOG_STATS
 118
 119 /* And these are the matching epilogs that restores things
 120  *
 121  * There are 3 epilogs:
 122  *
 123  * - SUCCESS       : Unwinds one level
 124  * - ERROR         : restore from level 0 and reset
 125  * - ERROR_SPECIAL : restore from current level and reset
 126  *
 127  * Normal errors use ERROR, that is, they restore the initial fault context
 128  * and trigger a fault. However, there is a special case for linear mapping
 129  * errors. Those should basically never happen, but if they do happen, we
 130  * want the error to point out the context that did that linear mapping
 131  * fault, not the initial level 0 (basically, we got a bogus PGF or something
 132  * like that). For userland errors on the linear mapping, there is no
 133  * difference since those are always level 0 anyway
 134  */
 135
 136 #define TLB_MISS_RESTORE(freg)                                              \
 137         ld      r14,EX_TLB_CR(r12);                                         \
 138         ld      r10,EX_TLB_R10(r12);                                        \
 139         ld      r15,EX_TLB_SRR0(r12);                                       \
 140         ld      r16,EX_TLB_SRR1(r12);                                       \
 141         mtspr   SPRN_SPRG_TLB_EXFRAME,freg;                                 \
 142         ld      r11,EX_TLB_R11(r12);                                        \
 143         mtcr    r14;                                                        \
 144         ld      r13,EX_TLB_R13(r12);                                        \
 145         ld      r14,EX_TLB_R14(r12);                                        \
 146         mtspr   SPRN_SRR0,r15;                                              \
 147         ld      r15,EX_TLB_R15(r12);                                        \
 148         mtspr   SPRN_SRR1,r16;                                              \
 149         TLB_MISS_RESTORE_STATS                                              \
 150         ld      r16,EX_TLB_R16(r12);                                        \
 151         ld      r12,EX_TLB_R12(r12);                                        \
 152
 153 #define TLB_MISS_EPILOG_SUCCESS                                             \
 154         TLB_MISS_RESTORE(r12)
 155
 156 #define TLB_MISS_EPILOG_ERROR                                               \
 157         addi    r12,r13,PACA_EXTLB;                                         \
 158         TLB_MISS_RESTORE(r12)
 159
 160 #define TLB_MISS_EPILOG_ERROR_SPECIAL                                       \
 161         addi    r11,r13,PACA_EXTLB;                                         \
 162         TLB_MISS_RESTORE(r11)
 163
 164 #ifdef CONFIG_BOOK3E_MMU_TLB_STATS
 165 #define TLB_MISS_PROLOG_STATS                                               \
 166         mflr    r10;                                                        \
 167         std     r8,EX_TLB_R8(r12);                                          \
 168         std     r9,EX_TLB_R9(r12);                                          \
 169         std     r10,EX_TLB_LR(r12);
 170 #define TLB_MISS_RESTORE_STATS                                              \
 171         ld      r16,EX_TLB_LR(r12);                                         \
 172         ld      r9,EX_TLB_R9(r12);                                          \
 173         ld      r8,EX_TLB_R8(r12);                                          \
 174         mtlr    r16;
 175 #define TLB_MISS_STATS_D(name)                                              \
 176         addi    r9,r13,MMSTAT_DSTATS+name;                                  \
 177         bl      tlb_stat_inc;
 178 #define TLB_MISS_STATS_I(name)                                              \
 179         addi    r9,r13,MMSTAT_ISTATS+name;                                  \
 180         bl      tlb_stat_inc;
 181 #define TLB_MISS_STATS_X(name)                                              \
 182         ld      r8,PACA_EXTLB+EX_TLB_ESR(r13);                              \
 183         cmpdi   cr2,r8,-1;                                                  \
 184         beq     cr2,61f;                                                    \
 185         addi    r9,r13,MMSTAT_DSTATS+name;                                  \
 186         b       62f;                                                        \
 187 61:     addi    r9,r13,MMSTAT_ISTATS+name;                                  \
 188 62:     bl      tlb_stat_inc;
 189 #define TLB_MISS_STATS_SAVE_INFO                                            \
 190         std     r14,EX_TLB_ESR(r12);    /* save ESR */
 191 #define TLB_MISS_STATS_SAVE_INFO_BOLTED                                     \
 192         std     r14,PACA_EXTLB+EX_TLB_ESR(r13); /* save ESR */
 193 #else
 194 #define TLB_MISS_PROLOG_STATS
 195 #define TLB_MISS_RESTORE_STATS
 196 #define TLB_MISS_PROLOG_STATS_BOLTED
 197 #define TLB_MISS_RESTORE_STATS_BOLTED
 198 #define TLB_MISS_STATS_D(name)
 199 #define TLB_MISS_STATS_I(name)
 200 #define TLB_MISS_STATS_X(name)
 201 #define TLB_MISS_STATS_Y(name)
 202 #define TLB_MISS_STATS_SAVE_INFO
 203 #define TLB_MISS_STATS_SAVE_INFO_BOLTED
 204 #endif
 205
 206 #define SET_IVOR(vector_number, vector_offset)  \
 207         LOAD_REG_ADDR(r3,interrupt_base_book3e);\
 208         ori     r3,r3,vector_offset@l;          \
 209         mtspr   SPRN_IVOR##vector_number,r3;
 210
 211 #endif /* _ASM_POWERPC_EXCEPTION_64E_H */
 212