1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef _ASM_POWERPC_IO_H
3 #define _ASM_POWERPC_IO_H
6 #define ARCH_HAS_IOREMAP_WC
8 #define ARCH_HAS_IOREMAP_WT
14 /* Check of existence of legacy devices */
15 extern int check_legacy_ioport(unsigned long base_port
);
16 #define I8042_DATA_REG 0x60
17 #define FDC_BASE 0x3f0
19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
20 extern struct pci_dev
*isa_bridge_pcidev
;
22 * has legacy ISA devices ?
24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
27 #include <linux/device.h>
28 #include <linux/compiler.h>
31 #include <asm/byteorder.h>
32 #include <asm/synch.h>
33 #include <asm/delay.h>
34 #include <asm/mmiowb.h>
36 #include <asm/ppc_asm.h>
37 #include <asm/pgtable.h>
39 #define SIO_CONFIG_RA 0x398
40 #define SIO_CONFIG_RD 0x399
44 /* 32 bits uses slightly different variables for the various IO
45 * bases. Most of this file only uses _IO_BASE though which we
46 * define properly based on the platform
50 #define _ISA_MEM_BASE 0
51 #define PCI_DRAM_OFFSET 0
52 #elif defined(CONFIG_PPC32)
53 #define _IO_BASE isa_io_base
54 #define _ISA_MEM_BASE isa_mem_base
55 #define PCI_DRAM_OFFSET pci_dram_offset
57 #define _IO_BASE pci_io_base
58 #define _ISA_MEM_BASE isa_mem_base
59 #define PCI_DRAM_OFFSET 0
62 extern unsigned long isa_io_base
;
63 extern unsigned long pci_io_base
;
64 extern unsigned long pci_dram_offset
;
66 extern resource_size_t isa_mem_base
;
68 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
69 * is not set or addresses cannot be translated to MMIO. This is typically
70 * set when the platform supports "special" PIO accesses via a non memory
71 * mapped mechanism, and allows things like the early udbg UART code to
74 extern bool isa_io_special
;
77 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
78 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
84 * Low level MMIO accessors
86 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
87 * specific and thus shouldn't be used in generic code. The accessors
90 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
91 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
92 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
94 * Those operate directly on a kernel virtual address. Note that the prototype
95 * for the out_* accessors has the arguments in opposite order from the usual
96 * linux PCI accessors. Unlike those, they take the address first and the value
99 * Note: I might drop the _ns suffix on the stream operations soon as it is
100 * simply normal for stream operations to not swap in the first place.
104 #define DEF_MMIO_IN_X(name, size, insn) \
105 static inline u##size name(const volatile u##size __iomem *addr) \
108 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
109 : "=r" (ret) : "Z" (*addr) : "memory"); \
113 #define DEF_MMIO_OUT_X(name, size, insn) \
114 static inline void name(volatile u##size __iomem *addr, u##size val) \
116 __asm__ __volatile__("sync;"#insn" %1,%y0" \
117 : "=Z" (*addr) : "r" (val) : "memory"); \
118 mmiowb_set_pending(); \
121 #define DEF_MMIO_IN_D(name, size, insn) \
122 static inline u##size name(const volatile u##size __iomem *addr) \
125 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
126 : "=r" (ret) : "m" (*addr) : "memory"); \
130 #define DEF_MMIO_OUT_D(name, size, insn) \
131 static inline void name(volatile u##size __iomem *addr, u##size val) \
133 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
134 : "=m" (*addr) : "r" (val) : "memory"); \
135 mmiowb_set_pending(); \
138 DEF_MMIO_IN_D(in_8
, 8, lbz
);
139 DEF_MMIO_OUT_D(out_8
, 8, stb
);
141 #ifdef __BIG_ENDIAN__
142 DEF_MMIO_IN_D(in_be16
, 16, lhz
);
143 DEF_MMIO_IN_D(in_be32
, 32, lwz
);
144 DEF_MMIO_IN_X(in_le16
, 16, lhbrx
);
145 DEF_MMIO_IN_X(in_le32
, 32, lwbrx
);
147 DEF_MMIO_OUT_D(out_be16
, 16, sth
);
148 DEF_MMIO_OUT_D(out_be32
, 32, stw
);
149 DEF_MMIO_OUT_X(out_le16
, 16, sthbrx
);
150 DEF_MMIO_OUT_X(out_le32
, 32, stwbrx
);
152 DEF_MMIO_IN_X(in_be16
, 16, lhbrx
);
153 DEF_MMIO_IN_X(in_be32
, 32, lwbrx
);
154 DEF_MMIO_IN_D(in_le16
, 16, lhz
);
155 DEF_MMIO_IN_D(in_le32
, 32, lwz
);
157 DEF_MMIO_OUT_X(out_be16
, 16, sthbrx
);
158 DEF_MMIO_OUT_X(out_be32
, 32, stwbrx
);
159 DEF_MMIO_OUT_D(out_le16
, 16, sth
);
160 DEF_MMIO_OUT_D(out_le32
, 32, stw
);
162 #endif /* __BIG_ENDIAN */
166 #ifdef __BIG_ENDIAN__
167 DEF_MMIO_OUT_D(out_be64
, 64, std
);
168 DEF_MMIO_IN_D(in_be64
, 64, ld
);
170 /* There is no asm instructions for 64 bits reverse loads and stores */
171 static inline u64
in_le64(const volatile u64 __iomem
*addr
)
173 return swab64(in_be64(addr
));
176 static inline void out_le64(volatile u64 __iomem
*addr
, u64 val
)
178 out_be64(addr
, swab64(val
));
181 DEF_MMIO_OUT_D(out_le64
, 64, std
);
182 DEF_MMIO_IN_D(in_le64
, 64, ld
);
184 /* There is no asm instructions for 64 bits reverse loads and stores */
185 static inline u64
in_be64(const volatile u64 __iomem
*addr
)
187 return swab64(in_le64(addr
));
190 static inline void out_be64(volatile u64 __iomem
*addr
, u64 val
)
192 out_le64(addr
, swab64(val
));
196 #endif /* __powerpc64__ */
199 * Low level IO stream instructions are defined out of line for now
201 extern void _insb(const volatile u8 __iomem
*addr
, void *buf
, long count
);
202 extern void _outsb(volatile u8 __iomem
*addr
,const void *buf
,long count
);
203 extern void _insw_ns(const volatile u16 __iomem
*addr
, void *buf
, long count
);
204 extern void _outsw_ns(volatile u16 __iomem
*addr
, const void *buf
, long count
);
205 extern void _insl_ns(const volatile u32 __iomem
*addr
, void *buf
, long count
);
206 extern void _outsl_ns(volatile u32 __iomem
*addr
, const void *buf
, long count
);
208 /* The _ns naming is historical and will be removed. For now, just #define
209 * the non _ns equivalent names
211 #define _insw _insw_ns
212 #define _insl _insl_ns
213 #define _outsw _outsw_ns
214 #define _outsl _outsl_ns
218 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
221 extern void _memset_io(volatile void __iomem
*addr
, int c
, unsigned long n
);
222 extern void _memcpy_fromio(void *dest
, const volatile void __iomem
*src
,
224 extern void _memcpy_toio(volatile void __iomem
*dest
, const void *src
,
229 * PCI and standard ISA accessors
231 * Those are globally defined linux accessors for devices on PCI or ISA
232 * busses. They follow the Linux defined semantics. The current implementation
233 * for PowerPC is as close as possible to the x86 version of these, and thus
234 * provides fairly heavy weight barriers for the non-raw versions
236 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
237 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
238 * own implementation of some or all of the accessors.
242 * Include the EEH definitions when EEH is enabled only so they don't get
243 * in the way when building for 32 bits
249 /* Shortcut to the MMIO argument pointer */
250 #define PCI_IO_ADDR volatile void __iomem *
252 /* Indirect IO address tokens:
254 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
255 * on all MMIOs. (Note that this is all 64 bits only for now)
257 * To help platforms who may need to differentiate MMIO addresses in
258 * their hooks, a bitfield is reserved for use by the platform near the
259 * top of MMIO addresses (not PIO, those have to cope the hard way).
261 * The highest address in the kernel virtual space are:
263 * d0003fffffffffff # with Hash MMU
264 * c00fffffffffffff # with Radix MMU
266 * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits
267 * that can be used for the field.
269 * The direct IO mapping operations will then mask off those bits
270 * before doing the actual access, though that only happen when
271 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
274 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
275 * all PIO functions call through a hook.
278 #ifdef CONFIG_PPC_INDIRECT_MMIO
279 #define PCI_IO_IND_TOKEN_SHIFT 52
280 #define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT)
281 #define PCI_FIX_ADDR(addr) \
282 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
283 #define PCI_GET_ADDR_TOKEN(addr) \
284 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
285 PCI_IO_IND_TOKEN_SHIFT)
286 #define PCI_SET_ADDR_TOKEN(addr, token) \
288 unsigned long __a = (unsigned long)(addr); \
289 __a &= ~PCI_IO_IND_TOKEN_MASK; \
290 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
291 (addr) = (void __iomem *)__a; \
294 #define PCI_FIX_ADDR(addr) (addr)
299 * Non ordered and non-swapping "raw" accessors
302 static inline unsigned char __raw_readb(const volatile void __iomem
*addr
)
304 return *(volatile unsigned char __force
*)PCI_FIX_ADDR(addr
);
306 static inline unsigned short __raw_readw(const volatile void __iomem
*addr
)
308 return *(volatile unsigned short __force
*)PCI_FIX_ADDR(addr
);
310 static inline unsigned int __raw_readl(const volatile void __iomem
*addr
)
312 return *(volatile unsigned int __force
*)PCI_FIX_ADDR(addr
);
314 static inline void __raw_writeb(unsigned char v
, volatile void __iomem
*addr
)
316 *(volatile unsigned char __force
*)PCI_FIX_ADDR(addr
) = v
;
318 static inline void __raw_writew(unsigned short v
, volatile void __iomem
*addr
)
320 *(volatile unsigned short __force
*)PCI_FIX_ADDR(addr
) = v
;
322 static inline void __raw_writel(unsigned int v
, volatile void __iomem
*addr
)
324 *(volatile unsigned int __force
*)PCI_FIX_ADDR(addr
) = v
;
328 static inline unsigned long __raw_readq(const volatile void __iomem
*addr
)
330 return *(volatile unsigned long __force
*)PCI_FIX_ADDR(addr
);
332 static inline void __raw_writeq(unsigned long v
, volatile void __iomem
*addr
)
334 *(volatile unsigned long __force
*)PCI_FIX_ADDR(addr
) = v
;
337 static inline void __raw_writeq_be(unsigned long v
, volatile void __iomem
*addr
)
339 __raw_writeq((__force
unsigned long)cpu_to_be64(v
), addr
);
343 * Real mode versions of the above. Those instructions are only supposed
344 * to be used in hypervisor real mode as per the architecture spec.
346 static inline void __raw_rm_writeb(u8 val
, volatile void __iomem
*paddr
)
348 __asm__
__volatile__("stbcix %0,0,%1"
349 : : "r" (val
), "r" (paddr
) : "memory");
352 static inline void __raw_rm_writew(u16 val
, volatile void __iomem
*paddr
)
354 __asm__
__volatile__("sthcix %0,0,%1"
355 : : "r" (val
), "r" (paddr
) : "memory");
358 static inline void __raw_rm_writel(u32 val
, volatile void __iomem
*paddr
)
360 __asm__
__volatile__("stwcix %0,0,%1"
361 : : "r" (val
), "r" (paddr
) : "memory");
364 static inline void __raw_rm_writeq(u64 val
, volatile void __iomem
*paddr
)
366 __asm__
__volatile__("stdcix %0,0,%1"
367 : : "r" (val
), "r" (paddr
) : "memory");
370 static inline void __raw_rm_writeq_be(u64 val
, volatile void __iomem
*paddr
)
372 __raw_rm_writeq((__force u64
)cpu_to_be64(val
), paddr
);
375 static inline u8
__raw_rm_readb(volatile void __iomem
*paddr
)
378 __asm__
__volatile__("lbzcix %0,0, %1"
379 : "=r" (ret
) : "r" (paddr
) : "memory");
383 static inline u16
__raw_rm_readw(volatile void __iomem
*paddr
)
386 __asm__
__volatile__("lhzcix %0,0, %1"
387 : "=r" (ret
) : "r" (paddr
) : "memory");
391 static inline u32
__raw_rm_readl(volatile void __iomem
*paddr
)
394 __asm__
__volatile__("lwzcix %0,0, %1"
395 : "=r" (ret
) : "r" (paddr
) : "memory");
399 static inline u64
__raw_rm_readq(volatile void __iomem
*paddr
)
402 __asm__
__volatile__("ldcix %0,0, %1"
403 : "=r" (ret
) : "r" (paddr
) : "memory");
406 #endif /* __powerpc64__ */
410 * PCI PIO and MMIO accessors.
413 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
414 * machine checks (which they occasionally do when probing non existing
415 * IO ports on some platforms, like PowerMac and 8xx).
416 * I always found it to be of dubious reliability and I am tempted to get
417 * rid of it one of these days. So if you think it's important to keep it,
418 * please voice up asap. We never had it for 64 bits and I do not intend
424 #define __do_in_asm(name, op) \
425 static inline unsigned int name(unsigned int port) \
428 __asm__ __volatile__( \
430 "0:" op " %0,0,%1\n" \
435 ".section .fixup,\"ax\"\n" \
444 : "r" (port + _IO_BASE) \
449 #define __do_out_asm(name, op) \
450 static inline void name(unsigned int val, unsigned int port) \
452 __asm__ __volatile__( \
454 "0:" op " %0,0,%1\n" \
459 : : "r" (val), "r" (port + _IO_BASE) \
463 __do_in_asm(_rec_inb
, "lbzx")
464 __do_in_asm(_rec_inw
, "lhbrx")
465 __do_in_asm(_rec_inl
, "lwbrx")
466 __do_out_asm(_rec_outb
, "stbx")
467 __do_out_asm(_rec_outw
, "sthbrx")
468 __do_out_asm(_rec_outl
, "stwbrx")
470 #endif /* CONFIG_PPC32 */
472 /* The "__do_*" operations below provide the actual "base" implementation
473 * for each of the defined accessors. Some of them use the out_* functions
474 * directly, some of them still use EEH, though we might change that in the
475 * future. Those macros below provide the necessary argument swapping and
476 * handling of the IO base for PIO.
478 * They are themselves used by the macros that define the actual accessors
479 * and can be used by the hooks if any.
481 * Note that PIO operations are always defined in terms of their corresonding
482 * MMIO operations. That allows platforms like iSeries who want to modify the
483 * behaviour of both to only hook on the MMIO version and get both. It's also
484 * possible to hook directly at the toplevel PIO operation if they have to
485 * be handled differently
487 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
488 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
489 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
490 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
491 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
492 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
493 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
496 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
497 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
498 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
499 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
500 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
501 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
502 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
503 #else /* CONFIG_EEH */
504 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
505 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
506 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
507 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
508 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
509 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
510 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
511 #endif /* !defined(CONFIG_EEH) */
514 #define __do_outb(val, port) _rec_outb(val, port)
515 #define __do_outw(val, port) _rec_outw(val, port)
516 #define __do_outl(val, port) _rec_outl(val, port)
517 #define __do_inb(port) _rec_inb(port)
518 #define __do_inw(port) _rec_inw(port)
519 #define __do_inl(port) _rec_inl(port)
520 #else /* CONFIG_PPC32 */
521 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
522 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
523 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
524 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
525 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
526 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
527 #endif /* !CONFIG_PPC32 */
530 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
531 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
532 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
533 #else /* CONFIG_EEH */
534 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
535 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
536 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
537 #endif /* !CONFIG_EEH */
538 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
539 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
540 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
542 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
543 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
544 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
545 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
546 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
547 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
549 #define __do_memset_io(addr, c, n) \
550 _memset_io(PCI_FIX_ADDR(addr), c, n)
551 #define __do_memcpy_toio(dst, src, n) \
552 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
555 #define __do_memcpy_fromio(dst, src, n) \
556 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
557 #else /* CONFIG_EEH */
558 #define __do_memcpy_fromio(dst, src, n) \
559 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
560 #endif /* !CONFIG_EEH */
562 #ifdef CONFIG_PPC_INDIRECT_PIO
563 #define DEF_PCI_HOOK_pio(x) x
565 #define DEF_PCI_HOOK_pio(x) NULL
568 #ifdef CONFIG_PPC_INDIRECT_MMIO
569 #define DEF_PCI_HOOK_mem(x) x
571 #define DEF_PCI_HOOK_mem(x) NULL
574 /* Structure containing all the hooks */
575 extern struct ppc_pci_io
{
577 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
578 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
580 #include <asm/io-defs.h>
582 #undef DEF_PCI_AC_RET
583 #undef DEF_PCI_AC_NORET
587 /* The inline wrappers */
588 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
589 static inline ret name at \
591 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
592 return ppc_pci_io.name al; \
593 return __do_##name al; \
596 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
597 static inline void name at \
599 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
600 ppc_pci_io.name al; \
605 #include <asm/io-defs.h>
607 #undef DEF_PCI_AC_RET
608 #undef DEF_PCI_AC_NORET
610 /* Some drivers check for the presence of readq & writeq with
611 * a #ifdef, so we make them happy here.
615 #define writeq writeq
619 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
622 #define xlate_dev_mem_ptr(p) __va(p)
625 * Convert a virtual cached pointer to an uncached pointer
627 #define xlate_dev_kmem_ptr(p) p
630 * We don't do relaxed operations yet, at least not with this semantic
632 #define readb_relaxed(addr) readb(addr)
633 #define readw_relaxed(addr) readw(addr)
634 #define readl_relaxed(addr) readl(addr)
635 #define readq_relaxed(addr) readq(addr)
636 #define writeb_relaxed(v, addr) writeb(v, addr)
637 #define writew_relaxed(v, addr) writew(v, addr)
638 #define writel_relaxed(v, addr) writel(v, addr)
639 #define writeq_relaxed(v, addr) writeq(v, addr)
641 #include <asm-generic/iomap.h>
643 static inline void iosync(void)
645 __asm__
__volatile__ ("sync" : : : "memory");
648 /* Enforce in-order execution of data I/O.
649 * No distinction between read/write on PPC; use eieio for all three.
650 * Those are fairly week though. They don't provide a barrier between
651 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
652 * they only provide barriers between 2 __raw MMIO operations and
653 * possibly break write combining.
655 #define iobarrier_rw() eieio()
656 #define iobarrier_r() eieio()
657 #define iobarrier_w() eieio()
661 * output pause versions need a delay at least for the
662 * w83c105 ide controller in a p610.
664 #define inb_p(port) inb(port)
665 #define outb_p(val, port) (udelay(1), outb((val), (port)))
666 #define inw_p(port) inw(port)
667 #define outw_p(val, port) (udelay(1), outw((val), (port)))
668 #define inl_p(port) inl(port)
669 #define outl_p(val, port) (udelay(1), outl((val), (port)))
672 #define IO_SPACE_LIMIT ~(0UL)
676 * ioremap - map bus memory into CPU space
677 * @address: bus address of the memory
678 * @size: size of the resource to map
680 * ioremap performs a platform specific sequence of operations to
681 * make bus memory CPU accessible via the readb/readw/readl/writeb/
682 * writew/writel functions and the other mmio helpers. The returned
683 * address is not guaranteed to be usable directly as a virtual
686 * We provide a few variations of it:
688 * * ioremap is the standard one and provides non-cacheable guarded mappings
689 * and can be hooked by the platform via ppc_md
691 * * ioremap_prot allows to specify the page flags as an argument and can
692 * also be hooked by the platform via ppc_md.
694 * * ioremap_nocache is identical to ioremap
696 * * ioremap_wc enables write combining
698 * * ioremap_wt enables write through
700 * * ioremap_coherent maps coherent cached memory
702 * * iounmap undoes such a mapping and can be hooked
704 * * __ioremap_at (and the pending __iounmap_at) are low level functions to
705 * create hand-made mappings for use only by the PCI code and cannot
706 * currently be hooked. Must be page aligned.
708 * * __ioremap is the low level implementation used by ioremap and
709 * ioremap_prot and cannot be hooked (but can be used by a hook on one
710 * of the previous ones)
712 * * __ioremap_caller is the same as above but takes an explicit caller
713 * reference rather than using __builtin_return_address(0)
715 * * __iounmap, is the low level implementation used by iounmap and cannot
716 * be hooked (but can be used by a hook on iounmap)
719 extern void __iomem
*ioremap(phys_addr_t address
, unsigned long size
);
720 extern void __iomem
*ioremap_prot(phys_addr_t address
, unsigned long size
,
721 unsigned long flags
);
722 extern void __iomem
*ioremap_wc(phys_addr_t address
, unsigned long size
);
723 void __iomem
*ioremap_wt(phys_addr_t address
, unsigned long size
);
724 void __iomem
*ioremap_coherent(phys_addr_t address
, unsigned long size
);
725 #define ioremap_nocache(addr, size) ioremap((addr), (size))
726 #define ioremap_uc(addr, size) ioremap((addr), (size))
727 #define ioremap_cache(addr, size) \
728 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
730 extern void iounmap(volatile void __iomem
*addr
);
732 extern void __iomem
*__ioremap(phys_addr_t
, unsigned long size
,
733 unsigned long flags
);
734 extern void __iomem
*__ioremap_caller(phys_addr_t
, unsigned long size
,
735 pgprot_t prot
, void *caller
);
737 extern void __iounmap(volatile void __iomem
*addr
);
739 extern void __iomem
* __ioremap_at(phys_addr_t pa
, void *ea
,
740 unsigned long size
, pgprot_t prot
);
741 extern void __iounmap_at(void *ea
, unsigned long size
);
744 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
745 * which needs some additional definitions here. They basically allow PIO
746 * space overall to be 1GB. This will work as long as we never try to use
747 * iomap to map MMIO below 1GB which should be fine on ppc64
749 #define HAVE_ARCH_PIO_SIZE 1
750 #define PIO_OFFSET 0x00000000UL
751 #define PIO_MASK (FULL_IO_SIZE - 1)
752 #define PIO_RESERVED (FULL_IO_SIZE)
754 #define mmio_read16be(addr) readw_be(addr)
755 #define mmio_read32be(addr) readl_be(addr)
756 #define mmio_read64be(addr) readq_be(addr)
757 #define mmio_write16be(val, addr) writew_be(val, addr)
758 #define mmio_write32be(val, addr) writel_be(val, addr)
759 #define mmio_write64be(val, addr) writeq_be(val, addr)
760 #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
761 #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
762 #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
763 #define mmio_outsb(addr, src, count) writesb(addr, src, count)
764 #define mmio_outsw(addr, src, count) writesw(addr, src, count)
765 #define mmio_outsl(addr, src, count) writesl(addr, src, count)
768 * virt_to_phys - map virtual addresses to physical
769 * @address: address to remap
771 * The returned physical address is the physical (CPU) mapping for
772 * the memory address given. It is only valid to use this function on
773 * addresses directly mapped or allocated via kmalloc.
775 * This function does not give bus mappings for DMA transfers. In
776 * almost all conceivable cases a device driver should not be using
779 static inline unsigned long virt_to_phys(volatile void * address
)
781 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL
) && !virt_addr_valid(address
));
783 return __pa((unsigned long)address
);
787 * phys_to_virt - map physical address to virtual
788 * @address: address to remap
790 * The returned virtual address is a current CPU mapping for
791 * the memory address given. It is only valid to use this function on
792 * addresses that have a kernel mapping
794 * This function does not handle bus mappings for DMA transfers. In
795 * almost all conceivable cases a device driver should not be using
798 static inline void * phys_to_virt(unsigned long address
)
800 return (void *)__va(address
);
804 * Change "struct page" to physical address.
806 static inline phys_addr_t
page_to_phys(struct page
*page
)
808 unsigned long pfn
= page_to_pfn(page
);
810 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL
) && !pfn_valid(pfn
));
812 return PFN_PHYS(pfn
);
816 * 32 bits still uses virt_to_bus() for it's implementation of DMA
817 * mappings se we have to keep it defined here. We also have some old
818 * drivers (shame shame shame) that use bus_to_virt() and haven't been
819 * fixed yet so I need to define it here.
823 static inline unsigned long virt_to_bus(volatile void * address
)
827 return __pa(address
) + PCI_DRAM_OFFSET
;
830 static inline void * bus_to_virt(unsigned long address
)
834 return __va(address
- PCI_DRAM_OFFSET
);
837 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
839 #endif /* CONFIG_PPC32 */
842 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
843 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
845 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
846 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
848 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
849 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
851 /* Clear and set bits in one shot. These macros can be used to clear and
852 * set multiple bits in a register using a single read-modify-write. These
853 * macros can also be used to set a multiple-bit bit pattern using a mask,
854 * by specifying the mask in the 'clear' parameter and the new bit pattern
855 * in the 'set' parameter.
858 #define clrsetbits(type, addr, clear, set) \
859 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
862 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
863 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
866 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
867 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
869 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
870 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
872 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
874 #endif /* __KERNEL__ */
876 #endif /* _ASM_POWERPC_IO_H */