1 #ifndef _ASM_POWERPC_IO_H
2 #define _ASM_POWERPC_IO_H
5 #define ARCH_HAS_IOREMAP_WC
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 /* Check of existence of legacy devices */
15 extern int check_legacy_ioport(unsigned long base_port
);
16 #define I8042_DATA_REG 0x60
17 #define FDC_BASE 0x3f0
19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
20 extern struct pci_dev
*isa_bridge_pcidev
;
22 * has legacy ISA devices ?
24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
27 #include <linux/device.h>
30 #include <linux/compiler.h>
32 #include <asm/byteorder.h>
33 #include <asm/synch.h>
34 #include <asm/delay.h>
37 #include <asm-generic/iomap.h>
43 #define SIO_CONFIG_RA 0x398
44 #define SIO_CONFIG_RD 0x399
48 /* 32 bits uses slightly different variables for the various IO
49 * bases. Most of this file only uses _IO_BASE though which we
50 * define properly based on the platform
54 #define _ISA_MEM_BASE 0
55 #define PCI_DRAM_OFFSET 0
56 #elif defined(CONFIG_PPC32)
57 #define _IO_BASE isa_io_base
58 #define _ISA_MEM_BASE isa_mem_base
59 #define PCI_DRAM_OFFSET pci_dram_offset
61 #define _IO_BASE pci_io_base
62 #define _ISA_MEM_BASE isa_mem_base
63 #define PCI_DRAM_OFFSET 0
66 extern unsigned long isa_io_base
;
67 extern unsigned long pci_io_base
;
68 extern unsigned long pci_dram_offset
;
70 extern resource_size_t isa_mem_base
;
72 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
73 * is not set or addresses cannot be translated to MMIO. This is typically
74 * set when the platform supports "special" PIO accesses via a non memory
75 * mapped mechanism, and allows things like the early udbg UART code to
78 extern bool isa_io_special
;
81 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
82 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
88 * Low level MMIO accessors
90 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
91 * specific and thus shouldn't be used in generic code. The accessors
94 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
95 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
96 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
98 * Those operate directly on a kernel virtual address. Note that the prototype
99 * for the out_* accessors has the arguments in opposite order from the usual
100 * linux PCI accessors. Unlike those, they take the address first and the value
103 * Note: I might drop the _ns suffix on the stream operations soon as it is
104 * simply normal for stream operations to not swap in the first place.
109 #define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0)
111 #define IO_SET_SYNC_FLAG()
114 /* gcc 4.0 and older doesn't have 'Z' constraint */
115 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
116 #define DEF_MMIO_IN_X(name, size, insn) \
117 static inline u##size name(const volatile u##size __iomem *addr) \
120 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \
121 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \
125 #define DEF_MMIO_OUT_X(name, size, insn) \
126 static inline void name(volatile u##size __iomem *addr, u##size val) \
128 __asm__ __volatile__("sync;"#insn" %1,0,%2" \
129 : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \
130 IO_SET_SYNC_FLAG(); \
132 #else /* newer gcc */
133 #define DEF_MMIO_IN_X(name, size, insn) \
134 static inline u##size name(const volatile u##size __iomem *addr) \
137 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
138 : "=r" (ret) : "Z" (*addr) : "memory"); \
142 #define DEF_MMIO_OUT_X(name, size, insn) \
143 static inline void name(volatile u##size __iomem *addr, u##size val) \
145 __asm__ __volatile__("sync;"#insn" %1,%y0" \
146 : "=Z" (*addr) : "r" (val) : "memory"); \
147 IO_SET_SYNC_FLAG(); \
151 #define DEF_MMIO_IN_D(name, size, insn) \
152 static inline u##size name(const volatile u##size __iomem *addr) \
155 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
156 : "=r" (ret) : "m" (*addr) : "memory"); \
160 #define DEF_MMIO_OUT_D(name, size, insn) \
161 static inline void name(volatile u##size __iomem *addr, u##size val) \
163 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
164 : "=m" (*addr) : "r" (val) : "memory"); \
165 IO_SET_SYNC_FLAG(); \
168 DEF_MMIO_IN_D(in_8
, 8, lbz
);
169 DEF_MMIO_OUT_D(out_8
, 8, stb
);
171 #ifdef __BIG_ENDIAN__
172 DEF_MMIO_IN_D(in_be16
, 16, lhz
);
173 DEF_MMIO_IN_D(in_be32
, 32, lwz
);
174 DEF_MMIO_IN_X(in_le16
, 16, lhbrx
);
175 DEF_MMIO_IN_X(in_le32
, 32, lwbrx
);
177 DEF_MMIO_OUT_D(out_be16
, 16, sth
);
178 DEF_MMIO_OUT_D(out_be32
, 32, stw
);
179 DEF_MMIO_OUT_X(out_le16
, 16, sthbrx
);
180 DEF_MMIO_OUT_X(out_le32
, 32, stwbrx
);
182 DEF_MMIO_IN_X(in_be16
, 16, lhbrx
);
183 DEF_MMIO_IN_X(in_be32
, 32, lwbrx
);
184 DEF_MMIO_IN_D(in_le16
, 16, lhz
);
185 DEF_MMIO_IN_D(in_le32
, 32, lwz
);
187 DEF_MMIO_OUT_X(out_be16
, 16, sthbrx
);
188 DEF_MMIO_OUT_X(out_be32
, 32, stwbrx
);
189 DEF_MMIO_OUT_D(out_le16
, 16, sth
);
190 DEF_MMIO_OUT_D(out_le32
, 32, stw
);
192 #endif /* __BIG_ENDIAN */
195 * Cache inhibitied accessors for use in real mode, you don't want to use these
196 * unless you know what you're doing.
198 * NB. These use the cpu byte ordering.
200 DEF_MMIO_OUT_X(out_rm8
, 8, stbcix
);
201 DEF_MMIO_OUT_X(out_rm16
, 16, sthcix
);
202 DEF_MMIO_OUT_X(out_rm32
, 32, stwcix
);
203 DEF_MMIO_IN_X(in_rm8
, 8, lbzcix
);
204 DEF_MMIO_IN_X(in_rm16
, 16, lhzcix
);
205 DEF_MMIO_IN_X(in_rm32
, 32, lwzcix
);
209 DEF_MMIO_OUT_X(out_rm64
, 64, stdcix
);
210 DEF_MMIO_IN_X(in_rm64
, 64, ldcix
);
212 #ifdef __BIG_ENDIAN__
213 DEF_MMIO_OUT_D(out_be64
, 64, std
);
214 DEF_MMIO_IN_D(in_be64
, 64, ld
);
216 /* There is no asm instructions for 64 bits reverse loads and stores */
217 static inline u64
in_le64(const volatile u64 __iomem
*addr
)
219 return swab64(in_be64(addr
));
222 static inline void out_le64(volatile u64 __iomem
*addr
, u64 val
)
224 out_be64(addr
, swab64(val
));
227 DEF_MMIO_OUT_D(out_le64
, 64, std
);
228 DEF_MMIO_IN_D(in_le64
, 64, ld
);
230 /* There is no asm instructions for 64 bits reverse loads and stores */
231 static inline u64
in_be64(const volatile u64 __iomem
*addr
)
233 return swab64(in_le64(addr
));
236 static inline void out_be64(volatile u64 __iomem
*addr
, u64 val
)
238 out_le64(addr
, swab64(val
));
242 #endif /* __powerpc64__ */
245 * Low level IO stream instructions are defined out of line for now
247 extern void _insb(const volatile u8 __iomem
*addr
, void *buf
, long count
);
248 extern void _outsb(volatile u8 __iomem
*addr
,const void *buf
,long count
);
249 extern void _insw_ns(const volatile u16 __iomem
*addr
, void *buf
, long count
);
250 extern void _outsw_ns(volatile u16 __iomem
*addr
, const void *buf
, long count
);
251 extern void _insl_ns(const volatile u32 __iomem
*addr
, void *buf
, long count
);
252 extern void _outsl_ns(volatile u32 __iomem
*addr
, const void *buf
, long count
);
254 /* The _ns naming is historical and will be removed. For now, just #define
255 * the non _ns equivalent names
257 #define _insw _insw_ns
258 #define _insl _insl_ns
259 #define _outsw _outsw_ns
260 #define _outsl _outsl_ns
264 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
267 extern void _memset_io(volatile void __iomem
*addr
, int c
, unsigned long n
);
268 extern void _memcpy_fromio(void *dest
, const volatile void __iomem
*src
,
270 extern void _memcpy_toio(volatile void __iomem
*dest
, const void *src
,
275 * PCI and standard ISA accessors
277 * Those are globally defined linux accessors for devices on PCI or ISA
278 * busses. They follow the Linux defined semantics. The current implementation
279 * for PowerPC is as close as possible to the x86 version of these, and thus
280 * provides fairly heavy weight barriers for the non-raw versions
282 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
283 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
284 * own implementation of some or all of the accessors.
288 * Include the EEH definitions when EEH is enabled only so they don't get
289 * in the way when building for 32 bits
295 /* Shortcut to the MMIO argument pointer */
296 #define PCI_IO_ADDR volatile void __iomem *
298 /* Indirect IO address tokens:
300 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
301 * on all MMIOs. (Note that this is all 64 bits only for now)
303 * To help platforms who may need to differenciate MMIO addresses in
304 * their hooks, a bitfield is reserved for use by the platform near the
305 * top of MMIO addresses (not PIO, those have to cope the hard way).
307 * This bit field is 12 bits and is at the top of the IO virtual
308 * addresses PCI_IO_INDIRECT_TOKEN_MASK.
310 * The kernel virtual space is thus:
312 * 0xD000000000000000 : vmalloc
313 * 0xD000080000000000 : PCI PHB IO space
314 * 0xD000080080000000 : ioremap
315 * 0xD0000fffffffffff : end of ioremap region
317 * Since the top 4 bits are reserved as the region ID, we use thus
318 * the next 12 bits and keep 4 bits available for the future if the
319 * virtual address space is ever to be extended.
321 * The direct IO mapping operations will then mask off those bits
322 * before doing the actual access, though that only happen when
323 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
326 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
327 * all PIO functions call through a hook.
330 #ifdef CONFIG_PPC_INDIRECT_MMIO
331 #define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul
332 #define PCI_IO_IND_TOKEN_SHIFT 48
333 #define PCI_FIX_ADDR(addr) \
334 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
335 #define PCI_GET_ADDR_TOKEN(addr) \
336 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
337 PCI_IO_IND_TOKEN_SHIFT)
338 #define PCI_SET_ADDR_TOKEN(addr, token) \
340 unsigned long __a = (unsigned long)(addr); \
341 __a &= ~PCI_IO_IND_TOKEN_MASK; \
342 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
343 (addr) = (void __iomem *)__a; \
346 #define PCI_FIX_ADDR(addr) (addr)
351 * Non ordered and non-swapping "raw" accessors
354 static inline unsigned char __raw_readb(const volatile void __iomem
*addr
)
356 return *(volatile unsigned char __force
*)PCI_FIX_ADDR(addr
);
358 static inline unsigned short __raw_readw(const volatile void __iomem
*addr
)
360 return *(volatile unsigned short __force
*)PCI_FIX_ADDR(addr
);
362 static inline unsigned int __raw_readl(const volatile void __iomem
*addr
)
364 return *(volatile unsigned int __force
*)PCI_FIX_ADDR(addr
);
366 static inline void __raw_writeb(unsigned char v
, volatile void __iomem
*addr
)
368 *(volatile unsigned char __force
*)PCI_FIX_ADDR(addr
) = v
;
370 static inline void __raw_writew(unsigned short v
, volatile void __iomem
*addr
)
372 *(volatile unsigned short __force
*)PCI_FIX_ADDR(addr
) = v
;
374 static inline void __raw_writel(unsigned int v
, volatile void __iomem
*addr
)
376 *(volatile unsigned int __force
*)PCI_FIX_ADDR(addr
) = v
;
380 static inline unsigned long __raw_readq(const volatile void __iomem
*addr
)
382 return *(volatile unsigned long __force
*)PCI_FIX_ADDR(addr
);
384 static inline void __raw_writeq(unsigned long v
, volatile void __iomem
*addr
)
386 *(volatile unsigned long __force
*)PCI_FIX_ADDR(addr
) = v
;
390 * Real mode version of the above. stdcix is only supposed to be used
391 * in hypervisor real mode as per the architecture spec.
393 static inline void __raw_rm_writeq(u64 val
, volatile void __iomem
*paddr
)
395 __asm__
__volatile__("stdcix %0,0,%1"
396 : : "r" (val
), "r" (paddr
) : "memory");
399 #endif /* __powerpc64__ */
403 * PCI PIO and MMIO accessors.
406 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
407 * machine checks (which they occasionally do when probing non existing
408 * IO ports on some platforms, like PowerMac and 8xx).
409 * I always found it to be of dubious reliability and I am tempted to get
410 * rid of it one of these days. So if you think it's important to keep it,
411 * please voice up asap. We never had it for 64 bits and I do not intend
417 #define __do_in_asm(name, op) \
418 static inline unsigned int name(unsigned int port) \
421 __asm__ __volatile__( \
423 "0:" op " %0,0,%1\n" \
428 ".section .fixup,\"ax\"\n" \
432 ".section __ex_table,\"a\"\n" \
440 : "r" (port + _IO_BASE) \
445 #define __do_out_asm(name, op) \
446 static inline void name(unsigned int val, unsigned int port) \
448 __asm__ __volatile__( \
450 "0:" op " %0,0,%1\n" \
453 ".section __ex_table,\"a\"\n" \
458 : : "r" (val), "r" (port + _IO_BASE) \
462 __do_in_asm(_rec_inb
, "lbzx")
463 __do_in_asm(_rec_inw
, "lhbrx")
464 __do_in_asm(_rec_inl
, "lwbrx")
465 __do_out_asm(_rec_outb
, "stbx")
466 __do_out_asm(_rec_outw
, "sthbrx")
467 __do_out_asm(_rec_outl
, "stwbrx")
469 #endif /* CONFIG_PPC32 */
471 /* The "__do_*" operations below provide the actual "base" implementation
472 * for each of the defined accessors. Some of them use the out_* functions
473 * directly, some of them still use EEH, though we might change that in the
474 * future. Those macros below provide the necessary argument swapping and
475 * handling of the IO base for PIO.
477 * They are themselves used by the macros that define the actual accessors
478 * and can be used by the hooks if any.
480 * Note that PIO operations are always defined in terms of their corresonding
481 * MMIO operations. That allows platforms like iSeries who want to modify the
482 * behaviour of both to only hook on the MMIO version and get both. It's also
483 * possible to hook directly at the toplevel PIO operation if they have to
484 * be handled differently
486 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
487 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
488 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
489 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
490 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
491 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
492 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
495 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
496 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
497 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
498 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
499 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
500 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
501 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
502 #else /* CONFIG_EEH */
503 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
504 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
505 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
506 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
507 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
508 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
509 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
510 #endif /* !defined(CONFIG_EEH) */
513 #define __do_outb(val, port) _rec_outb(val, port)
514 #define __do_outw(val, port) _rec_outw(val, port)
515 #define __do_outl(val, port) _rec_outl(val, port)
516 #define __do_inb(port) _rec_inb(port)
517 #define __do_inw(port) _rec_inw(port)
518 #define __do_inl(port) _rec_inl(port)
519 #else /* CONFIG_PPC32 */
520 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
521 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
522 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
523 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
524 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
525 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
526 #endif /* !CONFIG_PPC32 */
529 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
530 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
531 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
532 #else /* CONFIG_EEH */
533 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
534 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
535 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
536 #endif /* !CONFIG_EEH */
537 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
538 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
539 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
541 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
542 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
543 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
544 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
545 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
546 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
548 #define __do_memset_io(addr, c, n) \
549 _memset_io(PCI_FIX_ADDR(addr), c, n)
550 #define __do_memcpy_toio(dst, src, n) \
551 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
554 #define __do_memcpy_fromio(dst, src, n) \
555 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
556 #else /* CONFIG_EEH */
557 #define __do_memcpy_fromio(dst, src, n) \
558 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
559 #endif /* !CONFIG_EEH */
561 #ifdef CONFIG_PPC_INDIRECT_PIO
562 #define DEF_PCI_HOOK_pio(x) x
564 #define DEF_PCI_HOOK_pio(x) NULL
567 #ifdef CONFIG_PPC_INDIRECT_MMIO
568 #define DEF_PCI_HOOK_mem(x) x
570 #define DEF_PCI_HOOK_mem(x) NULL
573 /* Structure containing all the hooks */
574 extern struct ppc_pci_io
{
576 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
577 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
579 #include <asm/io-defs.h>
581 #undef DEF_PCI_AC_RET
582 #undef DEF_PCI_AC_NORET
586 /* The inline wrappers */
587 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
588 static inline ret name at \
590 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
591 return ppc_pci_io.name al; \
592 return __do_##name al; \
595 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
596 static inline void name at \
598 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
599 ppc_pci_io.name al; \
604 #include <asm/io-defs.h>
606 #undef DEF_PCI_AC_RET
607 #undef DEF_PCI_AC_NORET
609 /* Some drivers check for the presence of readq & writeq with
610 * a #ifdef, so we make them happy here.
614 #define writeq writeq
618 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
621 #define xlate_dev_mem_ptr(p) __va(p)
624 * Convert a virtual cached pointer to an uncached pointer
626 #define xlate_dev_kmem_ptr(p) p
629 * We don't do relaxed operations yet, at least not with this semantic
631 #define readb_relaxed(addr) readb(addr)
632 #define readw_relaxed(addr) readw(addr)
633 #define readl_relaxed(addr) readl(addr)
634 #define readq_relaxed(addr) readq(addr)
635 #define writeb_relaxed(v, addr) writeb(v, addr)
636 #define writew_relaxed(v, addr) writew(v, addr)
637 #define writel_relaxed(v, addr) writel(v, addr)
638 #define writeq_relaxed(v, addr) writeq(v, addr)
644 * Enforce synchronisation of stores vs. spin_unlock
645 * (this does it explicitly, though our implementation of spin_unlock
646 * does it implicitely too)
648 static inline void mmiowb(void)
652 __asm__
__volatile__("sync; li %0,0; stb %0,%1(13)"
653 : "=&r" (tmp
) : "i" (offsetof(struct paca_struct
, io_sync
))
656 #endif /* !CONFIG_PPC32 */
658 static inline void iosync(void)
660 __asm__
__volatile__ ("sync" : : : "memory");
663 /* Enforce in-order execution of data I/O.
664 * No distinction between read/write on PPC; use eieio for all three.
665 * Those are fairly week though. They don't provide a barrier between
666 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
667 * they only provide barriers between 2 __raw MMIO operations and
668 * possibly break write combining.
670 #define iobarrier_rw() eieio()
671 #define iobarrier_r() eieio()
672 #define iobarrier_w() eieio()
676 * output pause versions need a delay at least for the
677 * w83c105 ide controller in a p610.
679 #define inb_p(port) inb(port)
680 #define outb_p(val, port) (udelay(1), outb((val), (port)))
681 #define inw_p(port) inw(port)
682 #define outw_p(val, port) (udelay(1), outw((val), (port)))
683 #define inl_p(port) inl(port)
684 #define outl_p(val, port) (udelay(1), outl((val), (port)))
687 #define IO_SPACE_LIMIT ~(0UL)
691 * ioremap - map bus memory into CPU space
692 * @address: bus address of the memory
693 * @size: size of the resource to map
695 * ioremap performs a platform specific sequence of operations to
696 * make bus memory CPU accessible via the readb/readw/readl/writeb/
697 * writew/writel functions and the other mmio helpers. The returned
698 * address is not guaranteed to be usable directly as a virtual
701 * We provide a few variations of it:
703 * * ioremap is the standard one and provides non-cacheable guarded mappings
704 * and can be hooked by the platform via ppc_md
706 * * ioremap_prot allows to specify the page flags as an argument and can
707 * also be hooked by the platform via ppc_md.
709 * * ioremap_nocache is identical to ioremap
711 * * ioremap_wc enables write combining
713 * * iounmap undoes such a mapping and can be hooked
715 * * __ioremap_at (and the pending __iounmap_at) are low level functions to
716 * create hand-made mappings for use only by the PCI code and cannot
717 * currently be hooked. Must be page aligned.
719 * * __ioremap is the low level implementation used by ioremap and
720 * ioremap_prot and cannot be hooked (but can be used by a hook on one
721 * of the previous ones)
723 * * __ioremap_caller is the same as above but takes an explicit caller
724 * reference rather than using __builtin_return_address(0)
726 * * __iounmap, is the low level implementation used by iounmap and cannot
727 * be hooked (but can be used by a hook on iounmap)
730 extern void __iomem
*ioremap(phys_addr_t address
, unsigned long size
);
731 extern void __iomem
*ioremap_prot(phys_addr_t address
, unsigned long size
,
732 unsigned long flags
);
733 extern void __iomem
*ioremap_wc(phys_addr_t address
, unsigned long size
);
734 #define ioremap_nocache(addr, size) ioremap((addr), (size))
735 #define ioremap_uc(addr, size) ioremap((addr), (size))
737 extern void iounmap(volatile void __iomem
*addr
);
739 extern void __iomem
*__ioremap(phys_addr_t
, unsigned long size
,
740 unsigned long flags
);
741 extern void __iomem
*__ioremap_caller(phys_addr_t
, unsigned long size
,
742 unsigned long flags
, void *caller
);
744 extern void __iounmap(volatile void __iomem
*addr
);
746 extern void __iomem
* __ioremap_at(phys_addr_t pa
, void *ea
,
747 unsigned long size
, unsigned long flags
);
748 extern void __iounmap_at(void *ea
, unsigned long size
);
751 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
752 * which needs some additional definitions here. They basically allow PIO
753 * space overall to be 1GB. This will work as long as we never try to use
754 * iomap to map MMIO below 1GB which should be fine on ppc64
756 #define HAVE_ARCH_PIO_SIZE 1
757 #define PIO_OFFSET 0x00000000UL
758 #define PIO_MASK (FULL_IO_SIZE - 1)
759 #define PIO_RESERVED (FULL_IO_SIZE)
761 #define mmio_read16be(addr) readw_be(addr)
762 #define mmio_read32be(addr) readl_be(addr)
763 #define mmio_write16be(val, addr) writew_be(val, addr)
764 #define mmio_write32be(val, addr) writel_be(val, addr)
765 #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
766 #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
767 #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
768 #define mmio_outsb(addr, src, count) writesb(addr, src, count)
769 #define mmio_outsw(addr, src, count) writesw(addr, src, count)
770 #define mmio_outsl(addr, src, count) writesl(addr, src, count)
773 * virt_to_phys - map virtual addresses to physical
774 * @address: address to remap
776 * The returned physical address is the physical (CPU) mapping for
777 * the memory address given. It is only valid to use this function on
778 * addresses directly mapped or allocated via kmalloc.
780 * This function does not give bus mappings for DMA transfers. In
781 * almost all conceivable cases a device driver should not be using
784 static inline unsigned long virt_to_phys(volatile void * address
)
786 return __pa((unsigned long)address
);
790 * phys_to_virt - map physical address to virtual
791 * @address: address to remap
793 * The returned virtual address is a current CPU mapping for
794 * the memory address given. It is only valid to use this function on
795 * addresses that have a kernel mapping
797 * This function does not handle bus mappings for DMA transfers. In
798 * almost all conceivable cases a device driver should not be using
801 static inline void * phys_to_virt(unsigned long address
)
803 return (void *)__va(address
);
807 * Change "struct page" to physical address.
809 #define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)
812 * 32 bits still uses virt_to_bus() for it's implementation of DMA
813 * mappings se we have to keep it defined here. We also have some old
814 * drivers (shame shame shame) that use bus_to_virt() and haven't been
815 * fixed yet so I need to define it here.
819 static inline unsigned long virt_to_bus(volatile void * address
)
823 return __pa(address
) + PCI_DRAM_OFFSET
;
826 static inline void * bus_to_virt(unsigned long address
)
830 return __va(address
- PCI_DRAM_OFFSET
);
833 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
835 #endif /* CONFIG_PPC32 */
838 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
839 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
841 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
842 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
844 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
845 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
847 /* Clear and set bits in one shot. These macros can be used to clear and
848 * set multiple bits in a register using a single read-modify-write. These
849 * macros can also be used to set a multiple-bit bit pattern using a mask,
850 * by specifying the mask in the 'clear' parameter and the new bit pattern
851 * in the 'set' parameter.
854 #define clrsetbits(type, addr, clear, set) \
855 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
858 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
859 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
862 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
863 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
865 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
866 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
868 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
870 #endif /* __KERNEL__ */
872 #endif /* _ASM_POWERPC_IO_H */