arch/powerpc/include/asm/nohash/64/pgtable-4k.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H
   3 #define _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H
   4
   5 #include <asm-generic/5level-fixup.h>
   6
   7 /*
   8  * Entries per page directory level.  The PTE level must use a 64b record
   9  * for each page table entry.  The PMD and PGD level use a 32b record for
  10  * each entry by assuming that each entry is page aligned.
  11  */
  12 #define PTE_INDEX_SIZE  9
  13 #define PMD_INDEX_SIZE  7
  14 #define PUD_INDEX_SIZE  9
  15 #define PGD_INDEX_SIZE  9
  16
  17 #ifndef __ASSEMBLY__
  18 #define PTE_TABLE_SIZE  (sizeof(pte_t) << PTE_INDEX_SIZE)
  19 #define PMD_TABLE_SIZE  (sizeof(pmd_t) << PMD_INDEX_SIZE)
  20 #define PUD_TABLE_SIZE  (sizeof(pud_t) << PUD_INDEX_SIZE)
  21 #define PGD_TABLE_SIZE  (sizeof(pgd_t) << PGD_INDEX_SIZE)
  22 #endif  /* __ASSEMBLY__ */
  23
  24 #define PTRS_PER_PTE    (1 << PTE_INDEX_SIZE)
  25 #define PTRS_PER_PMD    (1 << PMD_INDEX_SIZE)
  26 #define PTRS_PER_PUD    (1 << PUD_INDEX_SIZE)
  27 #define PTRS_PER_PGD    (1 << PGD_INDEX_SIZE)
  28
  29 /* PMD_SHIFT determines what a second-level page table entry can map */
  30 #define PMD_SHIFT       (PAGE_SHIFT + PTE_INDEX_SIZE)
  31 #define PMD_SIZE        (1UL << PMD_SHIFT)
  32 #define PMD_MASK        (~(PMD_SIZE-1))
  33
  34 /* PUD_SHIFT determines what a third-level page table entry can map */
  35 #define PUD_SHIFT       (PMD_SHIFT + PMD_INDEX_SIZE)
  36 #define PUD_SIZE        (1UL << PUD_SHIFT)
  37 #define PUD_MASK        (~(PUD_SIZE-1))
  38
  39 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */
  40 #define PGDIR_SHIFT     (PUD_SHIFT + PUD_INDEX_SIZE)
  41 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  42 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  43
  44 /* Bits to mask out from a PMD to get to the PTE page */
  45 #define PMD_MASKED_BITS         0
  46 /* Bits to mask out from a PUD to get to the PMD page */
  47 #define PUD_MASKED_BITS         0
  48 /* Bits to mask out from a PGD to get to the PUD page */
  49 #define PGD_MASKED_BITS         0
  50
  51
  52 /*
  53  * 4-level page tables related bits
  54  */
  55
  56 #define pgd_none(pgd)           (!pgd_val(pgd))
  57 #define pgd_bad(pgd)            (pgd_val(pgd) == 0)
  58 #define pgd_present(pgd)        (pgd_val(pgd) != 0)
  59 #define pgd_page_vaddr(pgd)     (pgd_val(pgd) & ~PGD_MASKED_BITS)
  60
  61 #ifndef __ASSEMBLY__
  62
  63 static inline void pgd_clear(pgd_t *pgdp)
  64 {
  65         *pgdp = __pgd(0);
  66 }
  67
  68 static inline pte_t pgd_pte(pgd_t pgd)
  69 {
  70         return __pte(pgd_val(pgd));
  71 }
  72
  73 static inline pgd_t pte_pgd(pte_t pte)
  74 {
  75         return __pgd(pte_val(pte));
  76 }
  77 extern struct page *pgd_page(pgd_t pgd);
  78
  79 #endif /* !__ASSEMBLY__ */
  80
  81 #define pud_offset(pgdp, addr)  \
  82   (((pud_t *) pgd_page_vaddr(*(pgdp))) + \
  83     (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
  84
  85 #define pud_ERROR(e) \
  86         pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
  87
  88 /*
  89  * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range() */
  90 #define remap_4k_pfn(vma, addr, pfn, prot)      \
  91         remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
  92
  93 #endif /* _ _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H */