arch/powerpc/include/asm/nohash/64/pgtable.h

   1 #ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_H
   2 #define _ASM_POWERPC_NOHASH_64_PGTABLE_H
   3 /*
   4  * This file contains the functions and defines necessary to modify and use
   5  * the ppc64 hashed page table.
   6  */
   7
   8 #ifdef CONFIG_PPC_64K_PAGES
   9 #include <asm/nohash/64/pgtable-64k.h>
  10 #else
  11 #include <asm/nohash/64/pgtable-4k.h>
  12 #endif
  13 #include <asm/barrier.h>
  14
  15 #define FIRST_USER_ADDRESS      0UL
  16
  17 /*
  18  * Size of EA range mapped by our pagetables.
  19  */
  20 #define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
  21                             PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
  22 #define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
  23
  24 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
  25 #define PMD_CACHE_INDEX (PMD_INDEX_SIZE + 1)
  26 #else
  27 #define PMD_CACHE_INDEX PMD_INDEX_SIZE
  28 #endif
  29 /*
  30  * Define the address range of the kernel non-linear virtual area
  31  */
  32
  33 #ifdef CONFIG_PPC_BOOK3E
  34 #define KERN_VIRT_START ASM_CONST(0x8000000000000000)
  35 #else
  36 #define KERN_VIRT_START ASM_CONST(0xD000000000000000)
  37 #endif
  38 #define KERN_VIRT_SIZE  ASM_CONST(0x0000100000000000)
  39
  40 /*
  41  * The vmalloc space starts at the beginning of that region, and
  42  * occupies half of it on hash CPUs and a quarter of it on Book3E
  43  * (we keep a quarter for the virtual memmap)
  44  */
  45 #define VMALLOC_START   KERN_VIRT_START
  46 #ifdef CONFIG_PPC_BOOK3E
  47 #define VMALLOC_SIZE    (KERN_VIRT_SIZE >> 2)
  48 #else
  49 #define VMALLOC_SIZE    (KERN_VIRT_SIZE >> 1)
  50 #endif
  51 #define VMALLOC_END     (VMALLOC_START + VMALLOC_SIZE)
  52
  53 /*
  54  * The second half of the kernel virtual space is used for IO mappings,
  55  * it's itself carved into the PIO region (ISA and PHB IO space) and
  56  * the ioremap space
  57  *
  58  *  ISA_IO_BASE = KERN_IO_START, 64K reserved area
  59  *  PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
  60  * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
  61  */
  62 #define KERN_IO_START   (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
  63 #define FULL_IO_SIZE    0x80000000ul
  64 #define  ISA_IO_BASE    (KERN_IO_START)
  65 #define  ISA_IO_END     (KERN_IO_START + 0x10000ul)
  66 #define  PHB_IO_BASE    (ISA_IO_END)
  67 #define  PHB_IO_END     (KERN_IO_START + FULL_IO_SIZE)
  68 #define IOREMAP_BASE    (PHB_IO_END)
  69 #define IOREMAP_END     (KERN_VIRT_START + KERN_VIRT_SIZE)
  70
  71
  72 /*
  73  * Region IDs
  74  */
  75 #define REGION_SHIFT            60UL
  76 #define REGION_MASK             (0xfUL << REGION_SHIFT)
  77 #define REGION_ID(ea)           (((unsigned long)(ea)) >> REGION_SHIFT)
  78
  79 #define VMALLOC_REGION_ID       (REGION_ID(VMALLOC_START))
  80 #define KERNEL_REGION_ID        (REGION_ID(PAGE_OFFSET))
  81 #define VMEMMAP_REGION_ID       (0xfUL) /* Server only */
  82 #define USER_REGION_ID          (0UL)
  83
  84 /*
  85  * Defines the address of the vmemap area, in its own region on
  86  * hash table CPUs and after the vmalloc space on Book3E
  87  */
  88 #ifdef CONFIG_PPC_BOOK3E
  89 #define VMEMMAP_BASE            VMALLOC_END
  90 #define VMEMMAP_END             KERN_IO_START
  91 #else
  92 #define VMEMMAP_BASE            (VMEMMAP_REGION_ID << REGION_SHIFT)
  93 #endif
  94 #define vmemmap                 ((struct page *)VMEMMAP_BASE)
  95
  96
  97 /*
  98  * Include the PTE bits definitions
  99  */
 100 #include <asm/nohash/pte-book3e.h>
 101 #include <asm/pte-common.h>
 102
 103 #ifdef CONFIG_PPC_MM_SLICES
 104 #define HAVE_ARCH_UNMAPPED_AREA
 105 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 106 #endif /* CONFIG_PPC_MM_SLICES */
 107
 108 #ifndef __ASSEMBLY__
 109
 110 /*
 111  * This is the default implementation of various PTE accessors, it's
 112  * used in all cases except Book3S with 64K pages where we have a
 113  * concept of sub-pages
 114  */
 115 #ifndef __real_pte
 116
 117 #ifdef CONFIG_STRICT_MM_TYPECHECKS
 118 #define __real_pte(e,p)         ((real_pte_t){(e)})
 119 #define __rpte_to_pte(r)        ((r).pte)
 120 #else
 121 #define __real_pte(e,p)         (e)
 122 #define __rpte_to_pte(r)        (__pte(r))
 123 #endif
 124 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12)
 125
 126 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift)       \
 127         do {                                                             \
 128                 index = 0;                                               \
 129                 shift = mmu_psize_defs[psize].shift;                     \
 130
 131 #define pte_iterate_hashed_end() } while(0)
 132
 133 /*
 134  * We expect this to be called only for user addresses or kernel virtual
 135  * addresses other than the linear mapping.
 136  */
 137 #define pte_pagesize_index(mm, addr, pte)       MMU_PAGE_4K
 138
 139 #endif /* __real_pte */
 140
 141
 142 /* pte_clear moved to later in this file */
 143
 144 #define PMD_BAD_BITS            (PTE_TABLE_SIZE-1)
 145 #define PUD_BAD_BITS            (PMD_TABLE_SIZE-1)
 146
 147 static inline void pmd_set(pmd_t *pmdp, unsigned long val)
 148 {
 149         *pmdp = __pmd(val);
 150 }
 151
 152 static inline void pmd_clear(pmd_t *pmdp)
 153 {
 154         *pmdp = __pmd(0);
 155 }
 156
 157 static inline pte_t pmd_pte(pmd_t pmd)
 158 {
 159         return __pte(pmd_val(pmd));
 160 }
 161
 162 #define pmd_none(pmd)           (!pmd_val(pmd))
 163 #define pmd_bad(pmd)            (!is_kernel_addr(pmd_val(pmd)) \
 164                                  || (pmd_val(pmd) & PMD_BAD_BITS))
 165 #define pmd_present(pmd)        (!pmd_none(pmd))
 166 #define pmd_page_vaddr(pmd)     (pmd_val(pmd) & ~PMD_MASKED_BITS)
 167 extern struct page *pmd_page(pmd_t pmd);
 168
 169 static inline void pud_set(pud_t *pudp, unsigned long val)
 170 {
 171         *pudp = __pud(val);
 172 }
 173
 174 static inline void pud_clear(pud_t *pudp)
 175 {
 176         *pudp = __pud(0);
 177 }
 178
 179 #define pud_none(pud)           (!pud_val(pud))
 180 #define pud_bad(pud)            (!is_kernel_addr(pud_val(pud)) \
 181                                  || (pud_val(pud) & PUD_BAD_BITS))
 182 #define pud_present(pud)        (pud_val(pud) != 0)
 183 #define pud_page_vaddr(pud)     (pud_val(pud) & ~PUD_MASKED_BITS)
 184
 185 extern struct page *pud_page(pud_t pud);
 186
 187 static inline pte_t pud_pte(pud_t pud)
 188 {
 189         return __pte(pud_val(pud));
 190 }
 191
 192 static inline pud_t pte_pud(pte_t pte)
 193 {
 194         return __pud(pte_val(pte));
 195 }
 196 #define pud_write(pud)          pte_write(pud_pte(pud))
 197 #define pgd_write(pgd)          pte_write(pgd_pte(pgd))
 198
 199 static inline void pgd_set(pgd_t *pgdp, unsigned long val)
 200 {
 201         *pgdp = __pgd(val);
 202 }
 203
 204 /*
 205  * Find an entry in a page-table-directory.  We combine the address region
 206  * (the high order N bits) and the pgd portion of the address.
 207  */
 208 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
 209
 210 #define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
 211
 212 #define pmd_offset(pudp,addr) \
 213   (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
 214
 215 #define pte_offset_kernel(dir,addr) \
 216   (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
 217
 218 #define pte_offset_map(dir,addr)        pte_offset_kernel((dir), (addr))
 219 #define pte_unmap(pte)                  do { } while(0)
 220
 221 /* to find an entry in a kernel page-table-directory */
 222 /* This now only contains the vmalloc pages */
 223 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 224 extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
 225                             pte_t *ptep, unsigned long pte, int huge);
 226
 227 /* Atomic PTE updates */
 228 static inline unsigned long pte_update(struct mm_struct *mm,
 229                                        unsigned long addr,
 230                                        pte_t *ptep, unsigned long clr,
 231                                        unsigned long set,
 232                                        int huge)
 233 {
 234 #ifdef PTE_ATOMIC_UPDATES
 235         unsigned long old, tmp;
 236
 237         __asm__ __volatile__(
 238         "1:     ldarx   %0,0,%3         # pte_update\n\
 239         andi.   %1,%0,%6\n\
 240         bne-    1b \n\
 241         andc    %1,%0,%4 \n\
 242         or      %1,%1,%7\n\
 243         stdcx.  %1,0,%3 \n\
 244         bne-    1b"
 245         : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
 246         : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY), "r" (set)
 247         : "cc" );
 248 #else
 249         unsigned long old = pte_val(*ptep);
 250         *ptep = __pte((old & ~clr) | set);
 251 #endif
 252         /* huge pages use the old page table lock */
 253         if (!huge)
 254                 assert_pte_locked(mm, addr);
 255
 256 #ifdef CONFIG_PPC_STD_MMU_64
 257         if (old & _PAGE_HASHPTE)
 258                 hpte_need_flush(mm, addr, ptep, old, huge);
 259 #endif
 260
 261         return old;
 262 }
 263
 264 static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
 265                                               unsigned long addr, pte_t *ptep)
 266 {
 267         unsigned long old;
 268
 269         if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
 270                 return 0;
 271         old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
 272         return (old & _PAGE_ACCESSED) != 0;
 273 }
 274 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 275 #define ptep_test_and_clear_young(__vma, __addr, __ptep)                   \
 276 ({                                                                         \
 277         int __r;                                                           \
 278         __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
 279         __r;                                                               \
 280 })
 281
 282 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 283 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 284                                       pte_t *ptep)
 285 {
 286
 287         if ((pte_val(*ptep) & _PAGE_RW) == 0)
 288                 return;
 289
 290         pte_update(mm, addr, ptep, _PAGE_RW, 0, 0);
 291 }
 292
 293 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
 294                                            unsigned long addr, pte_t *ptep)
 295 {
 296         if ((pte_val(*ptep) & _PAGE_RW) == 0)
 297                 return;
 298
 299         pte_update(mm, addr, ptep, _PAGE_RW, 0, 1);
 300 }
 301
 302 /*
 303  * We currently remove entries from the hashtable regardless of whether
 304  * the entry was young or dirty. The generic routines only flush if the
 305  * entry was young or dirty which is not good enough.
 306  *
 307  * We should be more intelligent about this but for the moment we override
 308  * these functions and force a tlb flush unconditionally
 309  */
 310 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
 311 #define ptep_clear_flush_young(__vma, __address, __ptep)                \
 312 ({                                                                      \
 313         int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
 314                                                   __ptep);              \
 315         __young;                                                        \
 316 })
 317
 318 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 319 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
 320                                        unsigned long addr, pte_t *ptep)
 321 {
 322         unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
 323         return __pte(old);
 324 }
 325
 326 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
 327                              pte_t * ptep)
 328 {
 329         pte_update(mm, addr, ptep, ~0UL, 0, 0);
 330 }
 331
 332
 333 /* Set the dirty and/or accessed bits atomically in a linux PTE, this
 334  * function doesn't need to flush the hash entry
 335  */
 336 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
 337 {
 338         unsigned long bits = pte_val(entry) &
 339                 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
 340
 341 #ifdef PTE_ATOMIC_UPDATES
 342         unsigned long old, tmp;
 343
 344         __asm__ __volatile__(
 345         "1:     ldarx   %0,0,%4\n\
 346                 andi.   %1,%0,%6\n\
 347                 bne-    1b \n\
 348                 or      %0,%3,%0\n\
 349                 stdcx.  %0,0,%4\n\
 350                 bne-    1b"
 351         :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
 352         :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
 353         :"cc");
 354 #else
 355         unsigned long old = pte_val(*ptep);
 356         *ptep = __pte(old | bits);
 357 #endif
 358 }
 359
 360 #define __HAVE_ARCH_PTE_SAME
 361 #define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
 362
 363 #define pte_ERROR(e) \
 364         pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 365 #define pmd_ERROR(e) \
 366         pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
 367 #define pgd_ERROR(e) \
 368         pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 369
 370 /* Encode and de-code a swap entry */
 371 #define MAX_SWAPFILES_CHECK() do { \
 372         BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
 373         /*                                                      \
 374          * Don't have overlapping bits with _PAGE_HPTEFLAGS     \
 375          * We filter HPTEFLAGS on set_pte.                      \
 376          */                                                     \
 377         BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
 378         } while (0)
 379 /*
 380  * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
 381  */
 382 #define SWP_TYPE_BITS 5
 383 #define __swp_type(x)           (((x).val >> _PAGE_BIT_SWAP_TYPE) \
 384                                 & ((1UL << SWP_TYPE_BITS) - 1))
 385 #define __swp_offset(x)         ((x).val >> PTE_RPN_SHIFT)
 386 #define __swp_entry(type, offset)       ((swp_entry_t) { \
 387                                         ((type) << _PAGE_BIT_SWAP_TYPE) \
 388                                         | ((offset) << PTE_RPN_SHIFT) })
 389
 390 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val((pte)) })
 391 #define __swp_entry_to_pte(x)           __pte((x).val)
 392
 393 void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
 394 void pgtable_cache_init(void);
 395 #endif /* __ASSEMBLY__ */
 396
 397 #endif /* _ASM_POWERPC_NOHASH_64_PGTABLE_H */