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1 /*
2 * OPAL API definitions.
3 *
4 * Copyright 2011-2015 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #ifndef __OPAL_API_H
13 #define __OPAL_API_H
14
15 /****** OPAL APIs ******/
16
17 /* Return codes */
18 #define OPAL_SUCCESS 0
19 #define OPAL_PARAMETER -1
20 #define OPAL_BUSY -2
21 #define OPAL_PARTIAL -3
22 #define OPAL_CONSTRAINED -4
23 #define OPAL_CLOSED -5
24 #define OPAL_HARDWARE -6
25 #define OPAL_UNSUPPORTED -7
26 #define OPAL_PERMISSION -8
27 #define OPAL_NO_MEM -9
28 #define OPAL_RESOURCE -10
29 #define OPAL_INTERNAL_ERROR -11
30 #define OPAL_BUSY_EVENT -12
31 #define OPAL_HARDWARE_FROZEN -13
32 #define OPAL_WRONG_STATE -14
33 #define OPAL_ASYNC_COMPLETION -15
34 #define OPAL_EMPTY -16
35 #define OPAL_I2C_TIMEOUT -17
36 #define OPAL_I2C_INVALID_CMD -18
37 #define OPAL_I2C_LBUS_PARITY -19
38 #define OPAL_I2C_BKEND_OVERRUN -20
39 #define OPAL_I2C_BKEND_ACCESS -21
40 #define OPAL_I2C_ARBT_LOST -22
41 #define OPAL_I2C_NACK_RCVD -23
42 #define OPAL_I2C_STOP_ERR -24
43 #define OPAL_XIVE_PROVISIONING -31
44 #define OPAL_XIVE_FREE_ACTIVE -32
45 #define OPAL_TIMEOUT -33
46
47 /* API Tokens (in r0) */
48 #define OPAL_INVALID_CALL -1
49 #define OPAL_TEST 0
50 #define OPAL_CONSOLE_WRITE 1
51 #define OPAL_CONSOLE_READ 2
52 #define OPAL_RTC_READ 3
53 #define OPAL_RTC_WRITE 4
54 #define OPAL_CEC_POWER_DOWN 5
55 #define OPAL_CEC_REBOOT 6
56 #define OPAL_READ_NVRAM 7
57 #define OPAL_WRITE_NVRAM 8
58 #define OPAL_HANDLE_INTERRUPT 9
59 #define OPAL_POLL_EVENTS 10
60 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
61 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
62 #define OPAL_PCI_CONFIG_READ_BYTE 13
63 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
64 #define OPAL_PCI_CONFIG_READ_WORD 15
65 #define OPAL_PCI_CONFIG_WRITE_BYTE 16
66 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
67 #define OPAL_PCI_CONFIG_WRITE_WORD 18
68 #define OPAL_SET_XIVE 19
69 #define OPAL_GET_XIVE 20
70 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
71 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
72 #define OPAL_PCI_EEH_FREEZE_STATUS 23
73 #define OPAL_PCI_SHPC 24
74 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
75 #define OPAL_PCI_EEH_FREEZE_CLEAR 26
76 #define OPAL_PCI_PHB_MMIO_ENABLE 27
77 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
78 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
79 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
80 #define OPAL_PCI_SET_PE 31
81 #define OPAL_PCI_SET_PELTV 32
82 #define OPAL_PCI_SET_MVE 33
83 #define OPAL_PCI_SET_MVE_ENABLE 34
84 #define OPAL_PCI_GET_XIVE_REISSUE 35
85 #define OPAL_PCI_SET_XIVE_REISSUE 36
86 #define OPAL_PCI_SET_XIVE_PE 37
87 #define OPAL_GET_XIVE_SOURCE 38
88 #define OPAL_GET_MSI_32 39
89 #define OPAL_GET_MSI_64 40
90 #define OPAL_START_CPU 41
91 #define OPAL_QUERY_CPU_STATUS 42
92 #define OPAL_WRITE_OPPANEL 43 /* unimplemented */
93 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
94 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
95 #define OPAL_PCI_RESET 49
96 #define OPAL_PCI_GET_HUB_DIAG_DATA 50
97 #define OPAL_PCI_GET_PHB_DIAG_DATA 51
98 #define OPAL_PCI_FENCE_PHB 52
99 #define OPAL_PCI_REINIT 53
100 #define OPAL_PCI_MASK_PE_ERROR 54
101 #define OPAL_SET_SLOT_LED_STATUS 55
102 #define OPAL_GET_EPOW_STATUS 56
103 #define OPAL_SET_SYSTEM_ATTENTION_LED 57
104 #define OPAL_RESERVED1 58
105 #define OPAL_RESERVED2 59
106 #define OPAL_PCI_NEXT_ERROR 60
107 #define OPAL_PCI_EEH_FREEZE_STATUS2 61
108 #define OPAL_PCI_POLL 62
109 #define OPAL_PCI_MSI_EOI 63
110 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
111 #define OPAL_XSCOM_READ 65
112 #define OPAL_XSCOM_WRITE 66
113 #define OPAL_LPC_READ 67
114 #define OPAL_LPC_WRITE 68
115 #define OPAL_RETURN_CPU 69
116 #define OPAL_REINIT_CPUS 70
117 #define OPAL_ELOG_READ 71
118 #define OPAL_ELOG_WRITE 72
119 #define OPAL_ELOG_ACK 73
120 #define OPAL_ELOG_RESEND 74
121 #define OPAL_ELOG_SIZE 75
122 #define OPAL_FLASH_VALIDATE 76
123 #define OPAL_FLASH_MANAGE 77
124 #define OPAL_FLASH_UPDATE 78
125 #define OPAL_RESYNC_TIMEBASE 79
126 #define OPAL_CHECK_TOKEN 80
127 #define OPAL_DUMP_INIT 81
128 #define OPAL_DUMP_INFO 82
129 #define OPAL_DUMP_READ 83
130 #define OPAL_DUMP_ACK 84
131 #define OPAL_GET_MSG 85
132 #define OPAL_CHECK_ASYNC_COMPLETION 86
133 #define OPAL_SYNC_HOST_REBOOT 87
134 #define OPAL_SENSOR_READ 88
135 #define OPAL_GET_PARAM 89
136 #define OPAL_SET_PARAM 90
137 #define OPAL_DUMP_RESEND 91
138 #define OPAL_ELOG_SEND 92 /* Deprecated */
139 #define OPAL_PCI_SET_PHB_CAPI_MODE 93
140 #define OPAL_DUMP_INFO2 94
141 #define OPAL_WRITE_OPPANEL_ASYNC 95
142 #define OPAL_PCI_ERR_INJECT 96
143 #define OPAL_PCI_EEH_FREEZE_SET 97
144 #define OPAL_HANDLE_HMI 98
145 #define OPAL_CONFIG_CPU_IDLE_STATE 99
146 #define OPAL_SLW_SET_REG 100
147 #define OPAL_REGISTER_DUMP_REGION 101
148 #define OPAL_UNREGISTER_DUMP_REGION 102
149 #define OPAL_WRITE_TPO 103
150 #define OPAL_READ_TPO 104
151 #define OPAL_GET_DPO_STATUS 105
152 #define OPAL_OLD_I2C_REQUEST 106 /* Deprecated */
153 #define OPAL_IPMI_SEND 107
154 #define OPAL_IPMI_RECV 108
155 #define OPAL_I2C_REQUEST 109
156 #define OPAL_FLASH_READ 110
157 #define OPAL_FLASH_WRITE 111
158 #define OPAL_FLASH_ERASE 112
159 #define OPAL_PRD_MSG 113
160 #define OPAL_LEDS_GET_INDICATOR 114
161 #define OPAL_LEDS_SET_INDICATOR 115
162 #define OPAL_CEC_REBOOT2 116
163 #define OPAL_CONSOLE_FLUSH 117
164 #define OPAL_GET_DEVICE_TREE 118
165 #define OPAL_PCI_GET_PRESENCE_STATE 119
166 #define OPAL_PCI_GET_POWER_STATE 120
167 #define OPAL_PCI_SET_POWER_STATE 121
168 #define OPAL_INT_GET_XIRR 122
169 #define OPAL_INT_SET_CPPR 123
170 #define OPAL_INT_EOI 124
171 #define OPAL_INT_SET_MFRR 125
172 #define OPAL_PCI_TCE_KILL 126
173 #define OPAL_NMMU_SET_PTCR 127
174 #define OPAL_XIVE_RESET 128
175 #define OPAL_XIVE_GET_IRQ_INFO 129
176 #define OPAL_XIVE_GET_IRQ_CONFIG 130
177 #define OPAL_XIVE_SET_IRQ_CONFIG 131
178 #define OPAL_XIVE_GET_QUEUE_INFO 132
179 #define OPAL_XIVE_SET_QUEUE_INFO 133
180 #define OPAL_XIVE_DONATE_PAGE 134
181 #define OPAL_XIVE_ALLOCATE_VP_BLOCK 135
182 #define OPAL_XIVE_FREE_VP_BLOCK 136
183 #define OPAL_XIVE_GET_VP_INFO 137
184 #define OPAL_XIVE_SET_VP_INFO 138
185 #define OPAL_XIVE_ALLOCATE_IRQ 139
186 #define OPAL_XIVE_FREE_IRQ 140
187 #define OPAL_XIVE_SYNC 141
188 #define OPAL_XIVE_DUMP 142
189 #define OPAL_XIVE_GET_QUEUE_STATE 143
190 #define OPAL_XIVE_SET_QUEUE_STATE 144
191 #define OPAL_SIGNAL_SYSTEM_RESET 145
192 #define OPAL_NPU_INIT_CONTEXT 146
193 #define OPAL_NPU_DESTROY_CONTEXT 147
194 #define OPAL_NPU_MAP_LPAR 148
195 #define OPAL_IMC_COUNTERS_INIT 149
196 #define OPAL_IMC_COUNTERS_START 150
197 #define OPAL_IMC_COUNTERS_STOP 151
198 #define OPAL_GET_POWERCAP 152
199 #define OPAL_SET_POWERCAP 153
200 #define OPAL_GET_POWER_SHIFT_RATIO 154
201 #define OPAL_SET_POWER_SHIFT_RATIO 155
202 #define OPAL_SENSOR_GROUP_CLEAR 156
203 #define OPAL_PCI_SET_P2P 157
204 #define OPAL_QUIESCE 158
205 #define OPAL_NPU_SPA_SETUP 159
206 #define OPAL_NPU_SPA_CLEAR_CACHE 160
207 #define OPAL_NPU_TL_SET 161
208 #define OPAL_SENSOR_READ_U64 162
209 #define OPAL_SENSOR_GROUP_ENABLE 163
210 #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 164
211 #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 165
212 #define OPAL_HANDLE_HMI2 166
213 #define OPAL_NX_COPROC_INIT 167
214 #define OPAL_XIVE_GET_VP_STATE 170
215 #define OPAL_LAST 170
216
217 #define QUIESCE_HOLD 1 /* Spin all calls at entry */
218 #define QUIESCE_REJECT 2 /* Fail all calls with OPAL_BUSY */
219 #define QUIESCE_LOCK_BREAK 3 /* Set to ignore locks. */
220 #define QUIESCE_RESUME 4 /* Un-quiesce */
221 #define QUIESCE_RESUME_FAST_REBOOT 5 /* Un-quiesce, fast reboot */
222
223 /* Device tree flags */
224
225 /*
226 * Flags set in power-mgmt nodes in device tree describing
227 * idle states that are supported in the platform.
228 */
229
230 #define OPAL_PM_TIMEBASE_STOP 0x00000002
231 #define OPAL_PM_LOSE_HYP_CONTEXT 0x00002000
232 #define OPAL_PM_LOSE_FULL_CONTEXT 0x00004000
233 #define OPAL_PM_NAP_ENABLED 0x00010000
234 #define OPAL_PM_SLEEP_ENABLED 0x00020000
235 #define OPAL_PM_WINKLE_ENABLED 0x00040000
236 #define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */
237 #define OPAL_PM_STOP_INST_FAST 0x00100000
238 #define OPAL_PM_STOP_INST_DEEP 0x00200000
239
240 /*
241 * OPAL_CONFIG_CPU_IDLE_STATE parameters
242 */
243 #define OPAL_CONFIG_IDLE_FASTSLEEP 1
244 #define OPAL_CONFIG_IDLE_UNDO 0
245 #define OPAL_CONFIG_IDLE_APPLY 1
246
247 #ifndef __ASSEMBLY__
248
249 /* Other enums */
250 enum OpalFreezeState {
251 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
252 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
253 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
254 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
255 OPAL_EEH_STOPPED_RESET = 4,
256 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
257 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
258 };
259
260 enum OpalEehFreezeActionToken {
261 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
262 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
263 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
264
265 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
266 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2,
267 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3
268 };
269
270 enum OpalPciStatusToken {
271 OPAL_EEH_NO_ERROR = 0,
272 OPAL_EEH_IOC_ERROR = 1,
273 OPAL_EEH_PHB_ERROR = 2,
274 OPAL_EEH_PE_ERROR = 3,
275 OPAL_EEH_PE_MMIO_ERROR = 4,
276 OPAL_EEH_PE_DMA_ERROR = 5
277 };
278
279 enum OpalPciErrorSeverity {
280 OPAL_EEH_SEV_NO_ERROR = 0,
281 OPAL_EEH_SEV_IOC_DEAD = 1,
282 OPAL_EEH_SEV_PHB_DEAD = 2,
283 OPAL_EEH_SEV_PHB_FENCED = 3,
284 OPAL_EEH_SEV_PE_ER = 4,
285 OPAL_EEH_SEV_INF = 5
286 };
287
288 enum OpalErrinjectType {
289 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0,
290 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1,
291 };
292
293 enum OpalErrinjectFunc {
294 /* IOA bus specific errors */
295 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0,
296 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1,
297 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2,
298 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3,
299 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4,
300 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5,
301 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6,
302 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7,
303 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8,
304 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9,
305 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10,
306 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11,
307 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12,
308 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13,
309 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14,
310 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15,
311 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16,
312 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17,
313 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18,
314 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19,
315 };
316
317 enum OpalMmioWindowType {
318 OPAL_M32_WINDOW_TYPE = 1,
319 OPAL_M64_WINDOW_TYPE = 2,
320 OPAL_IO_WINDOW_TYPE = 3
321 };
322
323 enum OpalExceptionHandler {
324 OPAL_MACHINE_CHECK_HANDLER = 1,
325 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
326 OPAL_SOFTPATCH_HANDLER = 3
327 };
328
329 enum OpalPendingState {
330 OPAL_EVENT_OPAL_INTERNAL = 0x1,
331 OPAL_EVENT_NVRAM = 0x2,
332 OPAL_EVENT_RTC = 0x4,
333 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
334 OPAL_EVENT_CONSOLE_INPUT = 0x10,
335 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
336 OPAL_EVENT_ERROR_LOG = 0x40,
337 OPAL_EVENT_EPOW = 0x80,
338 OPAL_EVENT_LED_STATUS = 0x100,
339 OPAL_EVENT_PCI_ERROR = 0x200,
340 OPAL_EVENT_DUMP_AVAIL = 0x400,
341 OPAL_EVENT_MSG_PENDING = 0x800,
342 };
343
344 enum OpalThreadStatus {
345 OPAL_THREAD_INACTIVE = 0x0,
346 OPAL_THREAD_STARTED = 0x1,
347 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
348 };
349
350 enum OpalPciBusCompare {
351 OpalPciBusAny = 0, /* Any bus number match */
352 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
353 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
354 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
355 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
356 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
357 OpalPciBusAll = 7, /* Match bus number exactly */
358 };
359
360 enum OpalDeviceCompare {
361 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
362 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
363 };
364
365 enum OpalFuncCompare {
366 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
367 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
368 };
369
370 enum OpalPeAction {
371 OPAL_UNMAP_PE = 0,
372 OPAL_MAP_PE = 1
373 };
374
375 enum OpalPeltvAction {
376 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
377 OPAL_ADD_PE_TO_DOMAIN = 1
378 };
379
380 enum OpalMveEnableAction {
381 OPAL_DISABLE_MVE = 0,
382 OPAL_ENABLE_MVE = 1
383 };
384
385 enum OpalM64Action {
386 OPAL_DISABLE_M64 = 0,
387 OPAL_ENABLE_M64_SPLIT = 1,
388 OPAL_ENABLE_M64_NON_SPLIT = 2
389 };
390
391 enum OpalPciResetScope {
392 OPAL_RESET_PHB_COMPLETE = 1,
393 OPAL_RESET_PCI_LINK = 2,
394 OPAL_RESET_PHB_ERROR = 3,
395 OPAL_RESET_PCI_HOT = 4,
396 OPAL_RESET_PCI_FUNDAMENTAL = 5,
397 OPAL_RESET_PCI_IODA_TABLE = 6
398 };
399
400 enum OpalPciReinitScope {
401 /*
402 * Note: we chose values that do not overlap
403 * OpalPciResetScope as OPAL v2 used the same
404 * enum for both
405 */
406 OPAL_REINIT_PCI_DEV = 1000
407 };
408
409 enum OpalPciResetState {
410 OPAL_DEASSERT_RESET = 0,
411 OPAL_ASSERT_RESET = 1
412 };
413
414 enum OpalPciSlotPresence {
415 OPAL_PCI_SLOT_EMPTY = 0,
416 OPAL_PCI_SLOT_PRESENT = 1
417 };
418
419 enum OpalPciSlotPower {
420 OPAL_PCI_SLOT_POWER_OFF = 0,
421 OPAL_PCI_SLOT_POWER_ON = 1,
422 OPAL_PCI_SLOT_OFFLINE = 2,
423 OPAL_PCI_SLOT_ONLINE = 3
424 };
425
426 enum OpalSlotLedType {
427 OPAL_SLOT_LED_TYPE_ID = 0, /* IDENTIFY LED */
428 OPAL_SLOT_LED_TYPE_FAULT = 1, /* FAULT LED */
429 OPAL_SLOT_LED_TYPE_ATTN = 2, /* System Attention LED */
430 OPAL_SLOT_LED_TYPE_MAX = 3
431 };
432
433 enum OpalSlotLedState {
434 OPAL_SLOT_LED_STATE_OFF = 0, /* LED is OFF */
435 OPAL_SLOT_LED_STATE_ON = 1 /* LED is ON */
436 };
437
438 /*
439 * Address cycle types for LPC accesses. These also correspond
440 * to the content of the first cell of the "reg" property for
441 * device nodes on the LPC bus
442 */
443 enum OpalLPCAddressType {
444 OPAL_LPC_MEM = 0,
445 OPAL_LPC_IO = 1,
446 OPAL_LPC_FW = 2,
447 };
448
449 enum opal_msg_type {
450 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
451 * additional params function-specific
452 */
453 OPAL_MSG_MEM_ERR = 1,
454 OPAL_MSG_EPOW = 2,
455 OPAL_MSG_SHUTDOWN = 3, /* params[0] = 1 reboot, 0 shutdown */
456 OPAL_MSG_HMI_EVT = 4,
457 OPAL_MSG_DPO = 5,
458 OPAL_MSG_PRD = 6,
459 OPAL_MSG_OCC = 7,
460 OPAL_MSG_TYPE_MAX,
461 };
462
463 struct opal_msg {
464 __be32 msg_type;
465 __be32 reserved;
466 __be64 params[8];
467 };
468
469 /* System parameter permission */
470 enum OpalSysparamPerm {
471 OPAL_SYSPARAM_READ = 0x1,
472 OPAL_SYSPARAM_WRITE = 0x2,
473 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
474 };
475
476 enum {
477 OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
478 };
479
480 struct opal_ipmi_msg {
481 uint8_t version;
482 uint8_t netfn;
483 uint8_t cmd;
484 uint8_t data[];
485 };
486
487 /* FSP memory errors handling */
488 enum OpalMemErr_Version {
489 OpalMemErr_V1 = 1,
490 };
491
492 enum OpalMemErrType {
493 OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
494 OPAL_MEM_ERR_TYPE_DYN_DALLOC,
495 };
496
497 /* Memory Reilience error type */
498 enum OpalMemErr_ResilErrType {
499 OPAL_MEM_RESILIENCE_CE = 0,
500 OPAL_MEM_RESILIENCE_UE,
501 OPAL_MEM_RESILIENCE_UE_SCRUB,
502 };
503
504 /* Dynamic Memory Deallocation type */
505 enum OpalMemErr_DynErrType {
506 OPAL_MEM_DYNAMIC_DEALLOC = 0,
507 };
508
509 struct OpalMemoryErrorData {
510 enum OpalMemErr_Version version:8; /* 0x00 */
511 enum OpalMemErrType type:8; /* 0x01 */
512 __be16 flags; /* 0x02 */
513 uint8_t reserved_1[4]; /* 0x04 */
514
515 union {
516 /* Memory Resilience corrected/uncorrected error info */
517 struct {
518 enum OpalMemErr_ResilErrType resil_err_type:8;
519 uint8_t reserved_1[7];
520 __be64 physical_address_start;
521 __be64 physical_address_end;
522 } resilience;
523 /* Dynamic memory deallocation error info */
524 struct {
525 enum OpalMemErr_DynErrType dyn_err_type:8;
526 uint8_t reserved_1[7];
527 __be64 physical_address_start;
528 __be64 physical_address_end;
529 } dyn_dealloc;
530 } u;
531 };
532
533 /* HMI interrupt event */
534 enum OpalHMI_Version {
535 OpalHMIEvt_V1 = 1,
536 OpalHMIEvt_V2 = 2,
537 };
538
539 enum OpalHMI_Severity {
540 OpalHMI_SEV_NO_ERROR = 0,
541 OpalHMI_SEV_WARNING = 1,
542 OpalHMI_SEV_ERROR_SYNC = 2,
543 OpalHMI_SEV_FATAL = 3,
544 };
545
546 enum OpalHMI_Disposition {
547 OpalHMI_DISPOSITION_RECOVERED = 0,
548 OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
549 };
550
551 enum OpalHMI_ErrType {
552 OpalHMI_ERROR_MALFUNC_ALERT = 0,
553 OpalHMI_ERROR_PROC_RECOV_DONE,
554 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
555 OpalHMI_ERROR_PROC_RECOV_MASKED,
556 OpalHMI_ERROR_TFAC,
557 OpalHMI_ERROR_TFMR_PARITY,
558 OpalHMI_ERROR_HA_OVERFLOW_WARN,
559 OpalHMI_ERROR_XSCOM_FAIL,
560 OpalHMI_ERROR_XSCOM_DONE,
561 OpalHMI_ERROR_SCOM_FIR,
562 OpalHMI_ERROR_DEBUG_TRIG_FIR,
563 OpalHMI_ERROR_HYP_RESOURCE,
564 OpalHMI_ERROR_CAPP_RECOVERY,
565 };
566
567 enum OpalHMI_XstopType {
568 CHECKSTOP_TYPE_UNKNOWN = 0,
569 CHECKSTOP_TYPE_CORE = 1,
570 CHECKSTOP_TYPE_NX = 2,
571 };
572
573 enum OpalHMI_CoreXstopReason {
574 CORE_CHECKSTOP_IFU_REGFILE = 0x00000001,
575 CORE_CHECKSTOP_IFU_LOGIC = 0x00000002,
576 CORE_CHECKSTOP_PC_DURING_RECOV = 0x00000004,
577 CORE_CHECKSTOP_ISU_REGFILE = 0x00000008,
578 CORE_CHECKSTOP_ISU_LOGIC = 0x00000010,
579 CORE_CHECKSTOP_FXU_LOGIC = 0x00000020,
580 CORE_CHECKSTOP_VSU_LOGIC = 0x00000040,
581 CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 0x00000080,
582 CORE_CHECKSTOP_LSU_REGFILE = 0x00000100,
583 CORE_CHECKSTOP_PC_FWD_PROGRESS = 0x00000200,
584 CORE_CHECKSTOP_LSU_LOGIC = 0x00000400,
585 CORE_CHECKSTOP_PC_LOGIC = 0x00000800,
586 CORE_CHECKSTOP_PC_HYP_RESOURCE = 0x00001000,
587 CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x00002000,
588 CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000,
589 CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000,
590 CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000,
591 };
592
593 enum OpalHMI_NestAccelXstopReason {
594 NX_CHECKSTOP_SHM_INVAL_STATE_ERR = 0x00000001,
595 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 0x00000002,
596 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 0x00000004,
597 NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 0x00000008,
598 NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 0x00000010,
599 NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 0x00000020,
600 NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 0x00000040,
601 NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 0x00000080,
602 NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 0x00000100,
603 NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 0x00000200,
604 NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 0x00000400,
605 NX_CHECKSTOP_DMA_CRB_UE = 0x00000800,
606 NX_CHECKSTOP_DMA_CRB_SUE = 0x00001000,
607 NX_CHECKSTOP_PBI_ISN_UE = 0x00002000,
608 };
609
610 struct OpalHMIEvent {
611 uint8_t version; /* 0x00 */
612 uint8_t severity; /* 0x01 */
613 uint8_t type; /* 0x02 */
614 uint8_t disposition; /* 0x03 */
615 uint8_t reserved_1[4]; /* 0x04 */
616
617 __be64 hmer;
618 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
619 __be64 tfmr;
620
621 /* version 2 and later */
622 union {
623 /*
624 * checkstop info (Core/NX).
625 * Valid for OpalHMI_ERROR_MALFUNC_ALERT.
626 */
627 struct {
628 uint8_t xstop_type; /* enum OpalHMI_XstopType */
629 uint8_t reserved_1[3];
630 __be32 xstop_reason;
631 union {
632 __be32 pir; /* for CHECKSTOP_TYPE_CORE */
633 __be32 chip_id; /* for CHECKSTOP_TYPE_NX */
634 } u;
635 } xstop_error;
636 } u;
637 };
638
639 /* OPAL_HANDLE_HMI2 out_flags */
640 enum {
641 OPAL_HMI_FLAGS_TB_RESYNC = (1ull << 0), /* Timebase has been resynced */
642 OPAL_HMI_FLAGS_DEC_LOST = (1ull << 1), /* DEC lost, needs to be reprogrammed */
643 OPAL_HMI_FLAGS_HDEC_LOST = (1ull << 2), /* HDEC lost, needs to be reprogrammed */
644 OPAL_HMI_FLAGS_TOD_TB_FAIL = (1ull << 3), /* TOD/TB recovery failed. */
645 OPAL_HMI_FLAGS_NEW_EVENT = (1ull << 63), /* An event has been created */
646 };
647
648 enum {
649 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
650 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
651 OPAL_P7IOC_DIAG_TYPE_BI = 2,
652 OPAL_P7IOC_DIAG_TYPE_CI = 3,
653 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
654 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
655 OPAL_P7IOC_DIAG_TYPE_LAST = 6
656 };
657
658 struct OpalIoP7IOCErrorData {
659 __be16 type;
660
661 /* GEM */
662 __be64 gemXfir;
663 __be64 gemRfir;
664 __be64 gemRirqfir;
665 __be64 gemMask;
666 __be64 gemRwof;
667
668 /* LEM */
669 __be64 lemFir;
670 __be64 lemErrMask;
671 __be64 lemAction0;
672 __be64 lemAction1;
673 __be64 lemWof;
674
675 union {
676 struct OpalIoP7IOCRgcErrorData {
677 __be64 rgcStatus; /* 3E1C10 */
678 __be64 rgcLdcp; /* 3E1C18 */
679 }rgc;
680 struct OpalIoP7IOCBiErrorData {
681 __be64 biLdcp0; /* 3C0100, 3C0118 */
682 __be64 biLdcp1; /* 3C0108, 3C0120 */
683 __be64 biLdcp2; /* 3C0110, 3C0128 */
684 __be64 biFenceStatus; /* 3C0130, 3C0130 */
685
686 uint8_t biDownbound; /* BI Downbound or Upbound */
687 }bi;
688 struct OpalIoP7IOCCiErrorData {
689 __be64 ciPortStatus; /* 3Dn008 */
690 __be64 ciPortLdcp; /* 3Dn010 */
691
692 uint8_t ciPort; /* Index of CI port: 0/1 */
693 }ci;
694 };
695 };
696
697 /**
698 * This structure defines the overlay which will be used to store PHB error
699 * data upon request.
700 */
701 enum {
702 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
703 };
704
705 enum {
706 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
707 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2,
708 OPAL_PHB_ERROR_DATA_TYPE_PHB4 = 3
709 };
710
711 enum {
712 OPAL_P7IOC_NUM_PEST_REGS = 128,
713 OPAL_PHB3_NUM_PEST_REGS = 256,
714 OPAL_PHB4_NUM_PEST_REGS = 512
715 };
716
717 struct OpalIoPhbErrorCommon {
718 __be32 version;
719 __be32 ioType;
720 __be32 len;
721 };
722
723 struct OpalIoP7IOCPhbErrorData {
724 struct OpalIoPhbErrorCommon common;
725
726 __be32 brdgCtl;
727
728 // P7IOC utl regs
729 __be32 portStatusReg;
730 __be32 rootCmplxStatus;
731 __be32 busAgentStatus;
732
733 // P7IOC cfg regs
734 __be32 deviceStatus;
735 __be32 slotStatus;
736 __be32 linkStatus;
737 __be32 devCmdStatus;
738 __be32 devSecStatus;
739
740 // cfg AER regs
741 __be32 rootErrorStatus;
742 __be32 uncorrErrorStatus;
743 __be32 corrErrorStatus;
744 __be32 tlpHdr1;
745 __be32 tlpHdr2;
746 __be32 tlpHdr3;
747 __be32 tlpHdr4;
748 __be32 sourceId;
749
750 __be32 rsv3;
751
752 // Record data about the call to allocate a buffer.
753 __be64 errorClass;
754 __be64 correlator;
755
756 //P7IOC MMIO Error Regs
757 __be64 p7iocPlssr; // n120
758 __be64 p7iocCsr; // n110
759 __be64 lemFir; // nC00
760 __be64 lemErrorMask; // nC18
761 __be64 lemWOF; // nC40
762 __be64 phbErrorStatus; // nC80
763 __be64 phbFirstErrorStatus; // nC88
764 __be64 phbErrorLog0; // nCC0
765 __be64 phbErrorLog1; // nCC8
766 __be64 mmioErrorStatus; // nD00
767 __be64 mmioFirstErrorStatus; // nD08
768 __be64 mmioErrorLog0; // nD40
769 __be64 mmioErrorLog1; // nD48
770 __be64 dma0ErrorStatus; // nD80
771 __be64 dma0FirstErrorStatus; // nD88
772 __be64 dma0ErrorLog0; // nDC0
773 __be64 dma0ErrorLog1; // nDC8
774 __be64 dma1ErrorStatus; // nE00
775 __be64 dma1FirstErrorStatus; // nE08
776 __be64 dma1ErrorLog0; // nE40
777 __be64 dma1ErrorLog1; // nE48
778 __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
779 __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
780 };
781
782 struct OpalIoPhb3ErrorData {
783 struct OpalIoPhbErrorCommon common;
784
785 __be32 brdgCtl;
786
787 /* PHB3 UTL regs */
788 __be32 portStatusReg;
789 __be32 rootCmplxStatus;
790 __be32 busAgentStatus;
791
792 /* PHB3 cfg regs */
793 __be32 deviceStatus;
794 __be32 slotStatus;
795 __be32 linkStatus;
796 __be32 devCmdStatus;
797 __be32 devSecStatus;
798
799 /* cfg AER regs */
800 __be32 rootErrorStatus;
801 __be32 uncorrErrorStatus;
802 __be32 corrErrorStatus;
803 __be32 tlpHdr1;
804 __be32 tlpHdr2;
805 __be32 tlpHdr3;
806 __be32 tlpHdr4;
807 __be32 sourceId;
808
809 __be32 rsv3;
810
811 /* Record data about the call to allocate a buffer */
812 __be64 errorClass;
813 __be64 correlator;
814
815 /* PHB3 MMIO Error Regs */
816 __be64 nFir; /* 000 */
817 __be64 nFirMask; /* 003 */
818 __be64 nFirWOF; /* 008 */
819 __be64 phbPlssr; /* 120 */
820 __be64 phbCsr; /* 110 */
821 __be64 lemFir; /* C00 */
822 __be64 lemErrorMask; /* C18 */
823 __be64 lemWOF; /* C40 */
824 __be64 phbErrorStatus; /* C80 */
825 __be64 phbFirstErrorStatus; /* C88 */
826 __be64 phbErrorLog0; /* CC0 */
827 __be64 phbErrorLog1; /* CC8 */
828 __be64 mmioErrorStatus; /* D00 */
829 __be64 mmioFirstErrorStatus; /* D08 */
830 __be64 mmioErrorLog0; /* D40 */
831 __be64 mmioErrorLog1; /* D48 */
832 __be64 dma0ErrorStatus; /* D80 */
833 __be64 dma0FirstErrorStatus; /* D88 */
834 __be64 dma0ErrorLog0; /* DC0 */
835 __be64 dma0ErrorLog1; /* DC8 */
836 __be64 dma1ErrorStatus; /* E00 */
837 __be64 dma1FirstErrorStatus; /* E08 */
838 __be64 dma1ErrorLog0; /* E40 */
839 __be64 dma1ErrorLog1; /* E48 */
840 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
841 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
842 };
843
844 struct OpalIoPhb4ErrorData {
845 struct OpalIoPhbErrorCommon common;
846
847 __be32 brdgCtl;
848
849 /* PHB4 cfg regs */
850 __be32 deviceStatus;
851 __be32 slotStatus;
852 __be32 linkStatus;
853 __be32 devCmdStatus;
854 __be32 devSecStatus;
855
856 /* cfg AER regs */
857 __be32 rootErrorStatus;
858 __be32 uncorrErrorStatus;
859 __be32 corrErrorStatus;
860 __be32 tlpHdr1;
861 __be32 tlpHdr2;
862 __be32 tlpHdr3;
863 __be32 tlpHdr4;
864 __be32 sourceId;
865
866 /* PHB4 ETU Error Regs */
867 __be64 nFir; /* 000 */
868 __be64 nFirMask; /* 003 */
869 __be64 nFirWOF; /* 008 */
870 __be64 phbPlssr; /* 120 */
871 __be64 phbCsr; /* 110 */
872 __be64 lemFir; /* C00 */
873 __be64 lemErrorMask; /* C18 */
874 __be64 lemWOF; /* C40 */
875 __be64 phbErrorStatus; /* C80 */
876 __be64 phbFirstErrorStatus; /* C88 */
877 __be64 phbErrorLog0; /* CC0 */
878 __be64 phbErrorLog1; /* CC8 */
879 __be64 phbTxeErrorStatus; /* D00 */
880 __be64 phbTxeFirstErrorStatus; /* D08 */
881 __be64 phbTxeErrorLog0; /* D40 */
882 __be64 phbTxeErrorLog1; /* D48 */
883 __be64 phbRxeArbErrorStatus; /* D80 */
884 __be64 phbRxeArbFirstErrorStatus; /* D88 */
885 __be64 phbRxeArbErrorLog0; /* DC0 */
886 __be64 phbRxeArbErrorLog1; /* DC8 */
887 __be64 phbRxeMrgErrorStatus; /* E00 */
888 __be64 phbRxeMrgFirstErrorStatus; /* E08 */
889 __be64 phbRxeMrgErrorLog0; /* E40 */
890 __be64 phbRxeMrgErrorLog1; /* E48 */
891 __be64 phbRxeTceErrorStatus; /* E80 */
892 __be64 phbRxeTceFirstErrorStatus; /* E88 */
893 __be64 phbRxeTceErrorLog0; /* EC0 */
894 __be64 phbRxeTceErrorLog1; /* EC8 */
895
896 /* PHB4 REGB Error Regs */
897 __be64 phbPblErrorStatus; /* 1900 */
898 __be64 phbPblFirstErrorStatus; /* 1908 */
899 __be64 phbPblErrorLog0; /* 1940 */
900 __be64 phbPblErrorLog1; /* 1948 */
901 __be64 phbPcieDlpErrorLog1; /* 1AA0 */
902 __be64 phbPcieDlpErrorLog2; /* 1AA8 */
903 __be64 phbPcieDlpErrorStatus; /* 1AB0 */
904 __be64 phbRegbErrorStatus; /* 1C00 */
905 __be64 phbRegbFirstErrorStatus; /* 1C08 */
906 __be64 phbRegbErrorLog0; /* 1C40 */
907 __be64 phbRegbErrorLog1; /* 1C48 */
908
909 __be64 pestA[OPAL_PHB4_NUM_PEST_REGS];
910 __be64 pestB[OPAL_PHB4_NUM_PEST_REGS];
911 };
912
913 enum {
914 OPAL_REINIT_CPUS_HILE_BE = (1 << 0),
915 OPAL_REINIT_CPUS_HILE_LE = (1 << 1),
916
917 /* These two define the base MMU mode of the host on P9
918 *
919 * On P9 Nimbus DD2.0 and Cumlus (and later), KVM can still
920 * create hash guests in "radix" mode with care (full core
921 * switch only).
922 */
923 OPAL_REINIT_CPUS_MMU_HASH = (1 << 2),
924 OPAL_REINIT_CPUS_MMU_RADIX = (1 << 3),
925
926 OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED = (1 << 4),
927 };
928
929 typedef struct oppanel_line {
930 __be64 line;
931 __be64 line_len;
932 } oppanel_line_t;
933
934 enum opal_prd_msg_type {
935 OPAL_PRD_MSG_TYPE_INIT = 0, /* HBRT --> OPAL */
936 OPAL_PRD_MSG_TYPE_FINI, /* HBRT/kernel --> OPAL */
937 OPAL_PRD_MSG_TYPE_ATTN, /* HBRT <-- OPAL */
938 OPAL_PRD_MSG_TYPE_ATTN_ACK, /* HBRT --> OPAL */
939 OPAL_PRD_MSG_TYPE_OCC_ERROR, /* HBRT <-- OPAL */
940 OPAL_PRD_MSG_TYPE_OCC_RESET, /* HBRT <-- OPAL */
941 };
942
943 struct opal_prd_msg_header {
944 uint8_t type;
945 uint8_t pad[1];
946 __be16 size;
947 };
948
949 struct opal_prd_msg;
950
951 #define OCC_RESET 0
952 #define OCC_LOAD 1
953 #define OCC_THROTTLE 2
954 #define OCC_MAX_THROTTLE_STATUS 5
955
956 struct opal_occ_msg {
957 __be64 type;
958 __be64 chip;
959 __be64 throttle_status;
960 };
961
962 /*
963 * SG entries
964 *
965 * WARNING: The current implementation requires each entry
966 * to represent a block that is 4k aligned *and* each block
967 * size except the last one in the list to be as well.
968 */
969 struct opal_sg_entry {
970 __be64 data;
971 __be64 length;
972 };
973
974 /*
975 * Candidate image SG list.
976 *
977 * length = VER | length
978 */
979 struct opal_sg_list {
980 __be64 length;
981 __be64 next;
982 struct opal_sg_entry entry[];
983 };
984
985 /*
986 * Dump region ID range usable by the OS
987 */
988 #define OPAL_DUMP_REGION_HOST_START 0x80
989 #define OPAL_DUMP_REGION_LOG_BUF 0x80
990 #define OPAL_DUMP_REGION_HOST_END 0xFF
991
992 /* CAPI modes for PHB */
993 enum {
994 OPAL_PHB_CAPI_MODE_PCIE = 0,
995 OPAL_PHB_CAPI_MODE_CAPI = 1,
996 OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2,
997 OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
998 OPAL_PHB_CAPI_MODE_DMA = 4,
999 OPAL_PHB_CAPI_MODE_DMA_TVT1 = 5,
1000 };
1001
1002 /* OPAL I2C request */
1003 struct opal_i2c_request {
1004 uint8_t type;
1005 #define OPAL_I2C_RAW_READ 0
1006 #define OPAL_I2C_RAW_WRITE 1
1007 #define OPAL_I2C_SM_READ 2
1008 #define OPAL_I2C_SM_WRITE 3
1009 uint8_t flags;
1010 #define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */
1011 uint8_t subaddr_sz; /* Max 4 */
1012 uint8_t reserved;
1013 __be16 addr; /* 7 or 10 bit address */
1014 __be16 reserved2;
1015 __be32 subaddr; /* Sub-address if any */
1016 __be32 size; /* Data size */
1017 __be64 buffer_ra; /* Buffer real address */
1018 };
1019
1020 /*
1021 * EPOW status sharing (OPAL and the host)
1022 *
1023 * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX
1024 * with individual elements being 16 bits wide to fetch the system
1025 * wide EPOW status. Each element in the buffer will contain the
1026 * EPOW status in it's bit representation for a particular EPOW sub
1027 * class as defined here. So multiple detailed EPOW status bits
1028 * specific for any sub class can be represented in a single buffer
1029 * element as it's bit representation.
1030 */
1031
1032 /* System EPOW type */
1033 enum OpalSysEpow {
1034 OPAL_SYSEPOW_POWER = 0, /* Power EPOW */
1035 OPAL_SYSEPOW_TEMP = 1, /* Temperature EPOW */
1036 OPAL_SYSEPOW_COOLING = 2, /* Cooling EPOW */
1037 OPAL_SYSEPOW_MAX = 3, /* Max EPOW categories */
1038 };
1039
1040 /* Power EPOW */
1041 enum OpalSysPower {
1042 OPAL_SYSPOWER_UPS = 0x0001, /* System on UPS power */
1043 OPAL_SYSPOWER_CHNG = 0x0002, /* System power config change */
1044 OPAL_SYSPOWER_FAIL = 0x0004, /* System impending power failure */
1045 OPAL_SYSPOWER_INCL = 0x0008, /* System incomplete power */
1046 };
1047
1048 /* Temperature EPOW */
1049 enum OpalSysTemp {
1050 OPAL_SYSTEMP_AMB = 0x0001, /* System over ambient temperature */
1051 OPAL_SYSTEMP_INT = 0x0002, /* System over internal temperature */
1052 OPAL_SYSTEMP_HMD = 0x0004, /* System over ambient humidity */
1053 };
1054
1055 /* Cooling EPOW */
1056 enum OpalSysCooling {
1057 OPAL_SYSCOOL_INSF = 0x0001, /* System insufficient cooling */
1058 };
1059
1060 /* Argument to OPAL_CEC_REBOOT2() */
1061 enum {
1062 OPAL_REBOOT_NORMAL = 0,
1063 OPAL_REBOOT_PLATFORM_ERROR = 1,
1064 OPAL_REBOOT_FULL_IPL = 2,
1065 };
1066
1067 /* Argument to OPAL_PCI_TCE_KILL */
1068 enum {
1069 OPAL_PCI_TCE_KILL_PAGES,
1070 OPAL_PCI_TCE_KILL_PE,
1071 OPAL_PCI_TCE_KILL_ALL,
1072 };
1073
1074 /* The xive operation mode indicates the active "API" and
1075 * corresponds to the "mode" parameter of the opal_xive_reset()
1076 * call
1077 */
1078 enum {
1079 OPAL_XIVE_MODE_EMU = 0,
1080 OPAL_XIVE_MODE_EXPL = 1,
1081 };
1082
1083 /* Flags for OPAL_XIVE_GET_IRQ_INFO */
1084 enum {
1085 OPAL_XIVE_IRQ_TRIGGER_PAGE = 0x00000001,
1086 OPAL_XIVE_IRQ_STORE_EOI = 0x00000002,
1087 OPAL_XIVE_IRQ_LSI = 0x00000004,
1088 OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008,
1089 OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010,
1090 OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020,
1091 };
1092
1093 /* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */
1094 enum {
1095 OPAL_XIVE_EQ_ENABLED = 0x00000001,
1096 OPAL_XIVE_EQ_ALWAYS_NOTIFY = 0x00000002,
1097 OPAL_XIVE_EQ_ESCALATE = 0x00000004,
1098 };
1099
1100 /* Flags for OPAL_XIVE_GET/SET_VP_INFO */
1101 enum {
1102 OPAL_XIVE_VP_ENABLED = 0x00000001,
1103 OPAL_XIVE_VP_SINGLE_ESCALATION = 0x00000002,
1104 };
1105
1106 /* "Any chip" replacement for chip ID for allocation functions */
1107 enum {
1108 OPAL_XIVE_ANY_CHIP = 0xffffffff,
1109 };
1110
1111 /* Xive sync options */
1112 enum {
1113 /* This bits are cumulative, arg is a girq */
1114 XIVE_SYNC_EAS = 0x00000001, /* Sync irq source */
1115 XIVE_SYNC_QUEUE = 0x00000002, /* Sync irq target */
1116 };
1117
1118 /* Dump options */
1119 enum {
1120 XIVE_DUMP_TM_HYP = 0,
1121 XIVE_DUMP_TM_POOL = 1,
1122 XIVE_DUMP_TM_OS = 2,
1123 XIVE_DUMP_TM_USER = 3,
1124 XIVE_DUMP_VP = 4,
1125 XIVE_DUMP_EMU_STATE = 5,
1126 };
1127
1128 /* "type" argument options for OPAL_IMC_COUNTERS_* calls */
1129 enum {
1130 OPAL_IMC_COUNTERS_NEST = 1,
1131 OPAL_IMC_COUNTERS_CORE = 2,
1132 OPAL_IMC_COUNTERS_TRACE = 3,
1133 };
1134
1135
1136 /* PCI p2p descriptor */
1137 #define OPAL_PCI_P2P_ENABLE 0x1
1138 #define OPAL_PCI_P2P_LOAD 0x2
1139 #define OPAL_PCI_P2P_STORE 0x4
1140
1141 #endif /* __ASSEMBLY__ */
1142
1143 #endif /* __OPAL_API_H */
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