arch/powerpc/include/asm/paca.h

   1 /*
   2  * This control block defines the PACA which defines the processor
   3  * specific data for each logical processor on the system.
   4  * There are some pointers defined that are utilized by PLIC.
   5  *
   6  * C 2001 PPC 64 Team, IBM Corp
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  */
  13 #ifndef _ASM_POWERPC_PACA_H
  14 #define _ASM_POWERPC_PACA_H
  15 #ifdef __KERNEL__
  16
  17 #ifdef CONFIG_PPC64
  18
  19 #include <linux/string.h>
  20 #include <asm/types.h>
  21 #include <asm/lppaca.h>
  22 #include <asm/mmu.h>
  23 #include <asm/page.h>
  24 #include <asm/exception-64e.h>
  25 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
  26 #include <asm/kvm_book3s_asm.h>
  27 #endif
  28 #include <asm/accounting.h>
  29 #include <asm/hmi.h>
  30
  31 register struct paca_struct *local_paca asm("r13");
  32
  33 #if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
  34 extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
  35 /*
  36  * Add standard checks that preemption cannot occur when using get_paca():
  37  * otherwise the paca_struct it points to may be the wrong one just after.
  38  */
  39 #define get_paca()      ((void) debug_smp_processor_id(), local_paca)
  40 #else
  41 #define get_paca()      local_paca
  42 #endif
  43
  44 #define get_lppaca()    (get_paca()->lppaca_ptr)
  45 #define get_slb_shadow()        (get_paca()->slb_shadow_ptr)
  46
  47 /* Maximum number of threads per core. */
  48 #define MAX_SMT         8
  49
  50 struct task_struct;
  51
  52 /*
  53  * Defines the layout of the paca.
  54  *
  55  * This structure is not directly accessed by firmware or the service
  56  * processor.
  57  */
  58 struct paca_struct {
  59 #ifdef CONFIG_PPC_BOOK3S
  60         /*
  61          * Because hw_cpu_id, unlike other paca fields, is accessed
  62          * routinely from other CPUs (from the IRQ code), we stick to
  63          * read-only (after boot) fields in the first cacheline to
  64          * avoid cacheline bouncing.
  65          */
  66
  67         struct lppaca *lppaca_ptr;      /* Pointer to LpPaca for PLIC */
  68 #endif /* CONFIG_PPC_BOOK3S */
  69         /*
  70          * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
  71          * load lock_token and paca_index with a single lwz
  72          * instruction.  They must travel together and be properly
  73          * aligned.
  74          */
  75 #ifdef __BIG_ENDIAN__
  76         u16 lock_token;                 /* Constant 0x8000, used in locks */
  77         u16 paca_index;                 /* Logical processor number */
  78 #else
  79         u16 paca_index;                 /* Logical processor number */
  80         u16 lock_token;                 /* Constant 0x8000, used in locks */
  81 #endif
  82
  83         u64 kernel_toc;                 /* Kernel TOC address */
  84         u64 kernelbase;                 /* Base address of kernel */
  85         u64 kernel_msr;                 /* MSR while running in kernel */
  86         void *emergency_sp;             /* pointer to emergency stack */
  87         u64 data_offset;                /* per cpu data offset */
  88         s16 hw_cpu_id;                  /* Physical processor number */
  89         u8 cpu_start;                   /* At startup, processor spins until */
  90                                         /* this becomes non-zero. */
  91         u8 kexec_state;         /* set when kexec down has irqs off */
  92 #ifdef CONFIG_PPC_STD_MMU_64
  93         struct slb_shadow *slb_shadow_ptr;
  94         struct dtl_entry *dispatch_log;
  95         struct dtl_entry *dispatch_log_end;
  96 #endif /* CONFIG_PPC_STD_MMU_64 */
  97         u64 dscr_default;               /* per-CPU default DSCR */
  98
  99 #ifdef CONFIG_PPC_STD_MMU_64
 100         /*
 101          * Now, starting in cacheline 2, the exception save areas
 102          */
 103         /* used for most interrupts/exceptions */
 104         u64 exgen[13] __attribute__((aligned(0x80)));
 105         u64 exmc[13];           /* used for machine checks */
 106         u64 exslb[13];          /* used for SLB/segment table misses
 107                                  * on the linear mapping */
 108         /* SLB related definitions */
 109         u16 vmalloc_sllp;
 110         u16 slb_cache_ptr;
 111         u32 slb_cache[SLB_CACHE_ENTRIES];
 112 #endif /* CONFIG_PPC_STD_MMU_64 */
 113
 114 #ifdef CONFIG_PPC_BOOK3E
 115         u64 exgen[8] __aligned(0x40);
 116         /* Keep pgd in the same cacheline as the start of extlb */
 117         pgd_t *pgd __aligned(0x40); /* Current PGD */
 118         pgd_t *kernel_pgd;              /* Kernel PGD */
 119
 120         /* Shared by all threads of a core -- points to tcd of first thread */
 121         struct tlb_core_data *tcd_ptr;
 122
 123         /*
 124          * We can have up to 3 levels of reentrancy in the TLB miss handler,
 125          * in each of four exception levels (normal, crit, mcheck, debug).
 126          */
 127         u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
 128         u64 exmc[8];            /* used for machine checks */
 129         u64 excrit[8];          /* used for crit interrupts */
 130         u64 exdbg[8];           /* used for debug interrupts */
 131
 132         /* Kernel stack pointers for use by special exceptions */
 133         void *mc_kstack;
 134         void *crit_kstack;
 135         void *dbg_kstack;
 136
 137         struct tlb_core_data tcd;
 138 #endif /* CONFIG_PPC_BOOK3E */
 139
 140 #ifdef CONFIG_PPC_BOOK3S
 141         mm_context_id_t mm_ctx_id;
 142 #ifdef CONFIG_PPC_MM_SLICES
 143         u64 mm_ctx_low_slices_psize;
 144         unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE];
 145 #else
 146         u16 mm_ctx_user_psize;
 147         u16 mm_ctx_sllp;
 148 #endif
 149 #endif
 150
 151         /*
 152          * then miscellaneous read-write fields
 153          */
 154         struct task_struct *__current;  /* Pointer to current */
 155         u64 kstack;                     /* Saved Kernel stack addr */
 156         u64 stab_rr;                    /* stab/slb round-robin counter */
 157         u64 saved_r1;                   /* r1 save for RTAS calls or PM */
 158         u64 saved_msr;                  /* MSR saved here by enter_rtas */
 159         u16 trap_save;                  /* Used when bad stack is encountered */
 160         u8 soft_enabled;                /* irq soft-enable flag */
 161         u8 irq_happened;                /* irq happened while soft-disabled */
 162         u8 io_sync;                     /* writel() needs spin_unlock sync */
 163         u8 irq_work_pending;            /* IRQ_WORK interrupt while soft-disable */
 164         u8 nap_state_lost;              /* NV GPR values lost in power7_idle */
 165         u64 sprg_vdso;                  /* Saved user-visible sprg */
 166 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 167         u64 tm_scratch;                 /* TM scratch area for reclaim */
 168 #endif
 169
 170 #ifdef CONFIG_PPC_POWERNV
 171         /* Per-core mask tracking idle threads and a lock bit-[L][TTTTTTTT] */
 172         u32 *core_idle_state_ptr;
 173         u8 thread_idle_state;           /* PNV_THREAD_RUNNING/NAP/SLEEP */
 174         /* Mask to indicate thread id in core */
 175         u8 thread_mask;
 176         /* Mask to denote subcore sibling threads */
 177         u8 subcore_sibling_mask;
 178 #endif
 179
 180 #ifdef CONFIG_PPC_BOOK3S_64
 181         /* Exclusive emergency stack pointer for machine check exception. */
 182         void *mc_emergency_sp;
 183         /*
 184          * Flag to check whether we are in machine check early handler
 185          * and already using emergency stack.
 186          */
 187         u16 in_mce;
 188         u8 hmi_event_available;          /* HMI event is available */
 189 #endif
 190
 191         /* Stuff for accurate time accounting */
 192         struct cpu_accounting_data accounting;
 193         u64 stolen_time;                /* TB ticks taken by hypervisor */
 194         u64 dtl_ridx;                   /* read index in dispatch log */
 195         struct dtl_entry *dtl_curr;     /* pointer corresponding to dtl_ridx */
 196
 197 #ifdef CONFIG_KVM_BOOK3S_HANDLER
 198 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
 199         /* We use this to store guest state in */
 200         struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
 201 #endif
 202         struct kvmppc_host_state kvm_hstate;
 203 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
 204         /*
 205          * Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for
 206          * more details
 207          */
 208         struct sibling_subcore_state *sibling_subcore_state;
 209 #endif
 210 #endif
 211 };
 212
 213 #ifdef CONFIG_PPC_BOOK3S
 214 static inline void copy_mm_to_paca(mm_context_t *context)
 215 {
 216         get_paca()->mm_ctx_id = context->id;
 217 #ifdef CONFIG_PPC_MM_SLICES
 218         get_paca()->mm_ctx_low_slices_psize = context->low_slices_psize;
 219         memcpy(&get_paca()->mm_ctx_high_slices_psize,
 220                &context->high_slices_psize, SLICE_ARRAY_SIZE);
 221 #else
 222         get_paca()->mm_ctx_user_psize = context->user_psize;
 223         get_paca()->mm_ctx_sllp = context->sllp;
 224 #endif
 225 }
 226 #else
 227 static inline void copy_mm_to_paca(mm_context_t *context){}
 228 #endif
 229
 230 extern struct paca_struct *paca;
 231 extern void initialise_paca(struct paca_struct *new_paca, int cpu);
 232 extern void setup_paca(struct paca_struct *new_paca);
 233 extern void allocate_pacas(void);
 234 extern void free_unused_pacas(void);
 235
 236 #else /* CONFIG_PPC64 */
 237
 238 static inline void allocate_pacas(void) { };
 239 static inline void free_unused_pacas(void) { };
 240
 241 #endif /* CONFIG_PPC64 */
 242
 243 #endif /* __KERNEL__ */
 244 #endif /* _ASM_POWERPC_PACA_H */