arch/powerpc/include/asm/pci-bridge.h

   1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
   2 #define _ASM_POWERPC_PCI_BRIDGE_H
   3 #ifdef __KERNEL__
   4 /*
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  */
  10 #include <linux/pci.h>
  11 #include <linux/list.h>
  12 #include <linux/ioport.h>
  13 #include <asm-generic/pci-bridge.h>
  14
  15 struct device_node;
  16
  17 /*
  18  * PCI controller operations
  19  */
  20 struct pci_controller_ops {
  21         void            (*dma_dev_setup)(struct pci_dev *dev);
  22         void            (*dma_bus_setup)(struct pci_bus *bus);
  23
  24         int             (*probe_mode)(struct pci_bus *);
  25
  26         /* Called when pci_enable_device() is called. Returns true to
  27          * allow assignment/enabling of the device. */
  28         bool            (*enable_device_hook)(struct pci_dev *);
  29
  30         /* Called during PCI resource reassignment */
  31         resource_size_t (*window_alignment)(struct pci_bus *, unsigned long type);
  32         void            (*reset_secondary_bus)(struct pci_dev *dev);
  33
  34 #ifdef CONFIG_PCI_MSI
  35         int             (*setup_msi_irqs)(struct pci_dev *dev,
  36                                           int nvec, int type);
  37         void            (*teardown_msi_irqs)(struct pci_dev *dev);
  38 #endif
  39
  40         int             (*dma_set_mask)(struct pci_dev *dev, u64 dma_mask);
  41 };
  42
  43 /*
  44  * Structure of a PCI controller (host bridge)
  45  */
  46 struct pci_controller {
  47         struct pci_bus *bus;
  48         char is_dynamic;
  49 #ifdef CONFIG_PPC64
  50         int node;
  51 #endif
  52         struct device_node *dn;
  53         struct list_head list_node;
  54         struct device *parent;
  55
  56         int first_busno;
  57         int last_busno;
  58         int self_busno;
  59         struct resource busn;
  60
  61         void __iomem *io_base_virt;
  62 #ifdef CONFIG_PPC64
  63         void *io_base_alloc;
  64 #endif
  65         resource_size_t io_base_phys;
  66         resource_size_t pci_io_size;
  67
  68         /* Some machines have a special region to forward the ISA
  69          * "memory" cycles such as VGA memory regions. Left to 0
  70          * if unsupported
  71          */
  72         resource_size_t isa_mem_phys;
  73         resource_size_t isa_mem_size;
  74
  75         struct pci_controller_ops controller_ops;
  76         struct pci_ops *ops;
  77         unsigned int __iomem *cfg_addr;
  78         void __iomem *cfg_data;
  79
  80         /*
  81          * Used for variants of PCI indirect handling and possible quirks:
  82          *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
  83          *  EXT_REG - provides access to PCI-e extended registers
  84          *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
  85          *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
  86          *   to determine which bus number to match on when generating type0
  87          *   config cycles
  88          *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
  89          *   hanging if we don't have link and try to do config cycles to
  90          *   anything but the PHB.  Only allow talking to the PHB if this is
  91          *   set.
  92          *  BIG_ENDIAN - cfg_addr is a big endian register
  93          *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
  94          *   the PLB4.  Effectively disable MRM commands by setting this.
  95          *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
  96          *   link status is in a RC PCIe cfg register (vs being a SoC register)
  97          */
  98 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE          0x00000001
  99 #define PPC_INDIRECT_TYPE_EXT_REG               0x00000002
 100 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS  0x00000004
 101 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK          0x00000008
 102 #define PPC_INDIRECT_TYPE_BIG_ENDIAN            0x00000010
 103 #define PPC_INDIRECT_TYPE_BROKEN_MRM            0x00000020
 104 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK      0x00000040
 105         u32 indirect_type;
 106         /* Currently, we limit ourselves to 1 IO range and 3 mem
 107          * ranges since the common pci_bus structure can't handle more
 108          */
 109         struct resource io_resource;
 110         struct resource mem_resources[3];
 111         resource_size_t mem_offset[3];
 112         int global_number;              /* PCI domain number */
 113
 114         resource_size_t dma_window_base_cur;
 115         resource_size_t dma_window_size;
 116
 117 #ifdef CONFIG_PPC64
 118         unsigned long buid;
 119         struct pci_dn *pci_data;
 120 #endif  /* CONFIG_PPC64 */
 121
 122         void *private_data;
 123 };
 124
 125 /* These are used for config access before all the PCI probing
 126    has been done. */
 127 extern int early_read_config_byte(struct pci_controller *hose, int bus,
 128                         int dev_fn, int where, u8 *val);
 129 extern int early_read_config_word(struct pci_controller *hose, int bus,
 130                         int dev_fn, int where, u16 *val);
 131 extern int early_read_config_dword(struct pci_controller *hose, int bus,
 132                         int dev_fn, int where, u32 *val);
 133 extern int early_write_config_byte(struct pci_controller *hose, int bus,
 134                         int dev_fn, int where, u8 val);
 135 extern int early_write_config_word(struct pci_controller *hose, int bus,
 136                         int dev_fn, int where, u16 val);
 137 extern int early_write_config_dword(struct pci_controller *hose, int bus,
 138                         int dev_fn, int where, u32 val);
 139
 140 extern int early_find_capability(struct pci_controller *hose, int bus,
 141                                  int dev_fn, int cap);
 142
 143 extern void setup_indirect_pci(struct pci_controller* hose,
 144                                resource_size_t cfg_addr,
 145                                resource_size_t cfg_data, u32 flags);
 146
 147 extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
 148                                 int offset, int len, u32 *val);
 149
 150 extern int __indirect_read_config(struct pci_controller *hose,
 151                                   unsigned char bus_number, unsigned int devfn,
 152                                   int offset, int len, u32 *val);
 153
 154 extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
 155                                  int offset, int len, u32 val);
 156
 157 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
 158 {
 159         return bus->sysdata;
 160 }
 161
 162 #ifndef CONFIG_PPC64
 163
 164 extern int pci_device_from_OF_node(struct device_node *node,
 165                                    u8 *bus, u8 *devfn);
 166 extern void pci_create_OF_bus_map(void);
 167
 168 static inline int isa_vaddr_is_ioport(void __iomem *address)
 169 {
 170         /* No specific ISA handling on ppc32 at this stage, it
 171          * all goes through PCI
 172          */
 173         return 0;
 174 }
 175
 176 #else   /* CONFIG_PPC64 */
 177
 178 /*
 179  * PCI stuff, for nodes representing PCI devices, pointed to
 180  * by device_node->data.
 181  */
 182 struct iommu_table;
 183
 184 struct pci_dn {
 185         int     flags;
 186 #define PCI_DN_FLAG_IOV_VF      0x01
 187
 188         int     busno;                  /* pci bus number */
 189         int     devfn;                  /* pci device and function number */
 190         int     vendor_id;              /* Vendor ID */
 191         int     device_id;              /* Device ID */
 192         int     class_code;             /* Device class code */
 193
 194         struct  pci_dn *parent;
 195         struct  pci_controller *phb;    /* for pci devices */
 196         struct  iommu_table *iommu_table;       /* for phb's or bridges */
 197         struct  device_node *node;      /* back-pointer to the device_node */
 198
 199         int     pci_ext_config_space;   /* for pci devices */
 200
 201 #ifdef CONFIG_EEH
 202         struct eeh_dev *edev;           /* eeh device */
 203 #endif
 204 #define IODA_INVALID_PE         (-1)
 205 #ifdef CONFIG_PPC_POWERNV
 206         int     pe_number;
 207 #ifdef CONFIG_PCI_IOV
 208         u16     vfs_expanded;           /* number of VFs IOV BAR expanded */
 209         u16     num_vfs;                /* number of VFs enabled*/
 210         int     offset;                 /* PE# for the first VF PE */
 211 #define M64_PER_IOV 4
 212         int     m64_per_iov;
 213 #define IODA_INVALID_M64        (-1)
 214         int     m64_wins[PCI_SRIOV_NUM_BARS][M64_PER_IOV];
 215 #endif /* CONFIG_PCI_IOV */
 216 #endif
 217         struct list_head child_list;
 218         struct list_head list;
 219 };
 220
 221 /* Get the pointer to a device_node's pci_dn */
 222 #define PCI_DN(dn)      ((struct pci_dn *) (dn)->data)
 223
 224 extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
 225                                            int devfn);
 226 extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
 227 extern struct pci_dn *add_dev_pci_data(struct pci_dev *pdev);
 228 extern void remove_dev_pci_data(struct pci_dev *pdev);
 229 extern void *update_dn_pci_info(struct device_node *dn, void *data);
 230
 231 static inline int pci_device_from_OF_node(struct device_node *np,
 232                                           u8 *bus, u8 *devfn)
 233 {
 234         if (!PCI_DN(np))
 235                 return -ENODEV;
 236         *bus = PCI_DN(np)->busno;
 237         *devfn = PCI_DN(np)->devfn;
 238         return 0;
 239 }
 240
 241 #if defined(CONFIG_EEH)
 242 static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
 243 {
 244         return pdn ? pdn->edev : NULL;
 245 }
 246 #else
 247 #define pdn_to_eeh_dev(x)       (NULL)
 248 #endif
 249
 250 /** Find the bus corresponding to the indicated device node */
 251 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
 252
 253 /** Remove all of the PCI devices under this bus */
 254 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
 255
 256 /** Discover new pci devices under this bus, and add them */
 257 extern void pcibios_add_pci_devices(struct pci_bus *bus);
 258
 259
 260 extern void isa_bridge_find_early(struct pci_controller *hose);
 261
 262 static inline int isa_vaddr_is_ioport(void __iomem *address)
 263 {
 264         /* Check if address hits the reserved legacy IO range */
 265         unsigned long ea = (unsigned long)address;
 266         return ea >= ISA_IO_BASE && ea < ISA_IO_END;
 267 }
 268
 269 extern int pcibios_unmap_io_space(struct pci_bus *bus);
 270 extern int pcibios_map_io_space(struct pci_bus *bus);
 271
 272 #ifdef CONFIG_NUMA
 273 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = (NODE))
 274 #else
 275 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = -1)
 276 #endif
 277
 278 #endif  /* CONFIG_PPC64 */
 279
 280 /* Get the PCI host controller for an OF device */
 281 extern struct pci_controller *pci_find_hose_for_OF_device(
 282                         struct device_node* node);
 283
 284 /* Fill up host controller resources from the OF node */
 285 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 286                         struct device_node *dev, int primary);
 287
 288 /* Allocate & free a PCI host bridge structure */
 289 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
 290 extern void pcibios_free_controller(struct pci_controller *phb);
 291
 292 #ifdef CONFIG_PCI
 293 extern int pcibios_vaddr_is_ioport(void __iomem *address);
 294 #else
 295 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
 296 {
 297         return 0;
 298 }
 299 #endif  /* CONFIG_PCI */
 300
 301 #endif  /* __KERNEL__ */
 302 #endif  /* _ASM_POWERPC_PCI_BRIDGE_H */